JPS6027170A - Double diffused insulated gate type fet - Google Patents

Abstract

PURPOSE:To prevent the step cut of wiring at the part of contact by a method wherein polycrystalline Si is buried at the bottom surface of an aperture of the source contact, etc. CONSTITUTION:Source regions 4 and 5 and a channel base region 42 are formed in the surface of a low concentration Si layer 2. The region 42 consists of only a low concentration P layer. A polycrystalline Si layer 41 of low resistance is buried in the aperture of an interlayer insulation film 8. The layer 41 is N type above the regions 4 and 5 and P type above between them. The layer 41 is buried at the entire part in the aperture, the upper surface of the film 8 being even with that of the layer 41 without any stepwise difference, and a source electrode wiring 43 and a gate electrode wiring 44 being then formed thereon.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, particularly a double diffused insulated dart type field effect transistor (hereinafter abbreviated as DMO8).
The present invention relates to the electrode wiring contact portion.

[Technical background of the invention]

Figure 1 (&) shows 1 in an N-channel DMOS chip.
The cross-sectional structure of one unit area (forming area for 81 DMOs) is shown. Here, 1 and 2 are a high-concentration silicon layer and a low-concentration silicon layer, which serve as a drain. A channel base region 3 is formed in a part of the surface of the low-concentration silicon layer 2, and this space region Two source regions 4 and 5 are formed on the surface of the semiconductor device 3, spaced apart from each other. Reference numeral 6 denotes an f-) insulating film (5SO2) formed from the upper surface of the low concentration silicon layer 2 to the center of the upper surface of the source regions 4 and 5, and a film made of polycrystalline silicon or high melting point extra film is formed on the upper surface. A dirt buried layer 7 is formed, and an interlayer insulating film 8. Source electrode wiring 9
．． Dirt electrode wiring 10 is formed. Further, in the space region 3, a high concentration P+ layer 11 is formed to a predetermined depth from the bottom surface between the source regions 4 and 5.

In the DMO 8 having the above configuration, the contact portion between the semiconductor substrate and the source electrode wiring 9 (hereinafter referred to as the source contact portion), the dirt buried layer 7 and the r-to electrode wiring 10
contact part (hereinafter referred to as the dirt contact part)
There are large differences between each. That is, the level difference in the source contact portion is due to the glabella insulating film 8, and f
-) The step difference in the contact portion is caused by the dirt insulating film 6, the dirt buried layer 7, and the interlayer insulating film 8.

Further, in the high concentration P+ layer 11, the ohmic contact between the source electrode wiring 9 and the space region 11 is a drain electrode, G is a dirt electrode, S is a source electrode, and D is a parallel parasitic diode between the source and drain. be.

[Problems with background technology]

By the way, as described above, in the source contact portion and the dirt contact portion, the source electrode wiring 9. When a sudden level difference occurs in the dirt electrode wiring 10, each of the wirings 9 and 10 is thinner in the vicinity of the opening edge of the interlayer insulating film 8, as shown in part A shown in FIG. Cutting (so-called step breakage) is likely to occur. This step breakage causes characteristic deterioration such as a decrease in the current capacity of the electrode wiring and an increase in resistance when the DMO8 is turned on, so in order to prevent this step breakage, the structure shown in Figure 2 or 3 is proposed. has been done. That is, in the DMO 8 in FIG. 2, the interlayer insulating film 8
When photo-etching the contact hole opening, the etching rate is varied in the direction of the depth of the glabellar insulating film 8 by a thickness of 74 mm, so that the inner peripheral surface of the opening is sloped. However, in the DMO 8 shown in FIG. 3, the interlayer insulating film 8
Photo-etching is performed to create two to several steps of variation on the inner peripheral surface of the opening.

In the DMO8 structure shown in FIGS. 2 and 3, the dimensions of the DMO8 forming opening formed in the dirt buried layer 7 (L in FIG. 1) are determined by etching accuracy, slope width, and positioning accuracy during photoetching. It is necessary to take this into account and increase the size. However, this generally means that DMO8 makes the most effective use of the main surface of the substrate.
This is contrary to the particular need to increase the density and increase the dart circumference.

As shown in FIG. 2, another method for forming a slope in the opening of the interlayer insulating film 7 is to form the glabella insulating film 8 using a high concentration PSG film or a BPSG film, and to There is a method in which an opening is formed vertically by etching, and then a slope is formed within the opening by melting by high temperature treatment. However, this method also has the disadvantage of requiring an increase in the size of the opening for forming the DMO 8, and furthermore, the N-type impurity is diffused from the glabella insulating film 8 into the exposed portion of the silicon substrate during the high temperature treatment. Another drawback is that the silicon substrate reacts with the atmosphere N2, making it impossible to make sufficient contact between the space region 3 and the source electrode wiring 9.

In addition, the high concentration P+ layer 11 required in the channel space region 3 increases the forward voltage drop (VF) of the parasitic diode D, lengthens the reverse recovery time (trr), and deteriorates the high frequency characteristics of the DMO 8. There are drawbacks to doing so.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is a double diffusion insulating dart that can prevent wiring breaks at electrode wiring contact portions and improve high frequency characteristics by reducing the forward voltage drop of parasitic diodes. A type field effect transistor is provided.

[Summary of the invention]

That is, the present invention provides a double diffused insulated dirt field effect transistor in which a polycrystalline silicon layer is buried at least in the bottom surface of the opening of the source contact part and the dirt contact part, and the channel part source region is formed only with a lightly doped impurity layer. It is characterized by:

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

The DMO 8 shown in FIG. 4 differs from the DMO 8 described above in FIG. The difference is that the space area 42 is composed of only a low concentration P layer and does not have a high concentration P+ layer (see FIG. 11), but the other parts are the same, so the same reference numerals are given and the explanation thereof will be omitted. , the different points will be explained in detail below.

That is, among the openings of the interlayer insulating film 8? - The polycrystalline silicon 41 buried in the opening on the substrate buried layer 7 is of N type, and the upper part of the source regions 4 and 5 of the polycrystalline silicon layer 41 buried in the opening on the silicon substrate is The upper portion between the source regions 4 and 5 is of P type. In this example, the polycrystalline silicon layer 41
is buried in almost the entire part of each of the openings, so that the upper surface of the interlayer insulating film 8 and the polycrystalline silicon layer 4
1 is a flat surface with no step, and a source electrode wiring 43 and a dirt electrode wiring 44 are formed on this flat surface.

Next, an example of the manufacturing process of the DMO 8 will be described with reference to FIGS. First, Figure 5 (,
), a dirt oxide film 6 is formed on a silicon substrate, a dirt buried layer 7 is formed thereon, and then a DMO
8 formation area is opened by patterning. Next, a channel space region 42 and source regions 4 and 5 are formed in the silicon substrate from the mother turning opening by high-temperature thermal diffusion. That is, double diffusion by self-reading is performed to form a DMO8eff structure. Next, an interlayer insulating film 8 is formed by a CvD (chemical vapor deposition) method, and multiple openings are formed in portions corresponding to contact portions by a photolithography method. Next, as shown in FIG. 5(b), an undoped polycrystalline silicon layer 41 is deposited on the surface by CVD. Next, the fifth
As shown in Figure (c), a photo-etching resist 51 is applied to the surface. In this case, it adheres thickly to the valleys of the steps on the surface of the polycrystalline silicon layer 410 and thinly adheres to the peaks. next,
The resist 51 and the polycrystalline silicon layer 41 are etched down to the surface of the interlayer insulating film 8 using a reactive ion etching device. As a result, the polycrystalline silicon layer 41 is buried only in the opening of the glabella insulating film 8, and the surface of the interlayer insulating film 8 is flattened without any steps. Next, as shown in FIG. 5(d), a photo-etching resist 52 is applied to the surface.
A portion corresponding to the dirt contact portion and a portion corresponding to the upper portion of the source region of the source contact portion are opened. Then, ions of arsenic, for example, are implanted through this opening. Next, as shown in FIG. 5(,), a photo-etching resist 53 is applied to the surface, and an opening is formed in a portion corresponding to the upper part between the source regions of the source contact portion. Perform ion implantation. Then, an annealing process is performed to convert the ion-implanted polycrystalline silicon layer 41 into an electrode. As a result, the arsenic ion-implanted portion of the polycrystalline silicon layer 41 is Nm
Tonashi,? The portion into which the ions are implanted becomes P type. Next, the resist 53 is removed and the metal film (for example, aluminum) is removed.
is deposited, and by photolithography, source electrode wiring 43 and dirt electrode wiring 44 are formed as shown in FIG.

Note that the ion implantation process shown in FIG. 5(d) and the ion implantation process shown in FIG.
The order of the ion implantation steps shown in , ) may be changed.

In the DMO 8 having the above-described structure, the electrode wiring contact portion is flattened, so that no breakage occurs. As a result, the current capacity of the wiring increases and D
The inside of the MOS Chizzo chip will work effectively, D
No increase in resistance or concentration of current occurs when MO8 is turned on. Furthermore, due to the flattening described above, DMOS
Is it possible to make a wire connection between the O8 operating section in the chip and the device envelope, which was made outside the DMO8 operating section in conventional chips? The landing pad area becomes unnecessary. This expands the DMO8 operating area within the chip, improving the degree of integration of the DMO8, increasing the overall dirt perimeter (dart channel width), reducing the on-resistance of the DMO8, and realizing higher power. It becomes possible.

In addition, in the source contact portion, the source electrode wiring 4
3 is in contact with the silicon substrate via a low resistance polycrystalline silicon layer 41. Therefore, even if the channel space region 42 is a low concentration P layer, the source electrode wiring 43
It is possible to make ohmic contact with the conventionally required high-concentration P layer. As a result, the potential barrier for carriers passing from the N layer (low concentration silicon layer 2) in the silicon substrate to the source electrode wiring 43 via the low concentration P layer (space region 42) is lowered, and the forward voltage drop characteristics in the parasitic diode are reduced. Since the accumulation of minority carriers is reduced, the reverse recovery time is shortened, and the high frequency characteristics are improved, making high-speed operation possible.

Furthermore, Figure 6 shows a large number of DMs formed in the DMOS chip.
O8 (the structure of one unit of which was described above with reference to Figure 4)
The equivalent circuit of 611 to 61n is shown below, and each DMO8
The resistance r at 611 to 61n is the low resistance of the polycrystalline silicon layer 41 buried in the opening of the glabellar insulating film of the source contact portion. Normally, there are variations in the threshold voltage of each DMO8 between the center and the periphery within the same chip.
Although it is easy to cause current concentration in some DMO8 and its parasitic diodes, set the value of the resistor r appropriately (DM
(There is a balance between the on-resistance of O8 and the forward voltage drop characteristic of the parasitic diode), it becomes possible to provide an effect as a stabilizing resistor, and it becomes possible to expand the safe operation area of DMO8.

Furthermore, the present invention is not limited to the above-mentioned embodiments, but instead of burying a low-resistance polycrystalline silicon layer from the bottom of the opening of the interlayer insulating film to the opening surface, Just by embedding, the level difference in the electrode wiring can be reduced and 4-ohmic contact between the silicon substrate and the electrode wiring can be obtained.

Although the above embodiment shows an N-channel type DMO 8, it goes without saying that the present invention can also be applied to a P-channel type DMO8.

〔Effect of the invention〕

As described above, according to the double-diffused insulated dart type field effect transistor of the present invention, it is possible to prevent disconnection of the wiring at the electrode wiring contact part, and the flattening of the electrode wiring surface allows wire bonding connection on the transistor operating part. Therefore, high integration can be achieved. Furthermore, since the channel base region can be formed only with a lightly doped impurity layer, the forward voltage drop of the parasitic diode can be reduced, the reverse recovery time can be shortened, and the high frequency characteristics can be improved. However, by appropriately setting the resistance value of the polycrystalline silicon layer embedded in the electrode wiring contact portion, current concentration in the transistor due to manufacturing variations can be prevented and the safe operating range can be expanded.

[Brief explanation of the drawing]

Figure 1(,) is a cross-sectional view showing the structure of a conventional double-diffused insulated dart field effect transistor, and Figure 1(b) is the same figure ().
2 and 3 are cross-sectional views showing the structure of a conventional double-diffused insulated f-) type field effect transistor, and FIG. 4 is a circuit diagram showing an equivalent circuit of the transistor of the present invention. Cross-sectional views showing the structure of an embodiment of a diffusion-insulated dart type field effect transistor, FIGS.
, ) are cross-sectional views showing the structure of the transistor shown in FIG. 4 in the manufacturing process, and FIG. 6 is a circuit diagram showing an equivalent circuit of each transistor in a chip in which the transistor shown in FIG. 4 is formed. 1.2... Silicon layer, 4, 5... Source region, 6
... Gate oxide film, 7... Dirt buried layer, 8.
...Interlayer insulating film, 4th...Polycrystalline silicon layer, 42.
... Channel portion base region, 43... Source electrode wiring, 44... Kate electrode wiring. Applicant's representative Patent attorney Takehiko Suzue Figure 1 <a) (b) Figure 2 Figure 3 Figure 4 Figure 6

Claims (1)

[Claims] a silicon substrate of a first conductivity type, a channel portion space region of a second conductivity type opposite to the first conductivity type diffused on a part of the surface of the silicon substrate, and a channel portion base region of the channel portion base region. source regions of a first conductivity type that are diffused and spaced apart from each other on a part of the surface of the silicon substrate; Partially opened r-
) oxide film, a dirt buried layer formed on the upper surface of this dirt oxide film, a portion corresponding to a dirt contact portion formed on the upper surface of the r-) buried layer and the double diffusion region in its opening, and a source contact. a polycrystalline polysilicon layer embedded in at least the bottom part of the opening of the glabellar insulating film and electroded in accordance with the conductivity type of the lower part;
The interlayer insulating film and a metal electrode wiring formed in a predetermined pattern are formed on the upper surface of the opening of the interlayer insulating film, and the steps of the metal electrode wiring are reduced, and the channel source region is formed only with a lightly doped impurity layer. A double-diffusion insulated dart type field effect transistor characterized by high power.