JPS6027168A - Thyristor - Google Patents
ThyristorInfo
- Publication number
- JPS6027168A JPS6027168A JP13503083A JP13503083A JPS6027168A JP S6027168 A JPS6027168 A JP S6027168A JP 13503083 A JP13503083 A JP 13503083A JP 13503083 A JP13503083 A JP 13503083A JP S6027168 A JPS6027168 A JP S6027168A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- layer
- groove
- anode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000010469 Glycine max Nutrition 0.000 description 1
- 244000068988 Glycine max Species 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41716—Cathode or anode electrodes for thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の技術分野］
本発明は、サイリスタに関し、特にゲートに逆バイアス
電圧を印加してターンオフさせるゲート・ターン・オフ
・サイリスタ（以下、ＧＴＯと略記する。）の改良構造
に係るものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a thyristor, and in particular to an improvement of a gate turn-off thyristor (hereinafter abbreviated as GTO) that is turned off by applying a reverse bias voltage to its gate. It is related to the structure.
［発明の技術的背景とその問題点］ 第１図に従来のＧＴＯの一般的な構造を示す。[Technical background of the invention and its problems] FIG. 1 shows the general structure of a conventional GTO.
同図において、ＧＴＯＩのゲート２に順バイアス電圧を
印加すると、ＧＴＯｌはターンオンし、そのオン領域は
ノコソードエミッタ領域幅Ｗｎｅに相当する全領域に広
がり、アノード電流がこのＧ−「０１の固有のラッチン
グ電流以上の鎮にあれば、ゲート２への順バイアス電圧
の印加を解除してもオン状態が持続される。In the same figure, when a forward bias voltage is applied to the gate 2 of the GTOI, the GTOl turns on and its on region spreads over the entire region corresponding to the width Wne of the node emitter region, and the anode current If the current is higher than the latching current, the on state is maintained even if the application of the forward bias voltage to the gate 2 is removed.
その後、ＧＴＯＩのゲート２に逆バイアス電圧を印加づ
ると、カソードエミッタ領域３のグー１〜電ｔ！ｉ２に
最も近い部分、づ゛なわら最も深く逆バイアスされてい
る部分からターンオフして行き、オン領域は次第にカソ
ードエミッタ領域３の中央部へと収縮しで行く。そして
最終的には、」−記のオン領域が非常に幅の狭い一本の
線状の領域となり、かかる部分での電流密度がきわめて
＾くなる。After that, when a reverse bias voltage is applied to the gate 2 of the GTOI, the voltage t! The turn-off starts from the part closest to i2, that is, the part that is most deeply reverse biased, and the on region gradually shrinks to the center of the cathode emitter region 3. In the end, the ON region indicated by "-" becomes a very narrow linear region, and the current density in this region becomes extremely low.
また、その部分の電流集中に伴い接合部温度が非常に高
くなる等により可制御陽極電流があまり大きくならない
という問題があった。In addition, there is a problem in that the controllable anode current does not become very large because the junction temperature becomes extremely high due to current concentration in that part.
また、この構造で可制御陽極電流を大きくしようとする
と、島状に分割したカソード・エミッタ領域３の幅を狭
くし、その島状カソード・エミッタ領域３の本数を増や
す必要があるが、この方法によると、シリコンペレット
の有効面積率、すなわち、総力ソードエミッタ面積をシ
リコンペレット全体の面積で除した値が減少してしまい
、定常状態でのオン電圧およびサージ電流耐量に悪影響
を及ぼす欠点があった。In addition, in order to increase the controllable anode current with this structure, it is necessary to narrow the width of the island-shaped cathode/emitter regions 3 and increase the number of island-shaped cathode/emitter regions 3. According to , the effective area ratio of the silicon pellet, that is, the value obtained by dividing the total force sword emitter area by the area of the entire silicon pellet, decreased, which had a negative effect on the on-voltage and surge current withstand capacity in steady state. .
ＧＴＯの上記欠点を改良する方法として以下のようない
くつかの方法が提案されているがいずれも最良のものと
なっていなかった。Several methods have been proposed to improve the above-mentioned drawbacks of GTO, but none of them have been the best.
例えば、特公昭４２−２１９７８号に示すようにカソー
ド・エミッタ電極に対応するアノード側のＰ層を形成し
ない欠損部を設けたり、Ｎベース層をアノード側の表面
にまで延在さＵたりしｌｃ構造のものがある。しかし、
この構造ではＧＴＯのオフ時におけるアノード・カソー
ド間に逆電圧が印加された時のＮベース領域内の空乏層
の広がりから逆電圧があまり高くできない欠点を有する
。For example, as shown in Japanese Patent Publication No. 42-21978, a defect is provided on the anode side corresponding to the cathode/emitter electrode where no P layer is formed, or an N base layer is extended to the surface of the anode side. There is a structure. but,
This structure has a drawback that the reverse voltage cannot be increased very much because the depletion layer in the N base region expands when a reverse voltage is applied between the anode and the cathode when the GTO is off.
また、伯の改良として、例えば、実公昭４４−１１９３
７号に示されているようにカソード・エミッタ電極に対
応するアノード側のＰ層表面に絶縁膜を形成し、その上
に金属電極層を形成した構造が提案されている。しかし
、この構造においても以下のような欠点を有づる。In addition, as an improvement of Haku, for example,
As shown in No. 7, a structure has been proposed in which an insulating film is formed on the surface of the P layer on the anode side corresponding to the cathode/emitter electrode, and a metal electrode layer is formed thereon. However, this structure also has the following drawbacks.
不純物拡散によって形成されたアノード側のＰ層の結晶
内の横方向抵抗は、表面に近いところ程低い。このため
Ｐ層表面に絶縁層を形成してもカソード・エミッタ電極
下方の電流密度は期待した程小さくならない。The intracrystalline lateral resistance of the anode-side P layer formed by impurity diffusion is lower as it approaches the surface. For this reason, even if an insulating layer is formed on the surface of the P layer, the current density below the cathode/emitter electrode does not become as small as expected.
［発明の目的］
本発明は、上記の事情に基づきなされたもので、中心部
の電力密度を効果的に緩和させ、可制御陽極電流を大ぎ
くしたゲート・ターン・Ａノ・サイリスタを提供づるこ
とを目的とする。[Object of the Invention] The present invention has been made based on the above-mentioned circumstances, and an object thereof is to provide a gate turn A thyristor in which the power density in the center part is effectively relaxed and the controllable anode current is greatly increased. purpose.
「発明の概要」
本発明は、−導電型を有する第１導電層と、この第１導
電廟に隣接して形成した前記第１導電層と反対導電型の
第２導電層と、この第２導電層に隣接して形成した前記
第１導電層と同じ導電型の第３導電層と、この第３導電
層内に選択的に形成した前記第２１電層と同じ導電型の
第４導電層と、この第４導電層に対向する箇所の前記第
１導電層の表面に形成した前記第４導電層側に向う溝を
形成し、この溝の表面を覆う絶縁層と、前記第１導電層
、第３導ＮＮおよび第４導電層にそれぞれ第１電極、第
２電極およびゲート電極とを設けたことを特徴とするサ
イリスタであって中心部への電力密度の集中を効果的に
緩和できるようにし、可制御陽極電流を大きくなるよう
にしたものである。"Summary of the Invention" The present invention provides a first conductive layer having a - conductivity type, a second conductive layer formed adjacent to the first conductive layer and having a conductivity type opposite to the first conductive layer, and a second conductive layer having a conductivity type opposite to the first conductive layer. a third conductive layer of the same conductivity type as the first conductive layer formed adjacent to the conductive layer; and a fourth conductive layer of the same conductivity type as the twenty-first conductive layer selectively formed within the third conductive layer. and a groove facing the fourth conductive layer formed on the surface of the first conductive layer at a location opposite to the fourth conductive layer, an insulating layer covering the surface of this groove, and the first conductive layer. , a thyristor characterized in that the third conductive NN and the fourth conductive layer are provided with a first electrode, a second electrode, and a gate electrode, respectively, so that concentration of power density in the center can be effectively alleviated. The controllable anode current is increased.
［発明の実施例］ 第２図は、本発明の一実施例を示す断面図である。[Embodiments of the invention] FIG. 2 is a sectional view showing one embodiment of the present invention.
同図において、ＧＴＯｌｌは、第１図と同様に例えばＰ
型筒１１電層１２と、この第１導電層１２に隣接して形
成した［１型の第２導電層１３と、この第２導電層１３
に隣接して形成したＰ型の第３導電層１４と、この第３
導電層１４内に選択的に形成した幅Ｗｎｅなるｎ型の第
４導電層１５とを有１′る。そしてこの第４導電層１５
に対向する第１導電層１２の表面部分には公知の方法で
幅ｗ１深さｄなる溝を形成し、その後例えばシリコン酸
化膜からなる絶縁層１６を形成し、この絶縁層１６で覆
われてた部分は、第１導電８１２上に設けられたアノー
ド金属Ｎ極１７と電気的に分離された構造とする。In the figure, GTOll is, for example, P
A mold cylinder 11 conductive layer 12 , a second conductive layer 13 of type 1 formed adjacent to this first conductive layer 12 , and a second conductive layer 13 formed adjacent to this first conductive layer 12 .
a P-type third conductive layer 14 formed adjacent to the third conductive layer 14;
An n-type fourth conductive layer 15 having a width Wne is selectively formed within the conductive layer 14. And this fourth conductive layer 15
A groove having a width w1 and a depth d is formed in the surface portion of the first conductive layer 12 facing the surface by a known method, and then an insulating layer 16 made of, for example, a silicon oxide film is formed, and the groove is covered with this insulating layer 16. This portion has a structure that is electrically isolated from the anode metal N pole 17 provided on the first conductor 812.
なお、第３導電層１４、第４導電層１５上には、それぞ
れゲート電極１８、カソード電極１９が設けられる。Note that a gate electrode 18 and a cathode electrode 19 are provided on the third conductive layer 14 and the fourth conductive layer 15, respectively.
上記の構造において、Ｇ、ＴＯｌｌのゲート電極１８を
負バイアスし、ターンオフさせると、そのターンＡ）領
域は通常のＧＴＯと同様に第４導電層１５、すなわちア
ノード・エミッタ領域の表面部分に前記の絶縁層１６が
存在するので、この絶縁Ｎ１６の部分に電流が集中しよ
うとしても、かかる部分の横方向抵抗の存在によりカソ
ード・１ミツタ領域の図示ｘ−Ｘ線で示す中央部分への
電流集中が阻止される。さらにこれを詳しく説明づれば
、アノード・エミッタ領域の横方向抵抗部分が欠損して
いて溝の底の部分の横方向抵抗が表面部分に較べて高い
のでかかる部分への電流の流れが阻止されることとなる
。したがって、この構造のＧＴＯで最も電流密度の高い
領域は、上記溝１６の両端ａ、ｂ付近に各々発生し、二
本の線状領域の内側へ向って一定の電流密度の勾配を持
って広がっている。In the above structure, when the gate electrode 18 of G, TOll is turned off by applying a negative bias, the turn A) region is formed on the surface of the fourth conductive layer 15, that is, the anode/emitter region, as in a normal GTO. Since the insulating layer 16 exists, even if the current tries to concentrate in the insulating layer N16, the current will not concentrate in the central part of the cathode 1st region shown by the line x-X in the figure due to the lateral resistance of this part. blocked. To explain this in more detail, the lateral resistance portion of the anode/emitter region is missing and the lateral resistance of the bottom portion of the groove is higher than that of the surface portion, so current flow to this portion is blocked. becomes. Therefore, in a GTO with this structure, the regions with the highest current density occur near both ends a and b of the groove 16, and spread toward the inside of the two linear regions with a constant current density gradient. ing.
上記の構造によれば、従来のＧＴＯの構造に較べ、電力
密度の集中を効果的に緩和でき、可制御電流を大きくす
ることができる。According to the above structure, the concentration of power density can be effectively alleviated and the controllable current can be increased compared to the conventional GTO structure.
なお、上記の効果を得るための溝の形成方法には次のい
ずれの方法でも良い。Note that any of the following methods may be used to form the grooves to obtain the above effect.
（１）図示の溝１６の深さｄをアノード・エミッタ領域
中の不純物濃度がかなり低いところまで深くし、溝１６
の底に対向するアノード・エミッタ領域部分の抵抗率を
高く取り、溝１６の幅Ｗは、比較的狭くとも必要な抵抗
値かえられる構造とすること。(1) The depth d of the groove 16 shown in the figure is increased to a point where the impurity concentration in the anode emitter region is quite low, and the groove 16
The resistivity of the anode/emitter region portion facing the bottom of the groove 16 is set high, and the width W of the groove 16 is structured so that the required resistance value can be changed even if it is relatively narrow.
（２）溝１６の深さｄは、比較的浅く取り、幅Ｗを前記
（１）よりも広くして必要な抵抗を得ること。(2) The depth d of the groove 16 should be relatively shallow, and the width W should be wider than in (1) above to obtain the necessary resistance.
「発明の効果」
本発明は、上記のようにカソード・エミッタ領域の中央
部分に対向するアノード・エミッタ領域の表面部分に満
を形成し、その表面部分に絶縁層を形成するようにした
ので、カソード・エミッタ領域の中央部分への電力集中
が効果的に緩和でき、その結果、可制御陽極電流が大き
くなる。"Effects of the Invention" In the present invention, as described above, a filler layer is formed on the surface portion of the anode emitter region opposite to the central portion of the cathode emitter region, and an insulating layer is formed on the surface portion. Power concentration in the central part of the cathode-emitter region can be effectively alleviated, resulting in a larger controllable anode current.
また、アノード・エミッタ・ショート構造では、逆耐圧
がゲート・カソード間耐圧のみ低い値になってしまうが
、本発明の構造では順耐１■と同等の逆耐圧を得ること
ができる。Further, in the anode-emitter short structure, only the gate-cathode breakdown voltage has a low reverse breakdown voltage, but the structure of the present invention can obtain a reverse breakdown voltage equivalent to the forward breakdown voltage 1.
第１図は、従来の０１−０の構造の一例を示Ｊ断面図、
第２図は、本発明に係るＧＴＯの構造を示す断面図であ
る。
１１・・・Ｇ−１０
１２・・・第１尋電層
１３・・・第２導電層
１４・・・第３導電層
１５・・・第４導電層
１６・・・溝
１７・・・アノード金属電極
１８・・・ゲート電極
特許出願人
神奈川県秦野市曽屋１２０４番地Figure 1 shows an example of the structure of the conventional 01-0;
FIG. 2 is a sectional view showing the structure of the GTO according to the present invention. 11...G-10 12...First conductive layer 13...Second conductive layer 14...Third conductive layer 15...Fourth conductive layer 16...Groove 17...Anode Metal electrode 18... Gate electrode patent applicant 1204 Soya, Hadano City, Kanagawa Prefecture
Claims (1)
接して形成した前記第１導Ｎ層と反対導電型の第２導電
層と、この第２導電層に隣接して形成した前記第１導電
層と同じ導電型の第３導電層と、この第３導電層内に選
択的に形成した前記第２導電層と同じ導電型の第４導電
層と、この第４導電層に対向する箇所の前記第１導Ｎ層
の表面に形成した前記第４導電層側に向う溝表面を覆う
絶縁層と、前記第１導劃り第３導Ｎ層および第４導電層
にそれぞれ第１電極、第２電極およびゲート電極とを設
けたことを特徴とするサイリスタ。a first conductive layer having one conductivity type; a second conductive layer formed adjacent to the first conductive layer and having an opposite conductivity type to the first conductive layer; a third conductive layer of the same conductivity type as the first conductive layer formed in the third conductive layer; a fourth conductive layer of the same conductivity type as the second conductive layer selectively formed within the third conductive layer; an insulating layer covering the surface of a groove facing the fourth conductive layer formed on the surface of the first conductive N layer at a location facing the conductive layer; and the first conductive third conductive N layer and the fourth conductive layer. A thyristor characterized in that each of the thyristors is provided with a first electrode, a second electrode, and a gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13503083A JPS6027168A (en) | 1983-07-22 | 1983-07-22 | Thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13503083A JPS6027168A (en) | 1983-07-22 | 1983-07-22 | Thyristor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027168A true JPS6027168A (en) | 1985-02-12 |
Family
ID=15142296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13503083A Pending JPS6027168A (en) | 1983-07-22 | 1983-07-22 | Thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027168A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0672116U (en) * | 1993-03-24 | 1994-10-07 | 有限会社イワサキ | Marker lamp structure |
-
1983
- 1983-07-22 JP JP13503083A patent/JPS6027168A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0672116U (en) * | 1993-03-24 | 1994-10-07 | 有限会社イワサキ | Marker lamp structure |
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