JPS6027043A - Memory extending method - Google Patents

Abstract

PURPOSE:To attain switching of areas from any area and to facilitate programming by forming the physical space of a memory which is controlled by a microprocessor with an fixed area, plural switching areas and shared areas belonging to these switching areas. CONSTITUTION:The physical space of a memory space of a memory system contains a fixed area S01, (n) units of switching regions S11-Sn1 and shared areas S12-Sn2 included in said switching areas on the physical space. For a logical address data supplied to a memory control circuit, a memroy selection MS01 is set at 1 with use of the data a1 which selects the fixed area or the switching area, the data a2 which selects the present switching area or the shared area, data a3 and a4 on the addresses of switching and shared areas and the data I/E showing the reading/writing cycles of a memory and as long as the data a1 is within the fixed area. Thus a memory 13 is selected and an address is decided by data a3 and a4. If the a1 is outside the fixed area, memories S14 and S15 which constitute switching and shared areas are selected.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a memory expansion method for expanding the capacity of memory controlled by a microprocessor.

In general, in systems using microprocessors, there are cases where the memory capacity must be larger than the maximum address space of the microprocessor.

Conventionally, a bank switching method has been known as a memory expansion method in such a case.

This bank switching method will be explained with reference to FIG. In this example, the maximum address space is 64 (bytes (00001
1 to FFFFII) microprocessor, 9
This is an example in which a memory having a capacity of 6 bytes is controlled.

In other words, the physical space in the RAM memory space of 96 Kbytes is divided into 32 bytes and one fixed area (bank).
Two switching areas (banks) 3 with by 1- on #0 and 3'2
1. Address space (logical space) 171
000011 to 8000+1 to the fixed area #o, and AOOOII-FFFF11 to the switching area #l, tt
It can be divided into 2.

And switching area #I having a common address space.

Switching #2 is performed by executing a bank switching instruction and rewriting the contents of the bank switching register.

However, in such a memory expansion method,
For example, if switching area #1 is currently selected and you want to switch the bank from this state to switching area #2, first select the fixed area #1.
0, and then execute the instruction to switch to switching area #2. Since it is not possible to directly transfer instruction control from switching area #1 to switching area #2, the program will not be duplicated. It becomes 1t.

Furthermore, since the programmer 11 is required to write bank switching data into a register for bank switching, there is also a problem in that the program becomes complicated.

Furthermore, a fixed area tt containing instructions for switching banks.
Program instructions and data can be mutually referenced between O and the controlled switching area 711 or switching area #2, but they cannot be directly referenced between switching area #1 and switching area #2. I can't do it.

OBJECT This invention was made in view of the above points, and an object of the present invention is to simplify programming when expanding memory capacity by the above-described bank switching method.

I Sodandan Shizokuko Hereinafter, the configuration of the present invention will be explained based on one embodiment.

FIG. 2 is a memory map diagram showing one embodiment of the present invention.

Referring to the figure, in this memory system, first, the physical space in the memory space is divided into one fixed area S. 1
and n switching areas Sll to S+n and shared areas SI2 to included in each of the switching areas Sll to Snl in the physical space.
It is composed of Sn2.

Then, the address space of the microprocessor (logical space 1
fJ) is a fixed area S in physical space. I, one switching area Sn+ (n=1...n), and each switching area S'l
It is allocated to each shared area S12 to Sn2 of l to Snl.

Here, the relationship between logical space and physical space will be explained.

The number of switching areas that make up the physical space is inversely proportional to the size of the shared area that belongs to the switching area.

That is, if the entire logical space is SL, then SL =
S 01 +S, n +S 12,313. However, 313 is a shared area S22 to other than shared area 8-kan 2.
It means a mixture of Sn2.

On the other hand, if the entire physical space is SP, then SP:=So++n (SIl+5I2). However, I] means the number of switching areas.

Therefore, the logical space SL is.

5L=SO++S+++nS+2, where S, I=nS 12,
511=(SL-3oI)/2 SI2=(Sl--3ot)/2n, so the physical space SP becomes sP:so++(SL+5OI)/2+(SL+5(B)·n/2).

Next, access to the memory configured in this way will be explained.

FIG. 3 is a block diagram of essential parts showing an example of a control circuit of this memory system.

In the figure, first, the logical address data input to this memory control circuit includes data a1 for selecting either a fixed area or a switching area (including a shared area), and data a1 for selecting either a fixed area or a switching area (including a shared area), and data a1 for selecting either a fixed area or a switching area (including a shared area), and a If a switching area is specified by data a2 and this ' data row 2, it becomes an address in the switching area, and if a shared area is specified, the shared area is determined, and the shared area is It consists of data a:]+84, which is the address within. In addition,
It is assumed that data a2 is set to "o" when selecting the switching area.

Data I/E indicating whether or not it is a memory read/write cycle (E cycle) is also input to this control circuit. Note that this data T/E is 0 during the E cycle.
”.

Next, comparator 1 calculates data a in the address space.
1, and compares the contents of this data a1 with the data SQL corresponding to the final address of the fixed area SQL set in advance by the DIP switch or the I10 command, and
> If So, set memory select h M So + to 1
”.

AND circuit 2 selects memory select l from comparator 1.
-M So is input via inverter B, and data a2 is input via inverter 4.

The AND circuit 5 selects the memory select l-M of the comparator 1.
S o is manually input via the inverter 3 , and data a2 is input via the inverters 4 and 6 .

The memory (switching register) 7 inputs the output of the AND circuit 5 and the output of the AND circuit 8 which inputs the data I/E,
When the output is 1'', data a3 is captured and stored.

Decoder 9 decodes data a3 stored in memory 7, and decoder 10 decodes input data a3.

The AND circuit 11 inputs the output of the AND circuit 2 and the output for selecting the switching area S11 from the decoder output, and outputs the memory select l' M Su.

The AND circuit 12 outputs the output of the AND circuit 5 and the decoder 1.
Output for selecting the shared area SI2 of the switching area Sl+ among the outputs of 0 is input, and a memory select MS, □ is output.

The memory 16 is a fixed area S. 1 and is selected when the memory select M So from comparator 1 is 1'', and the data aI ta2 ra3 ta4
Input the data asoI synthesized with the data a3,
4 specifies the address.

The memory 14 constitutes the switching area S11, and the AND circuit 1
Memory select MS from 1 is selected when the port is 1'', and data as11 is a composite of data a3+84.
is input, and the address is specified using the data a3ra4.

The memory 15 constitutes a shared area 312, and the AND circuit 1
2 is selected when the memory select M'S12 is 1'', data a4 is input as data as1□, and an address is specified by the data a4.

Note that the other output of the decoder 9 is a memory select hMsn+(wa;2...rr) for selecting a memory forming another switching area Sr++ (n=2...n) not shown.
) is input to an AND circuit similar to the AND circuit VP111.

Further, the other output of the decoder 10 is a memory select l-M S r12 (
n = 2...n), the AND circuit 12
is input to an AND circuit similar to .

Next, the operation of this control circuit configured as described above will be explained with reference to FIG. 4 as well.

First, when the address data is inputted, the comparator 1 determines whether or not the content of the data aI is within the fixed area Sot set in advance. If it is within the fixed area Sot, the comparator 1 Select h M So, is set to 1=.

Thereby, the memory 13 is selected and the data aSO+
The fixed area SOI address (
address) is determined and that address is accessed.

At this time, since the memory select M S 0+ is 1'', the outputs of the AND circuits 2 and 5 to which it is input via the inverter 3 are both ``o'', which is the output of the AND circuits 11 and 12. Memory select MSII#MS
+2 becomes 0'' and memories 14 and 15 are not selected.

On the other hand, the contents of data al are fixed area S. If it is not within 1, memory select of funparator 1 M S 0
1 becomes 0'' and memory 16 is not selected.

At this time, if the data a2 is O'', the output of the AND circuit 2 becomes 1'', while the output of the AND circuit 5 becomes 0.

Therefore, in this case, for example, memory (switching register)
Out of the outputs of the decoder 9 which decoded the contents of data a3 stored in 7, the output to the AND circuit 11 is 1.
”, memory select M S +
+ becomes 1'', and the memory 14 forming the switching area Sll
is selected.

In other words, the contents of the switching register 7 can be used to select multiple switching areas Sll.
~S1] One of the switching areas is determined (selected).

Then, data a3 + 84 constituting the data aSH input to the memory constituting the determined switching area
The address of the switching area is determined and accessed.

If the data a2 is the same, the output of the AND circuit 2 will be '0', and the output of the AND circuit 5 will be '0'.

Therefore, at this time, for example, if the output to the AND circuit 12 among the outputs of the decoder 1o that decoded the data a3 is 1'', the memo+J select/hMs+2 is
'', and the memory 15 constituting the shared area S12 of the stump area Sl+ is selected.

In other words, multiple switching areas Sll to n are created based on the content of data a3.
The shared area within fL is determined.

Then, data a4, which is data as12, input into the memory configuring the shared area of this determined switching territory J attack.
The address of the shared area is determined and accessed.

The analysis result of the instruction at this time is JMP.

In a phase such as CALL, data I/E becomes I'' unless it is an E cycle, so data a, ] is taken into the memory 7 and stored.

On the other hand, in the E cycle, data ■7E is O''
Therefore, the data a3 is not taken into the memory 7.

In other words, the contents of the memory (switching register) are not changed during the read/write cycle.

In this way, for example, if the contents of the current switching register specify the switching area Sll, the fixed area Sol
Instructions in the fixed area SOI+switchable area SI+++shared area S12) S22t532pSn2 can be accessed from Ren Cheng.

The contents of the switching register are not changed when reading/writing to/from the memory is performed by executing an instruction.

Also, the fixed area S. 1. Switching area Sl+ and shared area S
Even when control of the instruction is transferred to I2, the contents of the switching register are not changed.

On the other hand - C1 shared area"' 221 S! l
When control of the instruction is transferred to Sn2, the contents of the switching register are changed to the contents of data a3, and the IJJ switching area indicated by the data a3 is selected. .

Note that the switching area S11. Shared area S121 b 22
.

Regarding the command in S 32 + ”', +12,
1 V! It can be accessed from each area in the same way as instructions in one fixed area SOI.

For example, the shared area 5112 (11=2・
By storing data a, I, and data a4 in . . . n), it becomes possible to automatically select a desired switching area.

In other words, there is no need for an instruction to control switching of the switching area, and switching can be controlled automatically at an address where an execution command is located or an address where data is referenced.

Further, it is possible to directly refer to program commands and data between cut V areas.

As described above, by implementing the memory expansion method according to the present invention, switching of switching areas can be performed by directly transferring control from a - switching area to a shared area that is subject to other switching areas.

This eliminates the need to explicitly select the switching area in the program, and by setting common data, stack, and linkage instructions in the fixed area and shared area, the switching area can be controlled by the switching program. You can expand the memory space without any problems.

Along with this, it becomes possible to create multi-processing programs without being aware of areas.

As explained above, according to the present invention, it becomes possible to switch areas from any area, making it easier for the programmer 11 to perform mapping registers and bank switching.
There is no need for a program to control the tremor register, and it becomes easier to link programs in physical space.

[Brief explanation of the drawing]

Fig. 1 is a memory map diagram for explaining the bank switching method as a conventional memory expansion method, Fig. 2 is a memory map diagram for explaining the present invention in detail, and Fig. 3 is a memory map diagram for explaining the bank switching method as a conventional memory expansion method. FIG. 4, which is a block diagram of a main part showing an example of the control circuit of the system, is a flow diagram for explaining the operation of the control circuit of FIG. 6. Fig. 1 Fig. 2 Fig. 3 Registration of proceedings with an opening (spontaneous) September 14, 1980 Mr. Kazuo Wakasugi, Commissioner of the Patent Office ■, Special Application for Indication of Small Cases No. 132856 1981 2, Title of the Invention Memory Expansion Method 3, Relationship with the Amendment Person Case Patent Applicant: 1-3-6 Nakamagome, Ota-ku, Tokyo (674) Rico Co., Ltd. - 4, Agent: 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Column 6 of detailed explanation of the invention in the specification, contents of amendment (1) rsp:so on page 5, lines 15-16 of the specification,
, + (SL+5(B)/2+ (SL+So+) ・
n/2J. Correct as follows. 1rsP=s01+n, ((SL 5ot)/2+(S
L-8ob) / 2 n) :SOI+, (SL-8ol) ・n/2+ (SL
-3'o+) /2 = (SL + 5ot)/2+(SL 5at)・
n/2'' (2) 'a+>'So+J in the first line of page 7 of the same book
is corrected as Fat<So+J]. (3) 'a31a4J' on page 8, line 10 of the same book, 1ra
1. Correct as a2+ a3+ a4Jl. (4) Since r “1” in the 4th line of page 12 of the same book,
” becomes If “1”, so it is corrected to J. (5) Correct "switching area" on page 13, line 14 of the same book to "j of switching area."

Claims (1)

[Claims] 1 In a memory expansion method for expanding the capacity of memory controlled by a microprocessor, the physical space in the memory space is divided into a fixed area, a plurality of switching areas, and a plurality of shared areas belonging to each of the switching areas. 1. A memory expansion method characterized in that the logical space can be allocated to the fixed area, the switching area, and a plurality of shared areas.