JPS60263470A - Manufacture of semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To ensure highly efficient implantation of ions into a small cell area by a method wherein a floating gate electrode is built in an ion-implanted layer of the second conductivity type, a selective gate electrode is formed in a second gate insulating film, and a drain region and source region of the second conductivity type are formed on the surface of semiconductor to sandwich the floating gate electrode and selective gate electrode. CONSTITUTION:An n type impurity is implanted by the ion implantation method into the surface of a p type substrate for the formation of an n type inversion region 2. A floating gate electrode 4 is built in the n type inversion region 2 through the intermediary of a first gate insulating film 3. With the floating gate electrode 4 acting as a portion of the master, a p type impurity is implanted by the ion implantation method into a portion of the n type inversion region 2, for the formation of a p type region 5. Next, a second gate insulating film 7 is formed on the p type region 5. An insulating film 6 is next formed on the top and sides of the floating gate electrode 4. A process follows wherein a selective gate electrode 8 is formed with an end thereof in contact with the insulating film 6 situated on the floating gate electrode 4. A drain region 9 and source region 10 are formed by implanting an n type impurity so that they may sandwich the floating gate electrode 4 and selective gate electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a floating gate type semiconductor nonvolatile memory having an MI8 structure. More specifically, the present invention relates to a method of manufacturing a semiconductor nonvolatile memory that enables writing of charges into a floating gate electrode at low voltage and with high injection efficiency.

First, the structure, operation, and manufacturing method of a low program voltage channel injection floating gate semiconductor nonvolatile memory (hereinafter referred to as PAOMO8 memory) will be described.

FIG. 1 shows a cross-sectional view of a PAOMOS memory. Below, P
A case where the AOMOS memory is an N-channel type will be explained.

Surface KN of P-type semiconductor substrate 1 Type 1 source region 1
0 and a first channel region L in which a drain region 9 is formed and located between the drain region 9 and the source region 10.
A gate insulating film 3 is formed from above 1 to above drain region 6.
A floating gate electrode 4 is formed through the gate electrode. Also the second
A selection gate 8 is formed from above the channel region L2 to above the floating gate electrode 4 via a gate insulating film 7 and an interlayer insulating film 6.

Next, the operation of writing charges into the floating gate electrode 4 will be explained. The potential applied to the selection gate electrode 8 causes the second
The surface potential of the channel region L2 can be controlled to a level approximately corresponding to the source region ioI/c.

The surface potential of the first channel region L1 is controlled by the potential of the drain region 9 and the amount of charge of the floating gate electrode 4. Therefore, by applying the program voltage 4 to the drain region 9), the A
A large potential gap corresponding to the programming voltage is formed near the point, and by accelerating the channel electrons flowing out from the source region 10 by the electric field, some of the channel electrons are injected into the floating gate electrode 4 and written. is executed. In this case, since the floating gate electrode 4 is given a potential by the capacitive coupling formed with the drain region 9 via the gate insulating film 3, the efficiency of charge injection into the floating gate electrode 4 is this coupling capacitance O1.
It is advantageous to have a larger value of the ratio 01 (a) 01+ 02 + 03 5- to the total capacity.

In this memory manufacturing method, in order to form the above-mentioned coupling capacitance CI, the drain region? A process of forming a floating gate electrode 4 with a gate insulating film 3 interposed therebetween is adopted. In this manufacturing method, when forming the floating gate electrode 4, the dimension of the first channel region π1 needs to be set to a length that takes mask misalignment into full consideration. Therefore, 02 becomes large and the value of the above equation (a) becomes small. In order to compensate for this, it is necessary to increase 01, which has the drawback of increasing the +i product between the floating gate electrode 4 and the drain region 9.

The present invention has been made to eliminate these drawbacks, and provides a method for manufacturing a semiconductor nonvolatile memory that makes it possible to obtain high injection efficiency with a small cell area. The first embodiment of the present invention will be described below in Figures 2(a) to 2(a).
This will be explained in detail using (f).

First, as shown in FIG. 2(a), KN type impurities are implanted into the surface of the P type substrate 1 by ion implantation to form an N type inversion region 26-. Next, as shown in FIG. 2(b), a floating gate electrode 4 is formed on the N-type inversion region 2 with the first gate insulating film 3 interposed therebetween. Using the floating gate electrode 4 as part of a mask, a part of the N-type inversion region 2 is ion-implanted with KP-type impurities to form a P-type region 5, as shown in FIG. 2(0). Next, as shown in FIG. 2(d), a second gate insulating film 7 is formed on the KP type region, and an insulating film 6 is formed on the top and side surfaces of the floating gate electrode 4. Next, as shown in FIG. 2 (θ), the selection gate electrode 8 is formed so that one end thereof covers the insulating film 6K on the floating gate electrode 4. Then, as shown in FIG. 2(f), a drain region 9 and a source region 10 are formed with N-type impurities so that the floating gate electrode 4 and the selection gate electrode 8 are interposed therebetween.

A cross-sectional view of the PAOMO8 memory manufactured in this manner is shown in FIG. Since the P-type region 5 is formed in a self-aligned manner with respect to the floating gate electrode 4, i □1°
゜1. Yu, a. Yo 5° Yoka.

will be controlled by the spread of Here, the lateral expansion of the P-type region 5 can be generally controlled by a thermal process. This is because it is possible to obtain a structure that is completely unaffected by mask displacement when forming the floating gate electrode 4, and the first channel region L1 can be made to have a sufficiently small length. The parasitic capacitance 02 between the floating gate electrode 4 and the first channel region 51 can be made sufficiently small. If 02 becomes smaller, 01 can be made smaller while keeping the value of equation (a) large. Therefore, even if the area of the floating gate electrode 4 is reduced, the floating gate Even if the area of the electrode 4 is reduced, a sufficiently high potential can be applied to the floating gate electrode 4vζ, and high injection efficiency can be obtained.

Next, a second embodiment of the present invention is shown in FIGS. 5(a) to 5(f) and will be described. As shown in FIG. 3(a), a KN type impurity is implanted into the surface of the P type substrate 1 by ion implantation to form an N type inversion region 2, and as shown in FIG. 3(b), an N type inversion region is formed. 2
A floating gate electrode 4 is placed on top of the first gate insulating film 3 via the first gate insulating film 3.
form. Next, as shown in FIG. 3(C), it is not covered with the floating gate electrode 4. A second gate insulating film 7 is formed on the N-type inversion region 2, and an insulating film 6 is formed on the top and side surfaces of the floating gate electrode 4.

Next, as shown in FIG. 3(d), using the insulating film 6 on the floating gate electrode as part of a mask, a P-type impurity is ion-implanted into a part of the N-type inversion region 2. form. Next, as shown in FIG. 3 (θ), one end is connected to the floating gate electrode 4.
A selection gate electrode 8 is formed so as to span the insulating film 6 on top of the insulating film 6, and as shown in FIG. Source regions 10 are formed using N-type impurities.

In addition, the third embodiment of the present invention is shown in FIGS. 4(a) to (f) K.
and explain this. As shown in FIG. 4(a), an N-type impurity is implanted into the surface of the P-type substrate 1 by ion implantation to form an N-type inversion region 2, and as shown in FIG. 4(b), an N-type inversion region 2 is formed. A floating gate electrode 4 is formed on the first gate insulating film 3 with a first gate insulating film 3 interposed therebetween. As shown in FIG. 4(C), a second gate insulating film 7 is formed on the N-type inversion region 2 that is not covered with the floating gate electrode 4, and an insulating film is formed on the top and side surfaces of the floating gate electrode 4. 9- Form the selection electrode 8 as shown in FIG. 4 ((1)) so that one end covers the insulating film 6K on the floating gate electrode 4. Next, as shown in FIG. 4(e), Using the selection gate electrode 8 on the insulating film 6 as part of a mask, using the selection gate electrode 8 as part of the mask, a part of the N-type inversion region 2 [
P-type impurities are implanted by ion implantation to form P-type regions 5. Then, as shown in FIG. 4(f), the drain region 1 is placed so that the floating gate electrode 4 and the selection gate electrode 8 are in between.
0 are formed by N-type impurities.

Although the position of the P-type region 5 is slightly different from the first embodiment as well as the second and third embodiments, for the -1 part, the P type region 5 is slightly different from the first embodiment.
Since the lateral expansion of the mold region 5 can be controlled by 9, the effect remains the same.

Also, 1st. Second. It is clear that in both the third embodiment and the third embodiment, the effects of the present invention will not be impaired in any way even if the drain region and the source region are formed in any order during these steps.

As described above, according to the present invention, a nonvolatile memory cell can be manufactured that can obtain high injection efficiency with a small memory cell area without requiring a large floating gate area, which is a disadvantage of nonvolatile memories. I can do that.

The embodiments of the present invention have been shown for an N-channel type nonvolatile memory provided on a P-type substrate, but P8! ! It goes without saying that the manufacturing method of the present invention can be applied to nonvolatile memories made on semiconductor layers. Further, a similar manufacturing method can be applied to a P-channel type nonvolatile memory fabricated on an N-type semiconductor layer on an N-substrate, N-well, or insulating film.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor nonvolatile memory cell, FIGS. 2(a) to (f) are ratio cross-sectional views showing the order of steps in the manufacturing method of the first embodiment of the present invention, and FIG. ) to (f) show the process order of the manufacturing method of the second embodiment of the present invention. 41 bodies ~ (1) □ 8 pieces. 6゜□a2. . FIG. 5 is a cross-sectional view showing the process order of the manufacturing method, and is a cross-sectional view of a semiconductor nonvolatile memory cell manufactured according to the present invention. 1... P-type semiconductor substrate 2... N-type inverted no. 3...
・First gate insulating film 4...Floating gate electrode 5...P-type head region 6...Insulating film 7...Second gate insulating film 8...Selection gate electrode 9...Drain Area 10...Source area and above Applicant: Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Mogami

Claims (3)

[Claims] (1) At least a first
a step of forming an ion implantation layer of a second conductivity type different from the conductivity type; a step of forming a floating gate electrode on the ion implantation layer of the second conductivity type via a first insulating film; Electrodes as part of the mask! forming an ion implantation layer of @1 conductivity type, forming an insulating film on top and side surfaces of the floating gate electrode, and forming a second gate insulating film on the ion implantation layer of the first conductivity type. The process of
forming a selection gate electrode on the second gate insulating film so that one end thereof covers the insulating film on the floating gate electrode; A method for manufacturing a semiconductor nonvolatile memory, comprising the step of forming a second conductivity type drain region and source region on a semiconductor surface. (2) At least a first conductive layer is formed on the surface of the semiconductor substrate of the first conductivity type.
a step of forming an ion implantation layer of a second conductivity type different from the conductivity type; a step of forming a floating gate electrode on the ion implantation layer of the second conductivity type via a first gate insulating film; forming an insulating film on the top and side surfaces of the electrode; forming a second gate insulating film on the second conductivity type ion implantation layer; and masking the insulating film on the top and side surfaces of the floating gate electrode. forming an ion-implanted layer of the first conductivity type under the second gate insulating film; a step of forming a selection gate electrode thereon; and a step of forming a drain region and a source region of a second conductivity type on the surface of the semiconductor substrate so as to sandwich the floating gate electrode and the selection gate. A method of manufacturing non-volatile memory. (3) At least a first conductive layer on the surface of the first conductivity type semiconductor substrate.
a step of forming an ion implantation layer of a second conductivity type different from the conductivity type; a step of forming a floating gate electrode on the ion implantation layer of the second conductivity type via a first gate insulating film; forming an insulating film on top and side surfaces of the gate electrode; and forming a second gate insulating film on the second conductivity type ion implantation layer so that one end thereof covers the insulating film on the floating gate electrode. forming a selection gate electrode, and using the insulating film on the floating gate electrode and the side surfaces as part of a mask, forming an ion implantation layer of a first conductivity type under the selection gate via the selection gate electrode; A method for manufacturing a semiconductor nonvolatile memory, comprising the steps of: forming a drain region and a source region of a second conductivity type on the surface of the semiconductor substrate so as to sandwich the floating gate and the selection gate therebetween.