JPS60261058A - Tracking control circuit - Google Patents

Abstract

PURPOSE:To realize sure tracking control even if the level of crosstalk of a pilot signal is fluctuated by providing a tracking error signal of an adjacent tracking to adjust the amplification factor of a transmission system to a servo system. CONSTITUTION:A digital signal is subjected to time axis compression, an azimuth track is formed on a recording medium 2 while not forming a guard band and plural rotary heads record and reproduce signals on the tracks. In this case, a subtraction means 23 taking a difference of tracking error signals on the adjacent racks, a switch 25 transmitting the subtraction output to a drive system and a comparison means 51 comparing a tracking error signal at least having a larger level in each tracking error signal with a reference signal are provided. Then the amplification factor of the transmission system reaching the switch 25 is adjusted by the comparison output.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention converts, for example, a video signal or an audio signal into a PCM signal, and records this as one diagonal track on a recording medium by a rotating head in units of time. The present invention relates to a tracking control circuit suitable for use in a digital signal recording and reproducing device for reproducing digital signals.

BACKGROUND TECHNOLOGY AND PROBLEMS A helical scan type rotary head device records video and audio signals on a magnetic tape once per unit time.
When recording by forming diagonal tracks one by one and reproducing them, it has been considered to record and reproduce video signals and audio signals by converting them into PCM. This is because PCM allows high-quality recording and reproduction.

In this case, tracking control to ensure that the rotating head correctly scans the recording track during playback is conventionally performed by sending a control signal recorded at one end of the tape by a fixed magnetic head to the fixed head. Normally, this is done by reproducing the signal and making sure that the reproduction control signal and the rotational phase of the rotary head have a constant phase relationship.

However, this method requires a fixed magnetic head specifically for tracking control.

Providing such a fixed magnetic head is inconvenient when it is desired to downsize the recording/reproducing apparatus due to the mounting location and the like.

Therefore, the present applicant previously proposed a method of controlling the tracking of a rotary head for reproduction by using only the reproduction output of the rotary head for reproduction without using this fixed head.

In this method, PCM signals can easily be compressed and expanded on the time axis, so unlike analog signals, it is not necessary to record and reproduce the signals continuously in time.
This method was developed by focusing on the fact that it is possible to easily record this PCM signal and a separate signal by dividing the area into the tracks of a book.

In other words, when a PCM signal is compressed in the time axis and recorded by diagonally forming tracks on a recording medium using a plurality of rotating heads without forming a guard band, the PCM signal is recorded in the longitudinal direction of each track. Multiple tracking pilot signals are recorded independently as areas, and during playback,
A recording track is scanned by a rotary head whose scanning width is wider than the width of the track, and the tracking of the rotary head is controlled by the reproduced output of pilot signals from tracks on both sides of the track being scanned by the rotary head.

The reference signal for recording and reproducing this pilot signal for dragging is a 30Hz pulse signal ( PG) is used.

However, even during playback, if the PG double signal is used as a detection position reference when reproducing the tracking pilot signal, the PG double signal reference position may shift due to mechanical changes over time or temperature changes in the device, causing the PG double signal reference position to shift during playback. It appears as a kind of steady amount (offset) of tracking error.

For this reason, it becomes difficult to reproduce the tracking pilot signal at the same timing as during reproduction and recording, and to control the rotary head, and there is a problem in particular that compatibility between devices becomes incompatible.

In addition, since the sampling pulse for obtaining the reproduction output of the tracking pyro-node signal is formed over one rotation period of the head using the PG multiplied signal as a reference, the error increases in an integrated form, resulting in so-called jitter. There is an inconvenience that the position of the sampling pulse shifts due to the influence of

Furthermore, when considering tracking control in a rotary head type recording/reproducing apparatus, it is necessary to consider not only normal reproduction but also variable speed reproduction in which the tape speed is different from that during recording.

Purpose of the Invention In view of the above, the present invention provides a method for reliably reproducing a tracking pilot signal without being affected by mechanical aging, temperature changes, or jitter of the device, not only during normal reproduction but also during variable speed reproduction. Provided is a tracking control circuit in a digital signal recording and reproducing device that can correctly control a rotating head by using a digital signal to ensure compatibility between devices, and can simplify the circuit configuration when switching between multiple playback speeds for playback. It is something to do.

Summary of the Invention The present invention compresses the time axis of a digital signal, forms and records diagonal tracks on a recording medium using a plurality of rotating heads without forming a guard band, and reproduces the digital signal. In a recording/reproducing apparatus, a subtraction means for taking the difference between tracking error signals of adjacent tracks and racks, a transmission system for transmitting the output of this subtraction means to a drive system, and at least the one having a higher level among the above-mentioned tracking error signals. and a comparison means for comparing the tracking error signal and the reference signal, and is configured to adjust the amplification factor of the transmission system based on the output of the comparison means.

As a result, the present invention can be used reliably for tracking without being affected by mechanical changes over time, temperature changes, or jitter of the device, and even if the output fluctuates due to the combination of the recording medium and the rotating head. Tracking control of the rotary head can be performed by reproducing the pilot signal, and compatibility between devices can be achieved. Further, the circuit configuration when performing reproduction by switching between a plurality of reproduction speeds can be simplified.

EXAMPLE Hereinafter, an example of the present invention will be described in detail based on FIGS. 1 to 11.

FIG. 1 shows the circuit configuration of this embodiment, and here,
Only a circuit configuration for recording a tracking pilot signal and an erasing signal, which are directly related to the present invention, and reproducing them by switching between normal playback and variable speed playback, for example, double speed and triple speed, is shown. The circuit configuration for recording and reproducing signals is omitted.

In the figure, (IA) and (IB) are rotating heads, (
2) is a magnetic tape as a recording medium. The rotating heads (1^) and (IB) are arranged around the periphery of the drum (3) at equal angular intervals, i.e. 180 degrees apart, as shown in FIG. On the other hand, the magnetic tape (2) is wound around the tape guide drum (3) over an angular range, for example 90 degrees, which is smaller than its 180 degree angular range. Then, the rotating heads (IA) and (IB) are rotated at a rate of 30 revolutions per second in the direction of arrow (4H), and the tape (2) is run at a predetermined speed in the direction of arrow (4T). Then, (5B) shown in FIG. 3 is formed on the magnetic tape (2) by the rotary heads (IA) and (IB) in a so-called overwritten state, for example. That is, the head gap width (scanning width) W is made larger than the track width. In this case, the width directions of the gaps of the heads (IA) and (IB) are set in different directions with respect to the direction orthogonal to the scanning direction. In other words, the so-called azimuth angles are made different.

Then, a period (in this example, a period corresponding to an angular range of 90 degrees) occurs during which the two rotating heads (IA) and (IB) do not come into contact with the tape (2), and this period is utilized. The apparatus can be simplified by adding redundant data during recording and performing correction processing during reproduction.

(6) is an oscillator that generates a tracking pilot signal P, and the pilot signal P has, for example, a frequency fo that is a value with relatively large azimuth loss, that is, a frequency where azimuth loss is effective, for example, about 200 kHz, and recorded at a high level.

Note that the frequency of this pilot signal P is preferably a frequency with relatively little azimuth loss, as long as the linearity of the tracking phase shift versus the viroft reproduction output can be guaranteed. Further, (6A) is an oscillator that generates a signal E for erasing the pilot signal, and the erasing signal E is later superimposed on the previously recorded tape while erasing the previously recorded information. This is used because when making a new recording, it is necessary to erase the previously recorded pilot signal because the recording track does not always match the previous recording track, and the frequency f1 is the same as the pilot signal. For example, 700, which is practically distant from the frequency ro of
The frequency is around kHz and has relatively large azimuth loss. Further, the recording level is also set at a level that can practically erase the pilot signal P. and,
This erasing signal E is used here as a positioning signal for detecting the position of the pilot signal.

Further, (6B) is an oscillator that generates an erasing signal Eo different from the above-mentioned erasing signal E, and this erasing signal Eo
When the pilot signal P and the erasing signal E are overwritten, it is preferable that the erasing rate of these signals P and E is high, and the frequency f2 is, for example, 2 MHz.
A certain degree is used.

(7), (7A), and (7B) are recording waveform generation circuits, and an edge detection circuit (8A) detects an edge, for example, a falling edge, of a delayed signal related to pulse PG, which will be described later.
, (8B), the generation circuits (7) and (7A) generate how many pilot signals P and erasure signals per track based on the pilot signals from the oscillators (6) and (6B). A predetermined time tp depending on the arrangement in which Eo is inserted (tp is the recording time of each pilot signal and erasing signal Eo, however, the recording time per recording area of erasing signal Eo is track (5A) Then, the generation circuit (7B) continuously generates the pilot signal P and the erasure signal Eo having the time jp+ (the time at two separate points in the trunk (5B) is set as the time tp), and the generation circuit (7B) generates the signal from the oscillator (6A). Based on the erasing signal E, an erasing signal E having a predetermined time -tp is generated at a predetermined interval T1 depending on how many erasing signals E are inserted per track and in what arrangement. (8F) is the generation circuit (71, (7
This is an OR circuit that logically processes the outputs of ^) and (7B). (9) is a switch circuit for switching the rotary heads (IA) and (IB), and is switched by a switching signal S1 (FIG. 4A) from a timing signal generating circuit Ql. This timing signal generation circuit Ql has rotating heads (IA) (IB) from a pulse generator (11).
30Hz indicating the rotational phase of the rotary head (IA) (IB) obtained in synchronization with the rotation of the rotational drive motor (12).
pulse PG is supplied. Further, the pulse PG and a 30 Hz pulse from the timing signal generation circuit 01 are supplied to a phase servo circuit (13), and the rotational phase of the motor (12) is controlled by the servo output.

The biloft signal from the switch circuit (9) switched by the switching signal S1 from the timing signal generation circuit Ql is amplified by the amplifier (14A) or (14B) and then sent to the contact point of the switch circuit (15A) or (15B), respectively. It is supplied to the rotary head (IA) or <IB) via the R side and recorded on the magnetic tape (2). Switch circuit (15A
) and (15B) are connected to the R side during recording, and are switched to the P side during playback.

In addition, the output signal S2 from the timing signal generation circuit α
(Fig. 4C) is supplied to the delay circuit (16), which connects the rotary head (IA) (IB) and the pulse generator (11).
After a delay corresponding to the interval between the mounting positions, etc., the signal is supplied to the input side of an edge detection circuit (8A), and an edge, for example, a falling edge, is detected as a recording reference for the pilot signal. Note that the signal 3m (
The falling edge in FIG. 4D) is made to coincide with the time when the head first contacts the tape during one rotation period.

Also, (17A), (17B), (17C), (
170) and (17E) are delay times Tt(1) (times corresponding to the respective intervals of the pilot signal P, erasure signals E and Eo recorded on the rack), T2 (2T1
)T (time corresponding to a half-rotation period of the head), tp, and -tp. The signal S3 (Fig. 4D) from the delay circuit (16) is sent to the delay circuits (17A) to
(17G). The signal S4 (Fig. 4E) from the delay circuit (17A) is supplied to the edge detection circuit (8A), and the signal Ss (Fig. 4F) from the delay circuit (17B) is supplied to the edge detection circuit (8A).
) is supplied to the edge detection circuit (8B), and the delay circuit (1
The signal S6 (FIG. 4G) from 7C) is directly supplied to the edge detection circuit (8B), and is also supplied to the respective delay circuits (17^
) and (17B), the signals are delayed by times T1 and T2 and are supplied to the edge detection circuits (8B) and (8A) as a signal Sv (H in FIG. 4) and a signal Ss (I in FIG. 4).

Signal S9( from edge detection circuits (8A) and (8B)
The signals 511 (L) and 512 (M) are delayed by time tp and -tp in the delay circuits (170) and (17E), respectively.
). The signal S11 is supplied to the negative input terminal of the OR circuit (8C) and is delayed by a time -tp in the delay circuit (17E) to become the signal 513 (N in FIG. 4). This signal S13
is supplied to the - input terminal of the OR circuit (8D) and delayed by time -tp in the delay circuit (17B) to produce the signal 514 (
0) in Fig. 4, and this signal S14 is an OR circuit (8E).
The signal 515 (FIG. 4P) is supplied to the - input terminal of the OR circuit (8D) and is delayed by a time -tp in the delay circuit (17E), which is then supplied to the other input terminal of the OR circuit (8D).

Further, the signal St2 is supplied to the other input terminal of the OR circuit (8E) and is delayed by a time tp in the delay circuit (170) to become a signal 816 (Q in FIG. 4), and this signal Szg is supplied to the other input terminal of the OR circuit (8D). The signal is supplied to another input terminal and further delayed by a time tp in a delay circuit (170) to become a signal 517 (R in FIG. 4), which is supplied to the other input terminal of an OR circuit (8c).

The signals 5ze (S in FIG. 4), the signals 519 (T in FIG. 4) and the signals 320 (in the fourth diagram) from the OR circuits (8C), (8D) and (8B) are the recording waveform generating circuit (7), respectively.

(7A) and (7B), and the pilot signal P and erase signals Ea and E from the generators (6), (6B) and (6A), respectively, are supplied to the recording waveform generation circuits (71, OR circuit (
8F) as a composite signal 521 (FIG. 4V).

(18A) (18B) is the switch circuit (
These amplifiers (18^) (
Each output of 18B) is supplied to a switch circuit (19). The switch circuit (19) includes a timing signal generation circuit (
30Hz switching signal 81' (58th!IA,
6A and 7A), the head (
The half-rotation period including the tape contact period of IA) and the head (
IB) is alternately switched with a half-rotation period including the tape contact period.

(20) is the passing center frequency r for extracting only the pilot signal P from the reproduction output from the switch circuit (19).
o narrowband bandpass filter, (21) is a peak hold circuit for holding the peak value of the output of the filter (20) in order to improve response characteristics, (22)
, (60) is a sampling and holding circuit for sampling and holding the held peak value;
(23) is the sampling hold circuit (22), (6
The sampling hold circuits (22) and (60) are subtracters that subtract each output of the track currently being scanned during normal playback, as will be described later. Records at both ends and the center of a track, or during double-speed playback, the center or end of the track currently being scanned, and during triple-speed playback, records at the center or both ends of the trunk on both sides adjacent to the track currently being scanned. It works to sample and hold the crosstalk of each pilot signal.

(61) is a sampling pulse generation circuit (22).

(60) is an adder that adds the respective outputs, (62) is a reference signal generation circuit that generates a reference signal, (63) is a divider that divides the reference signal by the addition output of adder (61), ( 64)
is a multiplier that multiplies the division output of the divider (63) and the subtraction output of the subtractor (23). As described later, the reference value is divided by the sum of the outputs of the sampling and holding circuits (22) and (60), and the sampling and holding circuit (22)
, by multiplying by the subtracted value of each output of (60),
An output at a constant level is always obtained on the output side of the multiplier (64). In other words, it is possible to perform a so-called AGC operation in which the loop gain is automatically adjusted to a constant value.

(24) is a sampling and holding circuit for sampling and holding the multiplication output from the multiplier (64), and the timing of the sampling pulse given to this sampling and holding circuit (24) is given to the sampling and holding circuit (60). Any time after the sampling pulse may be used.

The output of the sampling hold circuit (24) is taken out as a tracking control signal to an output terminal (26) via a switch circuit (25).

Also, sampling hold circuits (22), (60)
.

In order to form sampling pulses etc. for (24),
A narrow band pass filter (29) with a passing center frequency f1 is provided on the output side of the switch circuit (19) for extracting only the erasing output E from the reproduced output, and its output 539 (Fig. 5, 6 The signal 522 (FIG. 5, FIG. 6 J, FIG. 7 L) is waveform-shaped by the waveform shaping circuit (30).

(31) is a rising edge detection circuit for detecting the rising edge of the signal from the waveform shaping circuit (30), and as described later, the rising edge of the erasing signal is detected every half rotation period of the head. Ru. The output of the detection circuit (31) is sent to a plurality of gate circuits (33z) and '(332).

(333) , (334) , (336) and (33s
), and the window signals SW1 to SW5V6 (FIG. 5 CH) from a window signal generation circuit (34) using a counter are used as the gate signals, for example.

The window signal generation circuit (34) responds to the output signal S2 from the timing signal generation circuit OI to the clock terminal (34).
42), and generates a window signal of a predetermined width that can cover at least both ends of the signal 322 described above in accordance with a plurality of playback modes.

That is, when the window signal generation circuit (34) receives a command signal to set the normal playback mode from the mode setting circuit (32), it sequentially generates the window signals SWz to S%16, and also receives a command to set the double speed playback mode. When the signal is received, the window signal SW2. When only SW5 or SWi+SW4 is generated and a command signal for setting the triple speed playback mode is received, the wind signal SW2+SWS or SWt, SW
3, S y4 , S we ).

Therefore, only the edges of the signal S22 that have entered within the period of these window signals SW1 to SV8 are derived to the output sides of the gate circuits (331) to (33e), and the output side of the OR circuit (35) output signal 523 (Fig. 5 M, 6
A delay circuit (36) using, for example, a counter as the start pulse
is supplied to one input side of the

Also, a plurality of delay time setting circuits (38) and (39)
is provided, and the setting circuit (38) sets a delay time ta from the time of generation of the signal 323 during double speed and triple speed playback until the actual sampling of the pilot signal starts;
The setting circuit (39) sets the delay time tb from the time of generation of the signal 323 to the actual sampling time of the pilot signal during double speed reproduction.

Each delay time set in the setting circuits (38) and (39) in this way is selected by the window signals SVi to SW6 from the window signal generation circuit (34) in the delay time setting selector (37). It is supplied to the other input side of the delay circuit (36). Therefore, the delay circuit (36), which is a counter, uses the signal 323 as a start pulse and counts the clock directly from the clock terminal (42) if no delay is required, or for the set time if a delay is required. At the end of the count, a narrow signal 324 (N in FIG. 5, N in FIG. 6, and N in FIG. 7) is generated on its output side.

(43) is a pulse generation circuit using a counter, for example, which counts the clock from the clock terminal (42) using the signal 324 from the delay circuit (36) as a trigger pulse, and counts the clock from the clock terminal (42) during normal playback and triple speed playback ( In the first method), a pair of pulses Pi (Fig. 5 O1 7th
(Fig. O), and one of the pair of pulses Pi (Fig. 6 M, P, Fig. 7 R) during double-speed playback and triple-speed playback (the second method). is generated corresponding to each pilot signal. This pulse Pi is supplied to a peak hold circuit (21) and also to a sampling pulse generation circuit (44) using, for example, a D-type flip-flop circuit.

The sampling pulse generating circuit (44) generates sampling pulses SP1°SF3 to the sampling hold circuits (22) and (24) in response to the pulse Pi.

Further, (51) is a comparison circuit provided on the output side of the filter (29), and this comparison circuit (51) is connected to the output of the filter (21), that is, the reproduction output of the erasing signal E and the reference power source (52). ), and if the reproduced output exceeds the reference value, an output signal 525 (C in Figure 8) is generated and is sent to the clock terminal of the D-type flip-flop FIIF (53) once as a latch pulse. supply Further, a circuit (54) for detecting, for example, the falling edge of the switching signal S1' from the timing signal generation circuit αQ is provided, and the output signal 526 (
E) in FIG. 8 is generated and supplied to the reset terminal R of the flip-flop circuit (53) as a reset signal. Also,
The switching signal 81' is inverted by the inverter (55) and becomes the signal 81' (FIG. 8F), which is output to the flip-flop circuit (55).
3) is supplied to the input terminal.

Furthermore, a circuit (56) for detecting, for example, the rising edge of the switching signal Ss' is provided, and generates an output signal 527 (FIG. 8G) in synchronization with the rising edge of the switching signal 31', and outputs a D-type flip-flop as a clock signal. It is supplied to the clock terminal of the circuit (57). The output signal 8 of the flip-flop circuit (53) is connected to the input terminal of the flip-flop circuit (57).
28 (Fig. 8H) is supplied, and the flip-flop circuit (
57) output signal 529 (Fig. 8 1) is output from the switch circuit (
25) is used as a switching control signal. That is,
As will be described later, the switch circuit (25) receives a control signal S
When 29 is at one level, for example, high level (H), contact a
is connected to the output terminal (2) to output the tracking control signal.
6) and performs normal operation, but the control signal 5e1
When 1 is at the other level, for example, low level (L), it is connected to the contact side, takes out a constant potential Vcc from the terminal (58) to the output terminal (26), and uses this as a tracking control signal for the capstan servo system. to force the scanning head to return to a normal tracking state.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the signal waveforms shown in FIGS. 4 to 10.

First, during recording, in response to the pulse PG from the pulse generator (11) that indicates the rotational phase of the rotary head (LA) (IB), the timing signal generation circuit α outputs the pulse signal shown in FIG. 4C.
A signal S2 as shown in Figure 4 is generated, and this signal S2 is delayed by a predetermined time TR in a delay circuit (16), so that a signal S3 as shown in Figure 4 is outputted to its output side. This signal S3 is supplied to the direct and delay circuit (17A) as described above.
), (17B) to the edge detection circuit (8A), where the edge (falling edge) is detected, and in synchronization with this edge, a narrow edge as shown in FIG. 4J is provided on the output side. A width signal S9 is generated. In addition, a delay circuit (17B
) (17G) and (17A) are supplied to the edge detection circuit (8B), which detects the edge (falling edge) and outputs the signal to the output side in synchronization with this edge. A signal SSO as shown in FIG. 4K is generated. The signals S-s + Sso are each passed through a delay circuit (1
7D) and (17B) and are delayed as described above (see Figure 4 L-R), resulting in an OR circuit (8
C) to (8E), signals Sxs to S20 as shown in FIG. ), (IB), the recording start standards for the pilot signal P, the erasing signal Eo, and the erasing signal E are established, respectively.

The signals S 1s + S 19 and S2o are supplied to recording waveform generation circuits (7), (7A) and (7B), respectively, and the recording waveform generation circuit (7) generates an oscillator (6) in synchronization with the supplied signal S1e. ) is passed for a predetermined time tp at predetermined intervals as shown in FIG. The erasing signal Eo from (6B) is passed for a substantially predetermined time tp at predetermined intervals as shown in FIG. In synchronization, the erasing signal E from the oscillator (6^) is passed for a predetermined time -tp at predetermined intervals as shown in FIG. 4U.

The output signals from the recording waveform generating circuit <v+, (7A) and (7B) are added by an OR circuit (8F), and a signal 321 as shown in FIG. 4 is taken out at the output side.

Incidentally, at this time, if we consider, for example, that the head (IB) is recording the track (5B2) in FIG. 3, the first, second, and third pulses of the signal Szs in FIG. A21 P A4 and P
Corresponding to AII, the first signal 31s in FIG.
, the second and third pulses are the erasing signal E A21E^4
corresponds to the erasing signal Eo adjacent to both sides of the erasing signal EA@l and an example of the erasing signal EA@l, and also corresponds to the signal 5 in FIG.
The 20 first, second, and third pulses correspond to the erasing signals EA2+, EA4, and EAII adjacent to the Eo, respectively, and the signals corresponding to the arrangement of these signals, that is, PA2.
EO* EA2. EO and P A41 E o +E
The composite signals of A41 Eo and EAII Ea + P All are taken out to the output side of the OR circuit (8F) for each group.

Furthermore, for example, considering the case where the head (IA) records the trunk (5A2) in FIG. 3, the first, second, and third pulses of the signal S1s in FIG. 4 S are the pilot signals P B2+ P Corresponding to R4 and psa, the first, second and third pulses of the signal S1S in FIG. Correspondingly, the first and second signals of the signal S20 in FIG.
and the third pulse are respectively E above.

Corresponds to the erasing signals EB21, EB4, and pae adjacent to the signal E
B21 E o + P R2 and EB41 EO + P
R4 and PH1,E.

The composite signal of EBe+R6 is taken out to the output side of the OR circuit (8F) for each group.

On the other hand, the timing signal generating circuit α generates a switching signal s1 as shown in FIG. 4A in response to the pulse PG from the pulse generator (11). ) is synchronized with the rotation of (IB),
As shown in FIGS. 4A and 4B, during the half-rotation period tA of the head when the signal S1 is at a high level, the head (IA)
The head (IB) contacts the tape (2) during the half-rotation period tB during which the signal S1 is at a low level.
). Then, the switch circuit (9) is switched by the switching signal S1 to the state shown in the figure during the period tA, and to the state opposite to the state shown in the figure during the period tB, thereby performing head switching.

Therefore, the signal Sz obtained on the output side of the OR circuit (8F)
t is the amplifier (14B) and the switch circuit (14B) when the switch circuit (91!J<
5B) to the head (IB), and at the beginning, middle and end of the contact period of the head (IB) with the tape (2) within the period tB, as shown in FIG. Recording areas ATt and A for tracking signals provided at both ends of the track (5B) in the longitudinal direction, which are equidistant A (corresponding to Ti) from the center position in the longitudinal direction of the track (5B)
T2 is recorded for time tp+, and further tracks (5
A similar recording area ATs installed in the center of B) at time tp+ -1p'
lZ On the other hand, when the switch circuit (9) is in the state shown in the figure, the signal S17 is connected to the amplifier (14^) and the Sui-Sochi circuit (15).
It is supplied to the head (1^) through the R side of ^), and for a period t
At the beginning, middle, and end of the contact period of the head (LA) in A with the tape (2), as shown in the figure, the track (5
Equidistant 41 from the center position in the longitudinal direction of A) (equivalent to To)
Recording is performed in the same way as in the recording area provided in the center of the track (5A) in the same recording area as described above provided in both ends of the trunk (5^) in the longitudinal direction.

In addition, at times other than the time when these pilot signals and erasure signals are recorded, the audio PCM signal of one segment portion to be recorded as one track, although not shown, is
During period t^, the head (IA) is connected through the amplifier (14A).
In the period QtB, it is supplied to the head (IB) through the amplifier (14B), and each track (5A) is supplied to the head (IB) through the amplifier (14B).
(5B) It is recorded in recording areas APL and AP2 other than the above-mentioned pilot signal recording area.

Next, reproduction of the signal recorded as described above will be explained.

Even during this reproduction, drum phase nervo is applied to the motor (12) by the phase servo circuit (13) in the same way as during recording.

First, during normal playback, the rotating head (IA)
The signals taken out from the tape (2) by the switch circuit (15A) and the amplifier (
18A), the contact P side of the switch circuit (15B), and the amplifier (18B) to the switch circuit (19). This switch circuit (19) uses a 30 Hz switching signal 81' as shown in FIG. , and a half-rotation period tB including the tape contact period of the head (IB). Therefore, from this switch circuit (19), an intermittent PCM signal sR of one segment as shown in FIG. The data is further supplied to a decoder, where data for each block is detected using a block synchronization signal, and subjected to processing such as error correction and de-interleaving, and then converted back to an analog audio signal by a D/A converter and output to the output side. .

Tracking control is performed as follows.

Now, for example, a scan @W where the head (IB) includes a track (5B2) as shown by a constant chain line in FIG.
, the head (IB) scans the tracks (5^2 (5^1)) on both sides of this track (582).
As shown in FIG.
and the pilot signal PBt of the track (5k), and on the right side of area A7@, the pilot signal P^4 of the track (5B2), the pilot signal PB4 of the adjacent track (5A2), and the pilot signal PB4 of the track (5A1) are reproduced. In the area AT2, the pilot signal pB@ of the trunk (5A2) on both sides, the pilot signal PB5 of the truck (5A1), and the pilot signal PA@ of the truck (5B2) are reproduced. At this time, the playback output of the head (IB) from the switch circuit (19) is supplied to a narrowband bandpass filter (20) with a passing center frequency fO, and as shown in FIG. 5J, the output SF is a pilot signal. Only the signal is extracted and supplied to the peak hold circuit (21).

Further, the output SR of the switch circuit (19) is supplied to a band pass filter (29), from which an erasing signal Sss as shown in FIG. 5K having a frequency f1 is extracted. This signal is supplied to the waveform shaping circuit (30) and made into a signal S22 as shown in Figure 5, and then the rising edge detection circuit (
3), where its rising edge is detected and supplied to gate circuits (33z) to (33g).

Further, in response to the signal S2 as shown in FIG. 5B from the timing signal generation circuit (11), the window signal generation circuit (34) generates a window signal SVx~3wa as shown in FIG. 5C-H. are generated sequentially and the gate circuit <331
) to (33g) as gate signals,
Therefore, on the output side of these gate circuits, only the signals that have entered during each period of the window signals SW, ~SW- are substantially taken out, and as a result, the gate circuits (331) to (33g
) on the output side of the OR circuit (35), as shown in FIG.
, (EA21 EA41 EA@ during the period tB, E B2 +E B4 + E Bg during the period tA), a narrow signal S23 is obtained.

This signal 323 is supplied to a delay circuit (36).

However, during this normal reproduction, the signal 323 coincides with the vicinity of the center of the pilot signal to be sampled, so there is no need to delay it, and therefore the selector (
37) does not set the delay time for the delay circuit (36), and the delay circuit (36) sequentially generates the signal S24 that matches the signal S23, as shown in FIG. 5N.

This signal S24 is supplied to the pulse generation circuit (43),
Based on the signal S24, as shown in FIG.
A pair of pulses pt corresponding to each pilot signal to be detected is formed, and a sampling pulse generation circuit (4
4) and a peak hold circuit (21). Based on the pulse Pi, the sampling pulse generation circuit (44) generates sampling pulses SP1 and SF3 as shown in P and Q in FIG. SP3
are generated, and the respective sampling and holding circuits (22)
.

(60) and (24).

The pulse pt thus obtained is supplied to the peak hold circuit (21), and the sampling pulses SpHSP2 and SF are formed based on this pulse Pi.
3 are sampling and hold circuits (22) and (60), respectively.
) and (24).

Therefore, while scanning the track (5B2) with the head (IB), as is clear from FIG.
The pulse train is in a state where the peak hold circuit (21) holds the crosstalk of the pilot signals PB21PR+ and PH1 of the adjacent track (5A2) on the opposite side to the transport direction shown by the arrow (4T) (Fig. 3). , the output of the peak hold circuit (21) at this time is supplied to the sampling hold circuit (22), where it is sampled by the sampling pulse sPi generated at the falling edge of the first pulse Pit, and is converted into an advanced phase tracking signal. The signal is supplied to one input terminal of the subtracter (23) as a signal.

Further, the second pulse P12 of the pulse pt is the pilot signal PB of the adjacent track (5Az) on the tape transport direction side.
1. The crosstalk between PB8 and PH1 is peak-bolded in the peak hold circuit (21).
The output of the peak bold circuit (21) at this time is supplied to the sampling hold circuit (6o), where it is sampled by the sampling pulse SP2 generated at the falling edge of the second pulse PL2, and is used as a tracking signal with a delayed phase. is supplied to the other input of the subtractor (23), and therefore the subtractor (23) receives the pilot signal PB.
2 and PBi, PH1 and pea, P Be h P as
Tracking signals corresponding to each crosstalk are sequentially subtracted. The subtracted output signal from the subtracter (23) is then supplied to one input end of the multiplier (64).

Also, sampling hold circuits (22), (60)
The respective outputs of are supplied to an adder (61) and added, and the added output is supplied to a divider (63), and the reference signal from the reference signal generation circuit (62) is divided by the added output and multiplied. is supplied to the other input end of the device (64). As a result, an output at a constant level is always obtained on the output side of the multiplier (64) even if there is a level fluctuation in the crosstalk of the pilot signal due to variations in the tape or rotating head.

This will be explained in detail with reference to FIGS. 9 and 10. Figure 9 shows an example of the relationship between the tracking phase and the crosstalk output of the pilot signal.
fPl is the crosstalk obtained on the sampling and holding circuit (22) side, and fP2 is the crosstalk obtained on the sampling and holding circuit (22) side.
60) side respectively.

When the tracking phase is 0 degrees, the rotary head is accurately scanning the trunk without shifting, and as it shifts toward the + side around 0 degrees, the crosstalk fP2 gradually increases until the phase approaches 90 degrees. , the crosstalk fP1 gradually decreases until the phase reaches 45
It becomes zero in degrees. Furthermore, if the shift is centered around 0 degrees, the crosstalk fPi will gradually increase and will decrease again when the phase approaches -90 degrees, while the crosstalk fP2 will gradually decrease and the phase will be 45 degrees. It becomes zero in degrees.

However, if there are variations in the tape, rotating head, etc., the amount of wall talk obtained at the output side of the sampling and hold circuits (22) and (6o) will change, and for example, it may become noisy. The sampling hold circuit at that time (2
Letting the crosstalks obtained on the output side of 2) and (6o) be rp□' and fP2', respectively, they change as shown by the dashed lines in FIG. 9 with respect to the tracking phase. In other words, the level of the crosstalk changes is exactly lower than that of the crosstalks fP1 and fP2.

And these crosstalk fPl, fP2 and fP1
Looking at the difference between ' and fP2', that is, how the subtractor (23) appears, the changes are as shown by the solid line a and the chain line in FIG. 10, respectively. Therefore, if the output with these characteristics is
When it returns to the number-bo system on the output terminal (26) side, the difference in characteristics shown by the solid line a and the chain line is the servo characteristic (servo gain).
The difference is Therefore, if there are significant variations in the tape, rotary head, etc., there is a risk that the servo system may oscillate or be unable to suppress disturbances, resulting in problems such as failure to satisfy the target servo characteristics.

Therefore, in this invention, subtraction! The output of (23) is not directly fed back to the servo system, but multiplied by the value that becomes the output and fed back. That is, the crosstalk fP1 and fpz (or fPi' and fp2') obtained at the output side of the sampling and hold circuits (22) and (6o) are added by an adder (61) and supplied to the divider (63). , which divides the reference signal from the reference signal generation circuit (62) by the supplied addition output and supplies it to the multiplier (64), which then outputs the result to the subtracter (
23) is multiplied by the subtracted output from .

Now, expressing this in terms of fP1 + fP2, the following formula % Formula % (11) In the above formula (11), Ref is the reference signal generation circuit (6
2) is the level of the reference signal from (fP1+fP2). In the above equation (1), when the tracking phase is 145 degrees or less, as can be seen from Fig. 9,
Since fp2=0, the above equation (1) becomes Ref
Since 1=0, the above equation (1) becomes. Furthermore, when the tracking phase is between 145 degrees and 45 degrees, (f p1 + fp2) is approximately Ref.
Therefore, the above equation (1) is equal to X (fpx fpz)
= (fpx fpz) ... (4) Ref. That is, when the tracking phase is below 145 degrees and above 45 degrees, the output of the multiplier (64) is ReL-
Ref, and between -45 degrees and 45 degrees (fp
z−fpz). This is represented by the broken line C in FIG. 10.

This also means that rp1' where the crosstalk has decreased to A
The same can be said for lrp2'.

Therefore, it is possible to realize a so-called AGC circuit in which the servo gain remains constant even if the outputs of the cross and -ri change.

The constant output thus obtained at the output side of the multiplier (64) is supplied to the sampling and holding circuit (24),
The sample is then held by the sampling pulse SP3 generated from the sampling pulse generation circuit (44) after the sampling pulse SP2. Therefore, the multiplication output of the multiplier (64) is obtained from the sampling and hold circuit (24) as a tracking control signal, and this signal is sent to the capstan (not shown) from the output terminal (26) via the contact a side of the switch circuit (25). The tape is supplied to the motor and the amount of tape transported is controlled.
) scans the track (5B2), it is controlled so that it spans the two tracks (5A2) and (5Az) on both sides by the same amount. That is, head CI
The center position of the gap in B) in the width direction is the track (5B2
) is controlled to scan in line with the center position.

The same process is performed for other tracks. For example, when the head (IA) scans the track (5A2), as shown on the right side of FIG. (5B2) pilot signal P A
7+ P A9. P^□□ and PA21 PA41PA
Since the crosstalk of e is obtained, these are sequentially peak held in the peak hold circuit (21) as described above, and the sampling pulse SP is supplied from the sampling pulse generation circuit (44) to the sampling hold circuit (22).
1, the pilot signal P At IP A9+ P
A tracking signal is obtained by sampling the crosstalk of At1, and a tracking signal is obtained by sampling the crosstalk of the pilot signal P^21 PA41 PAll using a sampling pulse SP2 supplied to the sampling and hold circuit (60). Then, the subtracter (23) and adder (61) subtract and add the tracking signals corresponding to the crosstalk of the pilot signals PAT and PA2, PAe and PA4, and PAll and PAe, respectively, and the subtracted output is directly sent to the multiplier ( 64), and the addition output is supplied to the multiplier (63) after dividing the reference signal by the divider (63).
64).

The multiplication output from the multiplier (64) is then supplied to the sampling and hold circuit (24) as a sampling pulse S.
By sampling at P3, a tracking control signal for the head (IA) can be obtained.

Similarly, move the track (5B3) to the head (IB).
When scanning, as shown in FIG. 3, the pilot signals PB? of the tracks (5A3) and (5A2) on both sides of it are scanned. l PBe1 PBII and P B21 P
Since the crosstalk of B4PBll is obtained, the crosstalk of the pilot signal PB7+PB111PB1□ is sampled with the sampling pulse SP, and the crosstalk of the pilot signal PB21 PH10PB@l is sampled with the sampling pulse SP2, and then subtracted. The pilot signal PB? and PH1, PBe and PH1, pntl and P
The head (IB
) can be obtained.

Next, during double speed playback, scanning is performed so that the center of the gap width of the rotary head passes through the position shown by the broken line TD in FIG. In other words, two images with different azimuth angles during recording
Scanning is performed during the first half of the tape contact period formed by the two rotary heads, and the other track (5A), for example, is scanned during the second half.

With this scanning method, the rotating head (1^) and (I
The signals extracted from the tape (2) by B) are sent to the contact P side of the switch circuit (15A) and the amplifier (18A), respectively.
) and the contact P side of the switch circuit (15B) and the amplifier (1
8B) to the switch circuit (19). This switch circuit (19) is the 68th switch circuit from the timing signal generation circuit section! ! 30Hz switching signal 8 as shown in IA
1', the rotation is alternately switched between a half-rotation period tA including the tape contact period of the head (IA) and a half-rotation period tB including the tape contact period of the head (IB), as in the case of recording. Therefore, from this switch circuit (19), the sixth
Intermittent PCM signals of one segment as shown in Figure G
R is obtained, which is supplied to a reproduced block code (not shown), demodulated to the original PCM signal, and further supplied to a decoder, where data for each block is detected by a block synchronization signal, and error correction and decoding are performed. Processing such as interleaving is performed, and the signal is converted back to an analog audio signal by a D/A converter and outputted to the output side.

Tracking control is performed as follows.

For example, if the head (IB) is to scan in the direction shown by the broken line TD across two tracks (5^2) (5B3) in FIG.
As shown in the figure, in the area ATL, the track (5B3
), the pilot signal PA2 of the track (582), and the pilot signal PR2 of the track (5A2) are reproduced, and in the area AT3, the pilot signal PAθ of the track (5To) and the pilot signal PAθ of the track (5To) are reproduced.
B2) pilot signal PA4 and truck (5A2)
The pilot signal PB4 of the track (5^3) is regenerated in the area AT2.
The biloft signal PBII of the track (5^2) and the pilot signal PA of the track (583) are reproduced. At this time, the head (IB) from the switch circuit (19)
) is supplied to a narrowband bandpass filter (20) with a passing center frequency fo, and as shown in the left part of Fig. 6H, only the pilot signal is extracted as the output SF, and this is the peak hold signal. It is supplied to the circuit (21).

Also, for example, two tracks (5A3) and (584) can be added to the 3rd B! When the head (IA) scans in the direction shown by the broken line TD at 0, the area ATL shown in the figure
In the case of the truck (584) pilot P^8,
Pilot signal P^7 of truck (5B3) and pilot signal PB of truck (5A3)? In area A-8, the biloft signal PAio of the track (5B4) and the pilot signal p of the track (583) are reproduced.
ne and in the area A, the track (5^
4) Pilot signal PB□2. The pilot signal PR11 of the track (543) and the pilot signal PA12 of the track (584) are reproduced. At this time, the reproduction output of the head (1^) from the switch circuit (14) is supplied to the bandpass filter (20), and as shown in the right part of Fig. 6H, only the pilot signal is output as SF. At the same time, the peak hold circuit (
21).

In addition, the output sR of the switch circuit (19) is supplied to the bandpass filter (29) in the same manner as described above, so that the erasing signal Ss (typically EA?+ during the period tB) as shown in FIG. EAll+EALi *During the period tA, typically EB?, EBIl, EBLi) are taken out. This signal SN is supplied to the waveform shaping circuit (3) to form a signal S22 as shown in FIG. 33i) to (33g).

Further, during double speed playback, the window signal generation circuit (34) generates window signals SW2 and SVS as shown in FIG. 332) and (33
s) as a gate signal, and therefore, only the rising edge of the signal S2* that entered during the period of the window signals Sw2 and SVS is substantially taken out to the output side of the gate circuits (332) and (33s). As a result, the output side of the OR circuit (35) on the output side of the gate circuits (332) and (33g) receives a signal S as shown in FIG.
A narrow signal S2i that coincides with the rising edge of 22 is obtained.

This signal 323 is supplied to a delay circuit (36).

Also, at this time, the delay time setting circuit (38) is selected in the selector (37), and the delay time ta is set in the delay circuit (36).
is set for. During the period tB, the delay circuit (36) generates a signal 324 delayed by a time ta from the signal 323, as shown on the left side of the sixth diagram, and during the period t^.
Then, as shown on the right side of the sixth diagram, a signal 324 matching the signal S23 is generated.

This signal S24 is supplied to the pulse generation circuit (43),
Based on the signal 524, as shown in FIG. 6M, a pulse Pi corresponding to each pilot signal to be detected is detected.
is formed and supplied to the sampling pulse generation circuit (44) and the peak hold circuit (21).

Note that during this double speed reproduction, one tracking error signal is obtained only during the rainy periods of periods tB and t^, that is, one rotation period of the head.

Therefore, in this case, for example, in the period tB, the pilot signal that appears last in the central area of the track being scanned by the first pulse Plx of the pulse Pi from the pulse generating circuit (43), that is, the head (IB) is ) and (583), the 6th vI! As shown in JH and M, the crosstalk of the pilot signal PB4 of the track (5A2) is held at its peak by the peak hold circuit (21), while in the period tA, the pulse generation circuit (
The pilot signal that first appears in the central area of the track being scanned by the second pulse P12 of the pulse Pi from 43), that is, the sixth pilot signal when the head (IA) scans across tracks (5A3) and (5B4). The pilot signal P^1 of the truck (584) as shown in Figures H and M
0 crosstalk is held at its peak.

Therefore, in this mode, the pulse generating circuit (43) generates only the first pulse Pt1 of the pulse Pi during one scanning period of the head, for example, the period te, and generates only the first pulse Pt1 of the pulse Pi during the other scanning period of the head, for example, the period tA. 2 pulse PL2
only occur.

As mentioned above, for example, when the bed (IB) scans across two tracks (5A2) and (5B3), the pilot signal PB in the area A TI+
The crosstalk of 4 is the pulse P of the pulse generation circuit (43).
i's first pulse Pt1 (Fig. 6M) is peak-held in the peak-hold circuit (21), and the output of the peak-hold circuit (21) at this time is the sampling pulse SP1 (
In order to make the polarity the same as the tracking error signal sampled in the sampling hold circuit (22) by the N in FIG.
3) and the adder (61).

Also, the head (IA) has two tracks (5A3) and (
5B4), the crosstalk of the pilot signal P^1° in the area ATO peaks at the second pulse P12 of the pulse Pi of the pulse generation circuit (43) (Fig. 6M). Hold circuit (21
), and the output of the peak hold circuit (21) at this time is output to the sampling pulse generation circuit (21).
Sampling link pulse SP2 from 44) (Fig. 6 O)
The signal is sampled by the sampling hold circuit (66) and supplied to one input terminal of the subtracter (23) and the adder (61).

Then, the multiplication output of the subtraction output and the output obtained by dividing the reference signal by the addition output is sent to the sampling hold circuit (24) from the sampling pulse generation circuit (44) as a sampling pulse SP3 (not shown).
(generated in response to a pulse Pta (not shown)), and is sent to the output terminal (26) via the contact a side of the switch circuit (25) as a tracking control signal.
) is derived.

This derived control signal is supplied to the capstan motor to control the amount of tape transport, so that the head (IB) can move between the tracks (5A2) and (5B3) and the head (IB).
When A) scans over two tracks (5A3) and (5B4), the rotary head is controlled so as to draw a scanning locus as shown by the broken line TD in FIG.

Note that in the double-speed playback described above, the crosstalk of the pilot signal recorded in the center area of the track being scanned is used, but as shown in the 61st WPNR, the crosstalk of the pilot signal recorded in the center area of the track being scanned is used. It is also possible to utilize the crosstalk of pilot signals recorded in

For example, in the period tB, the crosstalk of the biloft signal P^11 that appears last in the end region of the track being scanned is detected by the peak hold circuit (21) as the first pulse Ptz of the pulse pt shown in FIG. 6P. On the other hand, during the period tA, the crosstalk of the pilot signal PBT that appears last in the beginning region of the trunk being scanned is held in the peak hold circuit (21) by the second wave of the pulse Pi as shown in FIG. 6P. The peak is held at pulse P12.

Then, during period tB, the output of the peak hold circuit (21) is sampled in the sampling hold circuit (22) by a sampling pulse SP1 as shown in FIG. Similarly, the output of the peak hold circuit (21) is supplied to one input terminal of the subtracter (23) and the adder (61), and during the period tA, the output of the peak hold circuit (21) is sent to the sampling pulse generation circuit (60).
44) is sampled by the sampling pulse SP2 as shown in FIG. The output multiplied by the calculated output is used as the sampling pulse SP from the sampling pulse generation circuit (44) in the sampling hold circuit (24).
3 and output it to the output terminal (26) as a tracking control signal.

In this case, in response to the setting command signal from the mode setting circuit (32), the window signal generating circuit (34) generates the window signals Swa and SW4 as shown in the sixth diagram and E. Only the rising edge of the signal S2t that entered during the period of the signals Swa and SW+ is extracted and the signal 523 (K in Fig. 6) is sent to the output side of the OR circuit (35).
Try to get the following.

At this time, the selector (37) also selects the setting circuit (39).
) is selected and the delay time tb is set for the delay circuit (36), and a signal 524 (Fig. 6L) delayed by the time tb from the signal S23 is generated on the output side, and this is sent to the pulse generating circuit. (43) to obtain a pulse Pi as shown in FIG. 6P described above.

Also, when playing at 3x speed, adjacent tracks (5x
A) Even if (5B) has a different azimuth angle,
Since the rotary heads (IA) and (IB) alternately scan with a three-track pitch, the heads do not scan tracks with different azimuths as in the case of double speed. Therefore, in this example, the rotary head is controlled so as to draw a scanning locus as shown by the two-dot chain line TT in FIG.

Now, for example, if the head (IB) is
When scanning a range of scanning width W including a track (5B3) as shown by T, the head (IB) scans the tracks (5A3) (5^) on both sides of this track (5Bi).
2) and scan across the area AT as shown in Figure 3.
In L, the pilot signal PA of the truck (5B3)
T and the pilot signal p of the trucks on both sides (5A3)
Pilot signal PR2 of et and truck (5A2)
and in area AT2, the adjacent tracks (
5A3) pilot signal PBi□ and track (5A3)
2') pilot signal PBa and the track (5B3)
The pilot signal pAtt is regenerated. At this time, the playback output of the head (IB) from the switch circuit (19) is transmitted through a narrow band pass filter (20
), and as shown in FIG. 7J, only the pilot signal is taken out as its output sF, and this is supplied to the peak hold circuit (21).

Further, the output sR of the switch circuit (19) is supplied to the bandpass filter (29) in the same manner as described above, and this produces an erasing signal Si (typically E^?+'E
＾9+, E＾1□) are extracted. This signal SI+
is supplied to the waveform shaping circuit (30) and converted into a signal s2s as shown in Figure 7, and then sent to the rising edge detection circuit (31).
), where its rising edge is detected and supplied to gate circuits (331) to (33@).

In addition, during triple speed playback, the window signal generation circuit (34) generates window signals SW2 and SV6 as shown in FIGS. ) and (33
g) as a gate signal, therefore, on the output side of these gate circuits, the wind signals SV2 and S
Only the rising edge of the signal 322 input during each period of 1/6 is substantially taken out, and as a result, the gate circuit (33
As shown in FIG. 7M, a narrow signal S23 corresponding to the rising edge of the signal SH2 is obtained on the output side of the OR circuit (35) on the output side of 2) and (33s).

This signal S23 is supplied to a delay circuit (36).

However, in this case, as in normal reproduction, the signal S23 coincides with the vicinity of the center of the pilot signal to be sampled, so there is no need to delay it. No setting is made, and the delay circuit (36) generates a signal 324 that matches the signal S23, as shown in FIG. 7N.

This signal 324 is supplied to the pulse generation circuit (43),
Based on the signal S24, a pair of pulses Pi corresponding to each pilot signal to be detected is formed as shown in FIG.
) and a peak hold circuit (21). Based on the pair of pulses pt, the sampling pulse generation circuit (44) generates sampling pulses SPi and SF3 as shown in FIG. pulse SP
3 are generated, and the respective sampling and hold circuits (22
), (60) and (24).

Therefore, while scanning the track (583) with the head (IB), as is clear from FIG.
The pulse pt□ is applied to the peak hold circuit (21
), the output of the peak hold circuit (21) at this time is supplied to the sampling hold circuit (22), and the first pulse pH is
It is sampled by the sampling pulse SP1 generated at the falling edge of , and is supplied as an advanced phase tracking signal to one input terminal of the subtracter (23) and the adder (61) as in the normal reproduction.

Further, the second pulse PL2 of the pulse Pi is the pilot signal PB4 of the adjacent track (5A2) on the tape transport direction side.
The peak hold circuit (21) holds the crosstalk at its peak, and the output of the peak hold circuit (21) at this time is output to the sampling hold circuit (21).
60), which is sampled by the sampling pulse SP2 generated at the falling edge of the second pulse P12, and sent to the other input terminal of the subtracter (23) and the adder (61) for tracking of the delayed phase. Supplied as a signal.

Therefore, the subtracter (23) and adder (60) subtract and add tracking signals corresponding to the crosstalk between pilot signals PBs and PH1, respectively. Then, the multiplication output of the subtraction output and the output obtained by dividing the reference signal by the addition output is supplied to the sampling and hold circuit (24), where it is sampled by the sampling pulse SP3.

Therefore, from this sampling hold circuit (24), the output of the multiplier (64) is obtained as a tracking control signal, and this is sent to the capacitor (not shown) from the output terminal (26) via the contact a side of the switch circuit (25). The tape is supplied to the stun motor to control the tape transport amount, and the head (IB) draws a scanning trajectory as shown by the two-dot chain line TT in FIG. It will be ll11iIT.

The same process is applied to other trucks, for example, the truck (5B3) that is 3 trunks later than the truck (5B3).
When the head (IA) scans the 5A4) as indicated by the two-dot chain line T in FIG. 3, as shown in the right part of FIG. 7 J,
Truck (5A4) pilot signal P R$+P
Bio l P B12 and the trucks on both sides of it (5
Bs) and (5B4) biloft signals P^13. P^
1s+PA1v and P^8+ PAlo I PA12
Since crosstalk is obtained, the central part (area A) of the adjacent tracks (5Bs) and (5B4)
Pilot signals PALG and P recorded in TS)
Alo's crosstalk is sequentially peak-held by the peak-hold circuit (21), and the sampling pulse generation circuit (21)
The biloft signal P is generated by the sampling pulse SPs supplied from 44) to the sampling hold circuit (22).
^, S crosstalk is sampled to obtain a tracking signal, and this is sent to the next stage subtractor (23) and adder (6).
1), and also supplies the output from the peak hold circuit (21) corresponding to the crosstalk of the biloft signal P^1o to the sampling hold circuit (60), samples it with the sampling pulse SP2, and obtains a tracking signal. a subtracter (23) and an adder (61)
). And here, the pilot signal PA□
The tracking signals corresponding to the crosstalk of 5 and P^□0 are subtracted and added, and the multiplication output of the subtraction output and the output obtained by dividing the reference signal by the addition output is supplied to the sampling hold circuit (24). Sampling pulse SP3
By sampling with , a tracking control signal for the head (IA) can be obtained.

Note that during the above-mentioned 3x speed playback, the crosstalk of the pilot signal recorded in the center area of the track being scanned is used, but as shown in Figure 7 RT, Crosstalk of pilot signals recorded at the ends of the tracks may also be used.

For example, during the period tB, the pilot signal PB appears last and first in the beginning and end regions of the track being scanned, respectively.
2 and PIIll in the peak hold circuit (21) as shown in FIG. 7R.
The first pulse pH and the second peak hold at <rus P12, while in the period tA the pilot signal P appearing second in the beginning and end regions of the trunk being scanned, respectively.
The crosstalk between AII and pAlt is controlled by a pulse P as shown in FIG. 7R in the peak hold circuit (21).
The peak is held at the first pulse Pit and the second pulse P12 of i.

Then, in the period tB, the output of the peak hold circuit (21) (corresponding to the pilot signal PB2) is processed by the sampling pulse SP1 as shown in FIG. 7S from the sampling pulse generation circuit (44) in the sampling hold circuit (22). The peak signal corresponding to the pilot signal PB11 is sampled and supplied to the other input terminal of the subtracter (23) and the adder (6D) in order to have the same polarity as the tracking error signal during normal playback. The output of the hold circuit (21) is transferred to the sampling and hold circuit (
60) to the sampling pulse generation circuit (44)
The sampling pulse SP2 as shown in FIG. 7T from
The sampled signal is sampled and supplied to one input terminal of the subtracter (23) and the adder (61). Then, the multiplication output of the subtracted output and the output obtained by dividing the reference signal by the addition output is used as the sampling pulse S from the sampling pulse generation circuit (44) in the sampling hold circuit (24).
The signal is sampled by P3 and is output to the output terminal (26) as a tracking control signal. Also, during the period tA, the pilot signals PA8 and P/
'u? Perform the same operation for .

At this time, in response to the setting command signal from the mode setting circuit (32), the window signal generating circuit (34) generates the wind signal S as shown in FIG. 7 C, E, F, and H.
w1. Sva and S V4 * S wl+ are generated and the signal 321 entered during these window signals.
Only the rising edge of 1 is taken out, and a signal 523 (M in FIG. 7) is obtained at the output side of the OR circuit (35).

At this time, the selector (37) also selects the setting circuit (38).
) is selected, a delay time ta is set for the delay circuit (36), a signal 524 (N in FIG. 7) delayed by a time ta from the signal 323 is generated on its output side, and this is sent to the pulse generating circuit (36). 43) to obtain a pulse Pi as shown in FIG. 7R described above.

In addition, in this embodiment, as described above, the frequency f of the erasing signal E is selected in advance to a value with a relatively large azimuth loss, so that the head can detect the azimuth and the azimuth of the track being scanned. The relationship between the two can no longer be ignored, and the crosstalk component of the erasing signal E will be reduced accordingly if the azimuth differs, that is, if the track shifts from the track being scanned and enters an adjacent track.

Therefore, in this embodiment, when the amount of trunk deviation of the head is within a predetermined range, the normal operation of detecting the tracking error output according to the amount of track deviation and performing tracking control as described above is performed, and the amount of track deviation is When the predetermined range is exceeded, the control amount is fixed at a certain potential Vcc, thereby forcibly controlling the tracking of the head. The reference values to be compared at this time are the reproduced output of the erasing signal E (reverse azimuth) of the adjacent trunk when the head is scanning a track with the same azimuth, and the reproduction output of the erase signal E (reverse azimuth) when the head is scanning a track with the same azimuth. Among the playback outputs of the erasing signal E (same azimuth) of the adjacent trunk when The maximum value is determined so that it is smaller than the reproduced output of the erasing signal E for that track when it is present, and the reference value is set anywhere between the minimum value and the maximum value.

Furthermore, to explain in detail the setting of this reference value, in order to set this reference value without considering the influence of jitter etc.,
For example, in FIG. 3, the head (IB) is connected to the track (5
82) with just tracking, the maximum value is smaller than the playback output of the erasing signal EA2 of the same azimuth, and the minimum value is the adjacent track (5A2) or (5A1).
The adjacent track (5B3) when scanning a reverse azimuth track (5A2) or (5A1) with just tracking, which is larger than the playback output of the reverse azimuth erase signal EB2 or EBl and whose head (IB) is shifted by one track.
) or (5B2) erasing signal EA? Or playback output of EA2 (both azimuths) or adjacent track (5B2
) or (581) to be larger than the reproduced output of the erasing signal EA2 or E^1 (both have the same azimuth), and set the reference value within the range of this maximum value and minimum value.

However, if there is an effect such as jitter, the recording time of the erasing signal E must be at least shorter than the recording time of the pilot signal P (corresponding to -tp in this embodiment) as in this embodiment, which causes problems during scanning. Since the erasing signals E of both adjacent tracks partially overlap and the starting edge of the erasing signal E cannot be detected, a self-clock cannot be formed and there is a possibility that tracking control may malfunction.

For example, if the end of the erase signal EAT and the start of the erase signal E^2 overlap due to the influence of jitter, etc., the head (IB) will shift by one track and the track (5A2) with the opposite azimuth will be moved. Erasing signals EAT and EA2 that have the same azimuth when scanning with just tracking
The sum of the reproduced outputs will be detected.

As mentioned above, EA is one of the conditions for the minimum value of the reference value. Alternatively, even if it is determined to be larger than the playback output of EA2, it may cause malfunction. Therefore, in this case, the minimum value needs to be at least larger than the sum of the above-mentioned erasing signal E^7 and the playback output of EA2. , the range for setting the reference value in the comparator circuit (51) becomes narrower.

Therefore, in this embodiment, the erasing signal E is recorded as described above, and its starting end is the pilot signal P of the adjacent track.
In other words, the recording time of the erasing signal E should be at least shorter than the recording time of the pilot signal P. In this way, duplication of the above-mentioned erasing signals E is avoided. Therefore,
In this embodiment, it is no longer necessary to set a reference value that takes into consideration the overlap between these overlapped cancellation signals E, and the minimum value can be set wider, so even if there is an influence of jitter etc., the reference value This allows you to set a wider range of values.

Incidentally, in this embodiment, the minimum value of the reference value is the reproduction output of the erasing signal E (reverse azimuth) of the adjacent track when the head is scanning tracks of the same azimuth, and the
Among the playback outputs of the erasing signal E (same azimuth) of the adjacent track when scanning a track with a reverse azimuth shifted by one track, the playback output is determined to be larger than the playback output of the higher level one, and the maximum value is This can be determined in the same manner as described above.

It should be noted that the influence of jitter within time -tp can be sufficiently absorbed mechanically.

Therefore, if the detected crosstalk output of the erasing signal E exceeds this reference value, the signal S
23 is ordered, and sampling pulses SPI, SF3, and SF3 are formed based on this, but if it is less than the reference value, the head is already scanning the reverse track and the signal S
23 is not generated, therefore the sampling pulse SPt
, SF3. SF3 is also not formed.

Therefore, in this embodiment, the erasing signal E
If the crosstalk output is less than this value, it is assumed that the head is significantly out of track, and the head is forcibly shifted to the correct position.

This operation is performed by the circuits after the comparator circuit (51) shown in FIG. The operation of this circuit will now be explained with reference to FIG.

Now, a filter (2) is connected to one input side of the comparator circuit (51).
9) as shown in FIG. 8H. When supplied, this signal Sl is compared with the reference value from the reference power supply (52) supplied to the other input side of the comparison circuit (51) (7°), and if the signal SH is larger than the reference value, the comparison circuit ( 5
1), a signal 325 as shown in FIG. 8C is generated and supplied to the flip-flop circuit (53) as a latch pulse. On the other hand, prior to the generation of this signal S25, the switching signal 81' (
When the falling edge of FIG. 8H) is detected, a signal 82e as shown in FIG. 8H is generated on its output side, and the flip-flop circuit (53) is reset as shown in FIG. 8H.

Further, the input terminal of the flip-flop circuit (53) is supplied with a switching signal 81 as shown in FIG. When the (latch pulse) is supplied, a high level (H) signal 5211 is generated on the output side as shown in FIG. 8H, and is supplied to the next stage flip-flop circuit (57).

In addition, the switching signal 81' is detected by the rising edge detection circuit (56).
When the rising edge of the signal S27 is detected, a signal S27 as shown in FIG.
57) is supplied to the clock terminal.

At this point, a high level signal S29 is generated on the output side of the flip-flop circuit (57) as shown in FIG. 8I, and is supplied to the switch circuit (25) as a switching control signal. The switch circuit (25) is connected to the signal S29.
When is at a high level, it is connected to the contact a side, so that a tracking control signal from the sampling hold circuit (24) side is derived to the output terminal (26).

On the other hand, if the signal S is below the reference value, the comparator circuit (51
) is not generated at the output side of the flip-flop circuit (53), so the flip-flop circuit (53) remains reset to the signal S2@, and its output signal 328 is at a low level (L) as shown by the dashed line in FIG. 8H. is maintained. In this state, the output signal 329 of the flip-flop circuit (57) is also at a high level as shown by the broken line in FIG. 8I.

Then, at the rising edge of the switching signal Si', the detection circuit (56)
When the signal 527 (FIG. 8G) is supplied from the flip-flop circuit (57), the output signal S29 of the flip-flop circuit (57) changes from high level to low level as shown by the broken line in FIG. 329 is supplied to the switch circuit (25), and the switch circuit (25) switches to the contact side. As a result, the output terminal (26) has a constant potential V from the terminal (58).
A signal with cc is derived, and this signal is supplied to a capstan servo system (not shown) to perform tracking control.

For example, when the constant potential Vcc is positive, the tape is advanced through the capstan servo system, so the head essentially moves to the next track corresponding to its own p azimuth and performs a normal tracking operation. Also, the potential Vcc is 0
In this case, the tape advance is slowed down so that the head is essentially pulled back to the track it is currently scanning, thereby entering normal tracking operation.

In this way, in this embodiment, the signal E for erasing the pilot signal has a frequency with a relatively large azimuth loss, and is also used as a positioning signal for the pilot signal. The circuit configuration can be simplified and its performance can also be improved.

Furthermore, in this embodiment, during playback, the pilot signal is detected substantially based on the starting edge of the playback output of the erase signal E recorded in the track, and the sampling pulse is self-generated. Since the self-clock is generated substantially from the track pattern, there is no adverse effect when the pulse PG, such as an offset, is used as a reference.

In addition, an erasing signal E having a frequency where azimuth loss is effective
When the crosstalk output of the head is below the reference value, the control amount is forcibly fixed at a constant potential to perform head tracking control, which enables highly accurate tracking control.

In addition, each head generates a sampling pulse as described above during each scanning period of each head to detect the tracking position. In other words, each head generates a self-clock as a sampling pulse each time on the track pattern, and each track Since the tracking position is detected, the influence of jitter is also eliminated.

Furthermore, in each reproduction mode, the detection position of the pilot signal can be determined by essentially using the edge of the signal E for erasing it, or by switching the delay time from this edge, so most of the circuit configurations can be shared. can be converted into

Furthermore, since we are recording in such a way that the starting edge of the erasing signal E, which detects the position of the pilot signal, is located near the center of the pilot signals of the adjacent trunk, we take the trouble to set the starting edge of the erasing signal E to the position of the pilot signal. There is no need for a circuit for delaying the position near the center, and the circuit configuration is simplified accordingly. Furthermore, since the recording time of the erasing signal E is made to be at least shorter than the recording time of the pilot signal P, the erasing signal E of adjacent tracks is held at a predetermined interval, and therefore, the recording time due to the influence of jitter etc. The erasing signal E that has been erased does not substantially overlap between adjacent tracks.
It is possible to provide a margin for the setting range of the reference value in 1).

FIG. 11 shows a second embodiment of the present invention, in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the above embodiment, the sampling and holding circuit (22)
, (60) are added, the reference signal is divided by this added output, and multiplied by the subtracted output. However, in this embodiment, the sampling and hold circuits (22), (60) are
), one of the outputs having a higher level is detected, the reference signal is divided by this detection output, and the result is multiplied by the subtracted output.

Therefore, a gate circuit (65) is provided on the output side of the peak hold circuit (21). And this gate circuit (65
) from the sampling pulse generation circuit (44) to obtain the gate signal of the sampling pulse SP1. An OR circuit (66) to which SP2 is supplied is provided, its output is supplied to the clock terminal CK of a D-type flip-flop circuit (67), and the output from the output terminal Q of this flip-flop circuit (67) is used as a gate signal. The signal is supplied to the gate circuit (65). In addition, here is a flip-flop circuit (
The input terminal 1 and the inverting output terminal Q of 67) are used while being interconnected.

The output of the gate circuit (65) is sent to the peak hold circuit (68).
), where the peak is held.

That is, the output with the higher level among the outputs of the sampling and hold circuits (22) and (60) is held. And peak hold circuit (6B)
The output from the sampling and holding circuit (69) is sampled and held by the sampling pulse SP2 from the sampling pulse generating circuit (44), and is supplied to the divider (63).

After that, as described above, the reference signal from the reference signal generation circuit (62) is divided by the output of the sampling hold circuit (69) in the divider (63), and the output of this division is sent to the subtracter in the multiplier (64). (23) is multiplied by the subtraction power from (23). This multiplication output is then supplied to the sampling hold circuit (24), where it is sampled by the sampling pulse SP3 from the sampling pulse generation circuit (44), and is sent as a tracking control signal via the contact a side of the switch circuit (25). Output terminal (26)
is derived.

Therefore, in this embodiment as well as in the above-mentioned embodiments, even if there is a level fluctuation in the crosstalk of the pilot signal due to variations in the tape or rotating head, the servo gain can always be kept constant and reliable tracking control can be performed. be.

Each of the above-mentioned embodiments is a special rotary head device that records and reproduces data by winding the tape over an angular range narrower than the head angular interval. Of course, the present invention can also be applied to the case where a rotating head device for winding is used.

Also, the central area AT3 where the viroft signal etc. are recorded may be deleted and the PCM signal recorded in this area as well. In that case, there is no problem as tracking control can be performed using the pilot signals at both ends. .

Effects of the Invention As described above, according to the present invention, the difference between the tracking error signals of adjacent trunks is calculated, and the reference signal is divided by at least the tracking signal with a higher level among the respective tracking error signals, and this and the above-mentioned tracking signal are divided. Since the amplification factor of the transmission system to the tracking servo system is adjusted by signal processing that multiplies the difference signal, even if the crosstalk level of the pilot signal fluctuates due to the combination of the recording medium and the rotating head, etc. Even in the case of a servo-based system, it is possible to always achieve servo-based stabilization and reliable tracking control.

In addition, when scanning a recording track with a rotating head, the relative azimuth loss that has its starting end near the center of the pilot signal of the adjacent track and is recorded so that it is shorter than the recording time of the pilot signal is A pulse signal is formed to detect this pilot signal using the starting edge of the erasing signal E having a large frequency as a reference, and a tracking control signal based on the detection output is used to control the tracking of the rotary head, and a re-output of the erasing signal E is performed. When is below the reference value, the control amount is fixed at a constant potential and tracking control of the rotating head is performed.
Even if the device has mechanical changes over time, temperature changes, or jitter, it will not be affected in any way, and even if the device is different from the one used for recording, tracking control during normal playback or variable speed playback can be performed with high accuracy. can be done,
It is possible to achieve compatibility between the gas appliances.

Furthermore, since the erasing signal E for detecting the position of the pilot for tracking control is recorded so as to have its start end near the center of the adjacent pilot signals, it is necessary to locate the start end near the center of the pilot signals. This eliminates the need for a delay circuit, and simplifies the circuit configuration accordingly.

Furthermore, the recording time of the erasing signal E is made to be at least shorter than the recording time of the pilot signal P, and the erasing signals E of adjacent tracks are separated by a predetermined interval. Compared to the case where the track erasing signals E are recorded adjacent to each other, the setting range of the reference value in the comparator circuit (51) can be expanded, and the influence of jitter is also reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the rotary head device used in FIG. 1,
3 is a diagram showing an outline of the recording track pattern of the present invention, FIG. 4 is a signal waveform diagram for explaining the recording operation in FIG. 1, and FIG. 5 is a diagram for explaining the normal reproduction operation in FIG. 1. 6 is a signal waveform diagram for explaining the double speed playback operation in FIG. 1, and FIG. 7 is a signal waveform diagram for explaining the triple speed playback operation in FIG. 1. , FIG. 8 is a signal waveform diagram for explaining the reproduction operation in FIG. 1, and FIGS. 9 and 10 are
The figure is a diagram for explaining this invention, No. 11w! J
FIG. 2 is a circuit configuration diagram showing another embodiment of the present invention. (IA) (IB) is a rotating magnetic head, (2) is a magnetic tape, (6) is a pilot signal oscillator, (6A),
(6B) is an erase signal oscillator, +71. (7A)
, (7B) is a recording waveform generation circuit, (1B), (17A
) ~ (17E). (36) is a delay circuit, (8A) and (8B) are edge detection circuit R1 (20), (29) is a bandpass filter,
(21) and (6B) are peak hold circuits, (22)
. (24), (60), (69) are sampling and holding circuits, (23) is a subtracter, (25) is a switch circuit, (30) is a waveform shaping circuit, (31), (56) is a rising edge detection circuit, (32) is a mode setting circuit, (331
) to (33ε) are gate circuits, (34) are window signal generation circuits, (37) are delay time setting selectors, (3B)
. (39) is a delay time setting circuit, (43) is a pulse generation circuit, (44) is a sampling pulse generation circuit, (51)
is a comparison circuit, (52) is a reference power supply, and (53). (57) is a D-type flip-flop circuit, (56) is a falling detection circuit, (61) is an adder, (62) is a reference signal generation circuit, (63) is a divider, (64) is a multiplier, (6
5) is a gate circuit, (66) is an OR circuit, (67) is a D
It is a type flip-flop circuit.

Claims (1)

[Claims] In a digital signal recording and reproducing device that compresses the time axis of a digital signal, forms and records diagonal tracks on a recording medium using a plurality of rotary heads without forming a guard band, and reproduces the same, adjacent tracks are a subtracting means for calculating the difference between the tracking error signals of the subtracting means; a transmission system for transmitting the output of the subtracting means to the drive system; and a tracking error signal having a higher level among the above-mentioned tracking error signals, which is compared with a reference signal. A tracking control circuit comprising: comparing means, and adjusting an amplification factor of the transmission system based on the output of the comparing means.