JPS60259066A - Picture data compressor - Google Patents

Abstract

PURPOSE:To relieve the load of the succeeding MH code generation by generating forcibly a modified huffman (MH) code at a point of time when a 2560-bit picture element is generated even if a change point of a picture is not caused for a long time. CONSTITUTION:The MH code is generated by an output of an OR circuit 217. The OR circuit 217 is controlled by a 2560 detection signal from an NAND gate 210, an inverted change point detection signal from an exclusive OR gate 225 via an inverter, an end of line (EOL) detection signal from an NAND gate 226, a line end signal from a line counter and a low level output from an NAND gate 219. Thus, the EOL code is inputted to the head of one lineof the picture and the EOL code for 5 clocks' share is inputted at the end of one page and the MH code corresponding to the length of line at the point of time by using the change point detecting signal and the line end signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image data compression device used for facsimiles, image electronic files, etc., and particularly to an image data compression device suitable for high-resolution image processing.

Conventional image transmission devices such as facsimile machines and recent image file devices using optical disks, magnetic disks, etc. compress and handle image data to reduce the amount of data, speed up transmission or storage operations, and improve efficiency. is planning to change.

Such image compression is a type of so-called code conversion operation, and in the case of Modified Hoffman (MH) encoding, which is a typical compression method, the number of consecutive white or black pixels in an image is converted to another code. It is expressed in correspondence with the code.

At this time, the number of pixels that occur frequently is associated with a code code with a short code length, while the number of pixels that occur with a low frequency is associated with a code code with a long code length. This method utilizes the bias in the frequency of occurrence to express the entire image using a different code string with a smaller number of bits.

In addition, in the data format by MH encoding, an EOL (end of line) code that indicates a break between a group of MH here corresponding to an l-line image and an RTC (return to call) signal that indicates a break between one page of images are defined. . The receiving side, that is, the decoding processing device performs synchronization of decoding operations based on these EOL codes and RTC signals.

In recent years, printers capable of recording high-speed, high-resolution images, such as laser beam printers using an electrophotographic process, have been developed, and it is now possible to reproduce (record) compressed images using such printers. It is as desired. Along with this, high speed is desired for leagues and the like that optically read images to be reproduced by printers, and even higher speed compression and decoding processing is required.

Here, the formation of the EOL code and RTC signal, which play the important role as mentioned above, is also a big issue.In particular, in real-time and high-speed transmission, each part of the league, compression device, printer, etc. operates independently at high speed. A suitable EOL code and RTC signal formation mechanism is required to achieve this processing.

The present invention has been made in view of the above, and provides an image data compression device that enables high-speed and real-time compression processing. Specifically, the present invention is to provide an image data compression device that enables high-speed and real-time compression processing. means for inputting image data; means for compressing image data to be input; means for generating a code indicating the division of l lines by a line synchronization signal synchronized with the input of each line of image data; The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view of a cylinder to which the present invention is applied.

In the figure, 201 is a document table glass, 202 is a bar-shaped light source such as a halogen lamp or a fluorescent lamp, 205 is a first mirror, and 204
is the second mirror, 205 is the third mirror, 206 is the second mirror,
207 is a one-dimensional object imaging device such as COD.

To explain the operation of the apparatus, an fc original placed on an original table glass 201 is illuminated by a rod-shaped light source 202, and an ear 1 mirror 203 and a second mirror 20 scan (sub-scan) the original.
An image is formed on the C0D 207 by the lens 206 via the 4, 777, 3 mirror 205. The main scanning direction of the C0D 207 is perpendicular to the drawing. Rod-shaped light source 2
02 and the first mirror 203 are integrally connected to a support (not shown) and are connected to a guide rail (not shown). While moving in the direction, the original ÷ A plane is scanned (sub-scanning). Second
The mirror 204 and the fifth mirror 205 are integrally connected to each other by a support (not shown), and move in the same direction as the first mirror 203 at a speed of 1/2 of the moving speed of the first mirror 203 on a guide rail (not shown). The six bar-shaped light sources 202, the first mirror 203, the second mirror 204, and the third mirror 205 moving above move from the reading start position shown by the solid line in the figure to the reading end position shown by the dotted line (202', 203', 204', 205'), but at this time, the optical path length from the document table 201 through the mirrors 205°2 (14, 205 to the lens 2061) is always kept constant.

Note that this league device sub-scans an A4 size document in the transverse direction, and the linear density of the reading is 16 Line/rQm. Further, the resolution in the main scanning direction is 16 Pel/mm. Therefore, output bit a 11 by one main scanning line
This main scanning is performed for 4752 lines with S560 bits.

208 is a document 5 scanning start sensor, and 209 is a document reading end sensor. Yes, both sensors are composed of, for example, a photo interrogator, and are activated by an operation piece (not shown) provided on the Wc1 mirror 205, and when the first mirror 206 is located at a position corresponding to the respective sensor position. After the sensor output is completed and the reading of the document is completed, the mirror and light source described above quickly return to the solid line position.

FIG. 2 is a circuit diagram showing an example of the drive circuit 00D 207 shown in the first diagram. 207 is 00D (
photoelectric conversion element). 901 is a crystal oscillator that generates a clock signal OLK, which serves as the epaulet of the image reading operation;
2 is a counter that counts the clock signal from the crystal oscillator 901, and upon input of the shift pulse 907 instructing the start of shift register transfer at f:0D207, its output 908 is output 908 when the count ends from 7 to 5L60 in the example). is set to low level. This output 908 is used as a video enable signal V[iiN (horizontal synchronization signal) to be described later.

904 is QC! This is a ψ converter for converting the analog output of the level corresponding to the density of the image outputted from D 207 into a 4-bit digital signal, and it compares the voltage divided by the resistor R with the input analog signal. , output D0~D
It consists of four comparators that output . The 4-bit digital signal from the A/I converter 904 is sent to the binarization circuit 90
At step 5, the output signal is binarized by comparison with a fixed threshold value or binarized for halftone reproduction using a dither method, and is further output as a serial signal synchronized with the aforementioned clock signal CLK at a synchronization circuit 906. Ru.

This serial signal is a binarized image signal.

FIG. 6 is a schematic diagram of the OOD 207. il is an output transistor, and 306 is a capacitor memory that holds the output voltage. Further, 302 is a reset switch that resets the charge of the capacitor memory 303.

Reference numeral 506 is a photosensitive section, which includes a photodetector element 1.2 for each pixel.
It has... Reflected light from the original enters the photosensitive section 306, and each of the light receiving elements 1, 2, . . . is charged with an electric charge corresponding to the strength of the light. Light receiving elements 1, 2...
The charges respectively charged in the pixels are divided into even pixels and odd pixels, and shifted in parallel to COD shift registers 304 and 505, respectively.

The timing of this shift is determined by the shift pulse 907 described above.
0 input timing), the shift gates 306 and 308 are turned on by this shift pulse.

00D shift register 5'04, 505f-1 clock bus φ1. The charges are sequentially transferred to the left in the drawing by φ2, and charges corresponding to even-numbered pixels and odd-numbered pixels are alternately sent to the output register 01.

FIG. 4 shows a serial signal VB based on the outputs of the original reading start sensor 208 and the original reading end sensor 209.
This is a circuit for forming an XNO. The two Nant gates 403 and 404 constitute a well-known flip 70 tube. The input 401 of the Nant gate 405 receives the sensor output of the original reading start sensor 208, and the input 402 of the Nant gate 404 receives the sensor output of the original reading end sensor 209.
Apply the sensor output of As a result, the output 405 of the shift flip prop remains at a high level from the sensor output of the original reading start sensor 208 to the sensor output of the original reading end sensor 208. This high level signal is the vertical synchronizing signal VSYNC, that is, the vertical synchronizing signal VEYNO is
This signal is generated in synchronization with the start of reading the original by the CD 207K, and is deenergized in synchronization with the end of reading. In this embodiment, the vertical synchronization signal is generated by a position sensor of a mirror that moves at the ninth stage of scanning (reading) the original, but another method may be used, for example, by counting the number of main scans from the start of reading the CD 207.

A signal indicating the end of document reading may be generated when the count value reaches a predetermined value (9), and this signal may be used as the vertical synchronizing signal VBXMO.

FIG. 5 is a circuit diagram showing the configuration of a compression circuit that compresses the output binary image signal read by the reader shown in FIG. 1 by modified Huffman (M, H) encoding and outputs an MH code. .

The aforementioned image signal VIDffiO and clock signal OLK.

Video enable signal VEX and vertical synchronization signal VSYN
O is input.

220 and 221 are Ds operated by the clock signal OLK.
Flip-flop, video enable signal VZN
is input to the flip-flop 220, and the Q output of the flip-flop 220 is input to the flip-flop 221. Therefore, the video enable signal WIN is delayed by one clock at the flip-flop 220 and by two clocks at the flip-flop 221. The Q output of the flip-flop 220 and the Q output of the Aritub flop 221 are input to a Nant gate 226. Accordingly, multiple rises of the video enable signal VAN are detected, and when the multiple rises are detected, the output of the Nant gate 226 becomes low level. When this low level is output, one line of image @signal V
This is the input start timing of IIO, and the low level output of this Nant gate 226 is referred to as [1; OL detection signal.

222 and 224 also operate on the clock signal OLK.
The flip-flop 222 has an image signal VT D! In addition, the Q output of the flip 70 switch 222 is input to the flip 70 switch 224 via the AND gate 223.

Therefore, the image signal VTDICO is transferred to the flip-flop 22
2 for 1 clock, and flip-flop 224 for 2
There is a clock delay. Aritsubu flop 222
The Q output of the flip-flop 224 and the Q output of the flip-flop 224 are input to an exclusive-OR gate 225. Accordingly, a change point from white to black or from black to white in the image signal is detected, and when the change point is detected, the output of the exclusive OR gate 225 becomes a high repeat. The high level output of this exclusive OR gate 225 is called a change point detection signal.

218 is an 8 which performs a shift operation according to the clock signal OLK.
This is the focus foot register and the vertical synchronization signal VSYN.
Enter O, then change it from Q to Q! The output QM of the 7 shift register 218, which operates with a delay of 8 clocks, is input to the Nant gate 219 via the inverting gate 240, and the output QM also serves as another input to the Nant gate 219. As a result, the output of the Nant gate 219 becomes low level for five clocks after the fall of the vertical synchronizing signal VBYkH3. This low level output is the image signal VTDi for one page! This indicates the timing of completion of the input of O, and thereby controls the output of the RTC signal indicating the end of the image of one page.

211, 212 and 213 are 4-bit counters, which are connected in series to form a 12-pin counter. This is called a run length counter, and it counts the clock signal OLK. Note that the least significant bit of the counter 211 is set to 1.

The output of the counter 211 Q-QD, the output QA-Q, B of the counter 212, and the output of the counter 213. A
.

QD, the output QB, the output QB and Qc obtained by inverting Qo, and the inverted signal of the change point detection signal are input to the Nantes gate 210. In this case, when the count value of the 12-bit counter reaches (1oo1/111 times 1111), that is, 2559, the output of the Nant gate 21o becomes the a-level.

This low level output of the Nant gate 21o is called a 2560 detection signal.

214, 215 and 216 are 4-bit counters, which are connected in series to form a 12-bit counter, which is called a line counter, and counts the clock signal OLE. The initial set value of this line counter is set so that it can count by one more than the number of pixels for one line, which is 5560 bits. This is to make the run length counter count the same value as the run length counter, which always starts counting from 1. Then, when the clock (336o) for one line is counted up, the counter 216 outputs a 13-tuple carry signal RC. This ripple carry signal RO is called a line end signal.

Note that the counters 214 to 216 are activated by this line end signal.
is cleared.

217 is a negative logic OR circuit, and the output of the OR circuit 217 controls the generation of the ME code.

There is an input of #'i5 in the OR circuit 217, and it is ■
2560 detection signal from the Nant gate 210, ■ Signal obtained by inverting the change point detection signal from the exclusive OR gate 225 via an inverter, ■ EO from the Nant gate 226
They are the L detection signal, (1) the line end signal from the line counter, and (2) the low level output from the Nantes gate 219. If any of these five inputs becomes low level and there is a danger, the OR circuit N1217 outputs a low level.

The count value of the run length counter is cleared by the low level output of the OR circuit 217. In other words, the run length counter measures the changing points of the image signal, lie/end, and video input.
It is cleared when the cross signal VIN rises, when the vertical synchronization signal VSYN falls, or when the white or black run length exceeds 25606c. In addition, as will be described later, the a-level output of the OR circuit 217 can be used to
234 performs data acquisition.

231 to 234 are first-in and first-ara (F engineering FO) registers, respectively, and a of the OR circuit 217.
- The level output takes in the data applied to the input terminals 0° to D, and outputs the data using the UNOK signal, which will be described later. That is, the registers 252 to 234 take in the 12-bit count value of the run length counter in parallel, so the registers 252 to 234 lit: correspond to the OR circuit 21.
The run length at point 9, when point 7 becomes a low level output, is taken in. Finally, the register 231 receives the output of the OR circuit 241 at its input terminal, the Q output of the flip-flop 224 at its input terminal, and the output of the Nant gate 227 at its input terminal Ds.

The OR circuit 241 outputs a high level at either the low level output of the Nant gate 219 or the low level output (10L detection signal) of the Nant gate 226. This high level output is transmitted from the output Q0 of the register 231 to the G input of the buffer 235. As a result, the buffer 235 is placed in a 1OL code generation state, which will be described later.

That is, the &OL detection signal from the Nant gate 226 causes one clock's worth of II! If it is possible to generate an OL code, it is also possible to generate an EiOL code for 5 clocks by the low level signal of the AND gate 219. multiple fi
:Continuation of OL code is image signal VID[! of one page]
This is an RTC signal indicating completion of io.

Therefore, the pRTO signal is formed by the εOL code for five clocks.

In this way, in synchronization with the rise of the video enable signal VtC, which is the horizontal synchronization signal of the image signal VTDEliO,
The KOL code for 1 rip, or the vertical synchronization signal V B
! NC! IC0L for 5 clocks in synchronization with the falling edge of
code (i.e., an RTO signal), so that it is possible to accurately generate an IOL code at the beginning of a line of an image and an RTO signal at the end of a page of an image; In addition, the EOL code and the RTO signal are formed in real time with the image reading operation in accordance with the image reading operation of the image signal input device 1, such as a reader, to be compressed.

The input to the input end of the register 2510, that is, the Q output of the flip-flop 224 is a B/W signal, which indicates whether the input image signal is black or white.
A high level indicates black and a low level indicates white. The input signal to this input terminal D1 is input to the buffer 235 through the output terminal Q.

The Nantes gate 227 has a run length counter 21.
1 output Q A , Q D and the output Q of the counter 212
The six outputs of Q, B, and the inverted signal of the change check signal are applied, and when they all become 1, the low level output is sent to register 2! +1 input terminal 231. That is, when the lower 6 bits of the 12-bit count value are 1 (that is, the run length is 63), it can be determined that the run length is 63 or more based on this count value. Therefore, Nantes Gate 22
When the output of 7 becomes D level, it becomes 1! requires the generation of a makeup code. In this manner, the output of the NAND gate 227 is the ``M/T signal'' which indicates a make-up code at low level and a termination code at high level.

This M/T signal is delayed by one clock in flip-flop 242 and then transmitted from register 231 to buffer 235.

The buffer 255 buffers the outputs from the four FTPO registers 231 to 234 when the G input (gate input) is at a low level. However, when the EOII code is generated, the G input is at a high level, and the buffer 2
To the output of 35, 〇 to All become 1. This high level signal to the G input is the Q signal of the register 231 as described above. This is the output.

236 is a ROM for MH code generation (read only memory) and a ROM for effective code length generation.
ME codes for the white and heat run lengths are stored in ``A'', the run length data generated from the Iyo registers 231 to 234 and input via the buffer 265, the outputs of the VT multiplied signal, the Bμ multiplied signal, and the EOL. Furthermore, when it is necessary to generate the OL code, the outputs of the G input trap buffer 255 are all 1, but this signal Data is also stored in the ROM 236 to generate an EOL code.

2B7.238 is a buffer and transmits the output of the ROM 236 to the hunking circuit K239. The backing circuit 239 is a 16-bit backing circuit, and is a circuit for converting an MH code generated with an undefined length into a data string of a fixed length (16 bits).

Then, the back-upped data string of a certain length is output in parallel. Signal tTN in backing circuit 239
OK is output when 16-bit backing is completed or when the next MH code is required, and this causes j7
, outputs the data stored in the FTP'O registers 231 to 234, and outputs the data stored in the FTP'O registers 231 to 234, and outputs the data stored in the FTP'O registers 231 to 234.
Address the OM 256.

The operation of the circuit shown in FIG. 5 will be explained. The data format according to the Mu encoding method is as shown in FIG. 6 (2).

That is, the ME code indicating image data is transmitted continuously for each line, and the EOL code indicating the line break is transmitted between the lines.
A code is inserted. And M of n line for one page
Following completion of the lli code, an RTC signal is added that deviates from the sequence of multiple IL codes. Therefore, the receiving side, that is, the decoding processing device, performs synchronization for decoding using this Ion code, and also recognizes the delimitation of multiple images using the RTC signal 1. Incidentally, FIG. 6(1) tj: is the above-mentioned vertical synchronization signal V8YNO indicating the ME code period for t pages.

FIG. 7 is a diagram showing an example of the image signal VIDIUO for one line. Among the 3360 bits of one line, 515 bits of white are followed by 515 bits of black and 2530 bits of white. It is a diagram. FIG. 7(1) shows the video enable signal vEN described above, 1
It becomes high level at the beginning of the line 3360-bit image) and becomes low level at the end. Depending on the rising edge of the video enable signal v, a detection signal (6) is output from the Nant gate 226 shown in the fifth figure. Further, the change point detection signal (4) is outputted from the fifth exclusive OR gate 225 in response to the change in the image signal from white to black and from black to white. Furthermore, a line end signal (5) is outputted from the line counter shown in the figure 5 in synchronization with the end of 3660 bits.

According to this IL detection No. 43, F) EQOL code is also
Based on the change point detection signal and line end signal, the MU code corresponding to the run length at that time is generated as described above.

In the example of FIG. 8, which shows a case where all 3360 bits of one line are white, IN! Either the OIJ detection signal and the line end signal are formed in the same way as in the example shown in FIG. No MH code is generated based on . Therefore,
The Mu code for one line of image is generated only when the line end signal (5) is generated, and at this point a large amount of MH codes (for example, two makeup codes and one termination/glue code) are output. It becomes necessary. ,
However, much of the burden is concentrated when line end signals are generated.

Therefore, in this example, the 2560 detection signal from the Nant gate 210 is used as described above, and even if the change point of the image does not occur over a long period of time, the MH code is forcibly generated at the time when the 2560-bit pixel is generated. To reduce the burden of later MH code generation. Fig. 9 shows an example of using this 2560 detection signal. Fig. 49 shows a case where 1 line of 5360 in focus is all white image A9, similar to the column 8 in Fig. 8.
The EOL detection 'IN number (5) and line end signal (6) are formed in the same manner as in Figure 8, and the 256 detection signal (5)
is formed in the middle of one line. And this 2560
When a detection signal is generated, first a JH code (corresponding to a run length of 2560 bits) is generated, and then when a line end signal is generated, a MH code corresponding to a run length of 800 bits is generated.
Generates a sign. In this way, even if no change point occurs in the long-term Ki&, the M'H code generation for that point does not concentrate at one point, but can be generated separately. Furthermore, the 9th
The figure shows an example in which one line is entirely a black and white image, but if 2560 or more white or black images continue, the MH code corresponding to a run length of 2560 bits can be generated by generating a 2560 detection signal. , the ME code for the remaining run length is generated at the subsequent change point.

FIG. 10 shows the case where the image signal VID mark 0 from the league starts from a black image. That is,
This shows a case in which a 515-bit black image, a 515-bit monochrome image, and a 2,660-bit white image are input sequentially out of 6360 bits per line, and the relationship between black and white is completely reversed from that shown in Figure 7. It's in shape.

At this time, the MH code is generated from one corresponding to the run length of 515 bits of the black image.

According to the C0TTT recommendation, each line should start with a white run.

Therefore, in this case, it is natural to change the format so that the black and white image of run l length 0 is added before the black image of run 515.

However, just for this purpose, the initial ti of the run length counter is set to 0.
However, generating an MH code corresponding to a run length of 0 is disadvantageous in that the scale of the circuit is large. This is because the run length of a normal white image or the run length of a black image of image data is at least 1 bit, and moreover, it is common that the run length is longer than this.

Therefore, it is better to always set the initial value of the run length counter to 1'' as shown in Figure 5, which simplifies the circuit and saves space. As shown in FIG. 11, the first 1 bit of the initially existing h-bright image with run length 515 is replaced with a white image with run length 1.

This eliminates the need to enter the MH code of a white image with run length 0 at all.

However, in this case, naturally the first focus of the black image data will become a white image f image,
There is no problem or inconvenience in the reproduced image even if the first 1 bit out of 6560 pits in one line becomes white; in fact, the first 1 bit does not appear on the reproduced screen due to the effective area. It is I&Gate 225. That is, the IOL detection signal from the Nant gate 226 causes the 7 ring plug 2
This gates the output from 22 and forces it to a low level (white fish image) by one clot. or,
Always setting the initial value of the U/L counter to 1'' is achieved by setting the M input of the counter 211 shown in the fifth figure to a high level.
This is because there is no need for a 0 value to appear on the counter in order to output the MH code of a black and white image with a run length of 0.

Although the present invention has been described above using a facsimile as an example, it goes without saying that it can also be applied to compression processing of electronic files and other communications. Furthermore, the present invention is applicable not only to MH encoding but also to similar compression methods. As explained above, when compressing images with a relatively long run length, the timing of generation of compression codes can be separated. This prevents the burden from being concentrated at 1 o'clock.

Furthermore, even if one line starts from a black pixel, there is no need to form an MH$f number corresponding to a white image with a run length of zero, and a simple configuration can be used to create a MH$f number corresponding to a white image at the beginning of one line. , Ml (code can be generated.

In addition, in synchronization with the input of the data to be compressed, a code indicating a line break and a code indicating a page break to be added to the compression code of the image data is generated, thereby achieving high-speed and real-time compression processing. It is.

[Brief explanation of the drawing]

Figure 1 is a sectional view of a league to which the present invention is applied, Figure 2) i
A circuit diagram showing an example of an oOD drive circuit, Figure 3 is a COD
4 is a circuit diagram for forming a vertical synchronization signal, FIG. 5 is a circuit diagram showing an example of a circuit that performs E and Ill processing, and FIG. 16 is a diagram showing the data format of MH encoding. , FIGS. 7 to 11 are time charts showing the operation of the circuit in FIG. 5 with respect to image signals. 207 is (CD 220, 222, 224 is D-Flip 707 block 210
216 is a counter 217fi, a negative logic OR circuit 218, and a shift register 256 is a ROM. 4 tmi 4θ4 (J-Noratoin 1-J No.

Claims (1)

[Claims] A circuit that repeatedly inputs one page's worth of image data every line, a circuit that compresses the input image take, and a line synchronization signal synchronized with the input of each line of image data separate lines. a circuit that generates the code shown;
1. An image data compression device comprising: a circuit that generates a code indicating one page division based on a page synchronization signal synchronized with input of image data for one page.