JPS60258955A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent the decrease or inversion in logical level of accumulated informations by a method wherein a carrier trap region is provided in a substrate under the surface of the substrate where a bit line has been formed. CONSTITUTION:An N<+> type region 11 is epitaxially grown in the substrate 10, and a P type region 12 is formed thereon. Field SiO2 films 13 and an SiO2 gate insulation film 14 are formed by selective oxidation of the P type region 12. A fixed potential line 15 made of low-resistant poly Si is formed on the insulation film 14, and an interlayer insulation film 16 is formed by oxidizing the surface of the line; besides, a word line 17 made of low-resistant poly Si is formed on the film 14. A bit line 18 is formed by ion implantation by using the word line 17 as a mask. Since the N<+> type region 11 of high concentration which is reverse in conductivity type to an information charge accumulated region is provided thereunder so as to trap electrons generated by alpha ray irradiation by impressing a required potential +V on this region 11, the amount of electrons absorbed to a depletion layer DP markedly reduces. Thereby, the derease or inversion in logical level of accumulated informations is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, especially an insulating game device! The present invention relates to a semiconductor memory device such as a dynamic memory having a type of memory cell in which an information storage capacitor is formed in a portion corresponding to the drain or source of a field effect transistor.

In this type of memory that has been proposed in the past, electron-hole pairs are generated within the memory cell by alpha rays emitted from uranium (U) and thorium (Th) contained in the package, so the memory cell There is a problem in that the logic level of the information stored in the memory is lowered or reversed, or the level of the information readout gate is reversed when reading the information.

In order to solve these problems, a structure in which memory cells are provided in wells is disclosed in Japanese Utility Model Application Publication No. 55-54958.

An object of the present invention is to provide an improved semiconductor memory device that eliminates this type of disadvantage.

A semiconductor memory device according to an embodiment of the present invention includes a carrier trapping region in an information charge storage region and/or an information readout line (focus line) and/or an information amplification (sense amplifier) region to trap carriers generated by α-ray irradiation. The main feature is that it is captured, and an embodiment shown in the accompanying drawings will be described in detail below.

FIG. 1 is a circuit configuration diagram of an lMOS memory used in the present invention, in which a pair of bit lines B are connected to an insulated gate electrode (MOS) transistor Q3 whose gate electrode is connected to a word line W, and an information storage transistor Q3. A plurality of memory cells M consisting of a series circuit with a capacitor C are connected, and both bits are purely insulated gate type (MOS) transistors Q1. Q! A sense amplifier S consisting of the following is connected. FIG. 2 is a top pattern diagram of a semiconductor memory device consisting of a so-called semiconductor integrated circuit in which the circuit shown in FIG. 1 is incorporated into a single semiconductor substrate made of silicon or the like. In the drawing, the area indicated by a solid line is an area for forming an N-type semiconductor region within a P-type semiconductor region, and the area surrounded by a dotted line is an area for forming a sinusoid on the surface of a semiconductor substrate.
, etc., and an insulated gate type (MOS) element is formed at the intersection or overlapping portion with the solid line portion. Furthermore, regions 20 and 21 surrounded by dashed-dotted lines indicate metal wiring made of, for example, aluminum, and the bit lines 18 and MOS transistors Q, , Q, each made of an N-type region are shown in the shaded areas.
is connected to a gate electrode made of polycrystalline silicon. Note that the word line W (metallic wiring a such as aluminum) orthogonal to the bit line B is not shown in the figure for the sake of simplification. It is a cross-sectional view of , and shows the cross-section viewed from the ■-cabinet in Fig. 2. That is, FIG. 3 shows the structure of a memory cell portion according to an embodiment of the present invention, in which 10 is a semiconductor substrate made of P-type silicon, and 11 is a semiconductor substrate formed in this substrate 10 by epitaxial growth or ion implantation. N+
The type region 12 is a P type region formed on the N+ type region 11, and the field 840.13 is formed by selectively oxidizing the P subregion 12 to a depth of approximately 2 μm from the substrate surface. membrane, 14
is formed by lightly oxidizing the surface of the P-type region 120.
15 is a fixed potential line made of low resistance polysilicon formed on the gate insulating film 14;
6 is a Sin formed by oxidizing the surface of the fixed potential line 15;
17 is a gate electrode or word line made of low resistance polysilicon formed on the gate insulating film 14, and 18 is formed by self-alignment diffusion or ion implantation using the gate electrode 17 as a mask. N type source region or bit line.

In the above structure, the semiconductor surface region 12A directly under the gate electrode 17 of the P sub-region 12 acts as a channel region of the insulated gate field effect transistor, and the portion corresponding to the drain of this transistor is covered with the insulating film 14 and Together with the fixed potential line 15, it forms an information storage capacitor and acts as an information charge storage region. Accumulation of information charges in this capacitor section is controlled by the transistor.

By the way, when information of logic @lII' is stored in the memory cell having the above configuration, the depletion layer DP expands as shown in the figure. When alpha rays from the outside enter the memory cell in such a state, electron-hole pairs are generated, and the electrons are absorbed into the depletion layer DP, thereby changing the logic "I".
It acts to lower the store level of I'. Also, information@1”.

Regardless of ``0'', during information read and refresh operations, the charge on the bit line, which has been previously charged to a high potential and is in a floating state, and the charge accumulated in the memory cell cause charge distribution through the above transistor. As shown in FIG. 4, a bit line level is generated depending on the memory cell information.

Using the same mechanism, a reference level is set by a dummy cell on the bit line on the opposite side of the sense amplifier, and information is extracted by comparison and amplification with this level. In the conventional semiconductor device, the electrons due to αIK are absorbed by the bit line composed of N+ and its level is lowered by 'l'' and 10''.
However, according to the present invention as shown in FIG. 3, an N+ type region 11 of the opposite conductivity type and high impurity concentration is provided below the information charge storage region, and this N+ type region Since electrons generated by α-ray irradiation are captured in the N+ type region 11 by applying a predetermined potential V, the amount of electrons absorbed by the depletion layer Dr is significantly reduced. Therefore, a drop or inversion of the logic level of the stored information is prevented.

In the above embodiment, the N+ type region 11 was made to act as a carrier trapping region, but a region doped with recombination centers such as Au may also be used as the carrier trapping region. The advantage is that there is no need to connect an external potential source to the doped region.

Further, in the above embodiment, an example was explained in which a carrier trapping region was provided under the surface of the substrate where the memory cell M was formed, but the carrier trapping region was provided under the surface of the substrate where the memory cell M and/or the bit line B was formed and/or the sense amplifier S. The same effect as described above can be obtained by forming a similar carrier trapping region under the surface of the substrate provided with. The most desirable effect can be achieved by providing it in all three locations above, but especially,
Since the bit line B is commonly provided for a plurality of memory cell sections and extends over the surface of the semiconductor substrate, the bit line B occupies a large area.

Therefore, it is desirable to provide a carrier trapping region as described above in the substrate under this bit line.

In the various embodiments described above, the carrier trapping region 11 is formed of a thick field oxide layer 13, as shown in FIG.
The carrier trapping region is preferably spaced apart from the bottom of the substrate by at least 1 micron or more to prevent the generation of parasitic channels on the substrate surface at the bottom. It is better to form the Considering the penetration distance of α rays into the substrate, it is sufficient to provide the depth within about 25 microns or less.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device used in the present invention, FIG. 2 is a top pattern diagram of a semiconductor substrate when it is configured as a semiconductor integrated circuit, and FIG. 3 is a memory according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cell structure, and corresponds to the Cao-Lian cross section in FIG. 2. Further, FIG. 4 shows a signal level state diagram for explaining the present invention in detail. 10... Semiconductor substrate, 11... N+ for carrier capture
Type region, 12A... Channel region, 15... Fixed potential line, 17... Word line, 18... Bit line, 1
9... Depletion region, M... Memory cell, B
... B) line, W... word line, S... sense amplifier, QrmQ*, Qs... insulated gate transistor, C... information storage capacitor. (91-linI: /θ -296-

Claims (1)

[Claims] 1. A memory circuit is formed on a single semiconductor substrate, in which a plurality of series circuits of insulated gate field effect transistors and information storage capacitors are connected to a pair of bit lines, and a sense amplifier is connected to the bit lines. 1. A semiconductor memory device comprising: a carrier trapping region provided in the substrate at least below a surface portion of the substrate where a bit line is formed.