JPS60258587A - Symbol generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an improvement in a symbol generator used for the purpose of displaying figures on a display device such as a television. [Prior Art] FIG. FIG. 2 is a diagram for explaining a conventional device for generating a minute image.

In FIG. 1, (1) is a row position counter that specifies the row position of each pixel scanned on the screen, (2) is a column position counter that specifies the column position of each pixel scanned on the screen,
G11k': Upper end detector that detects the upper end of the minute.

(4) is a lower end detector that detects the lower end of the line segment, (5) is a column detector that detects the column position of the line segment, and (6) is an AND gate. Figure 2 shows the image of the line segment. In the diagram for explanation, 7) is the display image + (7a) is the pixel in the first row and first column of the display image (7), and (7b) is the pixel in the first row and last column of the display image 7). Pixel.

(7c) is the pixel in the second row and first column of image (7), (7d)
is a pixel at the upper end of the line segment + (7e) is a collection of images at the lower end of the line segment.

The operation of the conventional device will be explained below.

During the non-image display period, the row position counter (1) and column position counter (2) are initialized to point to the pixel (7a).

The first half detector (3) inputs the designated value of the upper row position of the line segment to be displayed, the lower end detector (4) inputs the designated value of the lower end row position of the sub-segment to be displayed, and the first column detector ( 5) inputs the designated value of the column position of the line segment to be displayed.

When the image display period begins, the column position counter (2) operates first and increases its value by 1 every display period for one pixel.

The output of the column position counter (2) is input to a column detector (5) and is compared with the line segment column position designation value.

The column detector (5) detects 1 when the specified value and the output of the column position counter (2) are equal. Otherwise, outputs 0.

When scanning to pixel (7b) in the first row is completed, the column position counter (2) is initialized and the 0th row position counter (1
) increases the value by 1.

Thereafter, the same operation as in the first row is repeated.

The output of the row position counter (11) is input to the top detector (3).

The upper end detector (3) outputs 0 when the output of the row position counter (11) is smaller than the designated value of the toe position by approximately 0. Otherwise, it outputs 1.

The output of the line position counter (1) is also input to the bottom end detector (41). Output.

The output of the upper end detector (3), the output of the lower end detector (4), and the output of the column detector (5) are ANDed. 2)
The output of refers to the column containing pixel (7d) and pixel (7e),
And when the output of the row position counter (1) points to the row from the row containing pixel (7d) to the row containing pixel (7e), 1. Otherwise, it is 0, so while the 0 row position counter (1) and column position counter (2) scan one screen, the AND gate (
A pure image can be obtained from the output of step 6).

As is clear from the above explanation, in the conventional circuit.

Only one line segment can be generated per circuit, and K, which represents multiple line segments, must prepare as many such circuits as the number of line segments to be displayed, and synthesize their outputs. There was a drawback.

[Summary of the invention]

This invention was made to eliminate the above-mentioned drawbacks of conventional devices, and provides a symbol generator that can display ↑ν line segments with one circuit. [Practical example of the invention] ] Hereinafter, one embodiment of the present invention will be described.

FIG. 3 is a diagram for explaining the development of an embodiment of this invention, and (8) is a memo with a memory location corresponding to each point of the image! J, (91 is the controller that controls i4L protrusion writing in the above memo January 8), and the output is from the row position counter (1) and column position counter (2) and the column position to the memo January 8). aD is a shift register that holds image data for one scanning line, α2 is a memo January 8
) and the output of the shift register 011 to 101, and αJ is an OR gate that calculates the OR of the shift register flD and the exclusive OR game H12.

In the following, to explain the operation of this embodiment, for convenience of explanation, the memory locations of the memo (January 8) will initially be explained as being outside the 0 state, and then the memory locations of the memory (8) will be changed to the 0 state. Explain how to do this.

During the non-image display period, the 0 row position counter (1) and the column position counter (2) are initialized to point to pixel (7a), the switch OI selects the external address input, and the shift register 01) is all in the 0 state. During this non-image display period set to , data specifying the upper end position of the line segment to be displayed and data specifying the lower end position of the line segment to be displayed are input from the external address input the number of times corresponding to the main line of the line segment to be displayed, Controller (
9) writes data 1 to the memo 81 every time an external address input occurs.

As a result, the storage locations in the memory (8) corresponding to the upper or lower end positions of the line segments to be displayed are in one state.

Anything else is set to 0 state.

During the image display period, the switch (11 row position counter (1)
.

and the output of the column position counter (2), and the 1-row position counter (1) and the column position counter (2) perform the same operations as in the conventional device.

Therefore, address data is inputted to the address input terminal of the memo (January 8) so that the memory locations are scanned by the rask scanning method every pixel display period.

During this time, the controller (9) reads the internal memory of the corresponding memory location during the display period of each pixel and writes data 0 to that memory location, thereby writing the data 0 to the memory location of the memory (8) that has been scanned. All data 0 is written to the data output terminal of the memo (January 8) when the memory location corresponding to the upper or lower end of the line segment to be displayed is scanned. At other times, a signal that is 0 is obtained.

The output terminal of the above memo January 8) is exclusive OR gate a2
is connected to the input terminal of the exclusive OR game H
2I/c, output of shift register OI) and memory 1
The output of the exclusive OR gate O2 is 0.0 when the two inputs are equal. Otherwise, it becomes 1.

The output of shift register Q11 is exclusive OR gate az
There is a delay of one scanning line with respect to the output of , and all the values are 0 in the first row of one image display period.

Hereinafter, for convenience of explanation, an example will be taken in which the line segments in FIG. Therefore, the output of exclusive OR gate O2 is also 0, and both the internal state and output of shift register αB are 0.
It is.

Subsequently, when pixel (7d) is scanned, the output of Memo January 8) is 1. Because the output of the shift register (111 is 0).

The output of exclusive OR gate az becomes 1, and 1 is input to shift register U.

After that, until just before the pixel in the same column as pixel (7d) in the next row of pixel (7d) is scanned, the output of memo January 8) and the output of shift register old) are both O, so exclusive logic The output of sum gate O2 is zero.

When the next pixel is scanned, the output of Memo January 81 is 0.
．． Since the output of shift register O11 is 1.

The output of the exclusive OR gate az becomes 1, and 1 is input to the shift register flit.

Thereafter, the above operation is repeated until just before the 0 pixel (7e) is scanned.

When pixel (7e) is scanned, the output of shift register 01) is 1. Since the output of the memo (January 8) also reaches 1, the output of the exclusive OR gate becomes 0, and the shift register (Ill
0 is input to .

Until the last pixel of image (7) is scanned, the output of fi2 is 0, so the exclusive logic phase game) +15 output is the pixel in the column containing pixel (7d). When the pixels from the row of pixel (7d) to the row of pixel (7e) are scanned, 1. Otherwise, it becomes 0, and the output of the shift register +Il+ is when the pixels from the row below the row of pixel (7d) in the column containing picture-i (7d) to the row of pixel (7e) are scanned. 1. At other times, it is 0.

The output of the shift register αD and the exclusive OR gate α
The output of 2 is input to the end sum gate α□□□.

The output of OR gate 0 is at least one of the two inputs.
When the direction is 1, 1. Otherwise, it will be 0, so 0 pixel (7d
) is scanned from pixel (7d) to pixel (7e) in the column containing 1. Otherwise, it is 0.

As is clear from this, the output of OR gate 0 is the same as the desired image signal, if we consider the same case when multiple subdivisions are specified.

The image signal containing all the specified line segments is processed by the OR gate (
It is clear that the signal is output from 13.

Officially, the method is to set all memory locations of Memo January 8) to 0 state, but since 0 is written to all memory locations of Memo January 8) during the image display period, 1 is written before displaying 0. It is sufficient to provide a dummy image display period corresponding to the number of screens. [Effects of the Invention] As is clear from the above explanation, according to the present invention, a circuit for displaying a line segment perpendicular to the scanning direction of Yanagi number on the same screen can be provided. It can be realized in a smaller size and at a lower cost than conventional ones.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional device, FIG. 2 is a diagram for explaining a line segment image, and FIG. 3 is a block diagram of an embodiment of the present invention. (2) is the column position counter, (31 is the upper end detector, (41 is the lower end detector, (5)
is a column detector, (6) is an AND game), (71 is an image. (7a) is a pixel in the first row and first column of image (7), (7b)
is the pixel in the first row and last column of image (7), and (7c) is the pixel in the first row and last column of image (7).
7), the pixel in the second row and first column, (7d) is the pixel at the top of the line segment, (7e) is the pixel at the bottom of the line segment, (8) is the memory lJ,
+91 is a controller, +IQ is a switch, αB is a shift register, 03 is an exclusive OR gate, and ai is an OR gate. Note that the same or corresponding parts in Figure 1 are indicated with the same reference numerals. . Agent Masuo Oiwa Figure 1

Claims (1)

[Claims] In a symbol generator that generates an image signal of a figure using a rask scanning method, a point on the line segment is determined to be a point other than a 1° line segment based on data specifying both ends of a line segment perpendicular to the scanning direction. A memory that has a memory location corresponding to each point on the screen to generate an image signal where the point is 0. Means for sequentially reading the memory and writing 0 in the read memory location during the image display period, and writing 1 in the memory using data specifying both end positions of a given line segment as an address during the non-image display period; a line memory that holds an image signal for one scanning line; a means for performing an exclusive OR operation on the outputs of the memory and the line memory and writing the result into the upper Hc'' line memory; an output of the line memory and the exclusive OR operation; 1. A symbol generator comprising means for performing a logical OR operation on the results of operations and outputting the results as an image signal.