JPS60254827A - D/a converting device - Google Patents

Abstract

PURPOSE:To regenerate a large amplitude value with a small number of bits by limiting the number of bits of digital waveform data and controlling a data input period according to an amplitude level. CONSTITUTION:The high-order two bits of data EV/AM inputted while its number of bits is limited are decoded by a decoder 298 and the remaining four bits are decoded by a decoder 300. Four output lines of the decoder 298 are connected to control inputs of gate elements GA1-GA4 of four gate element groups G1-G4 of an analog voltage generating circuit 302, and 16 output lines of the decoder 300 are connected to control inputs of 16 gate elements where voltage- division outputs of voltage dividing resistances are passed in the gate element groups G1-G4 of the circuit 302. Power lines PS1 and PS2 of the circuit 302 are supplied with a voltage VH from a power circuit 304 and an intermediate voltage VC according to a control input TG/SG. Further, a pulse width control circuit 306 controls the pulse width of the output voltage of the circuit 302 according to clock signals phi1 and phi2 and the voltage output of the circuit 306 is amplified by an amplifier 308 to output a voltage VOUT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a D/A conversion device, and particularly relates to an A/A conversion device suitable for processing digital waveform data related to sound in a sound generating device such as an electronic musical instrument. It is something.

[Summary of the Invention] This invention provides a large amplitude value with a small number of bits by limiting the number of bits of the digital waveform data and controlling the data input period according to the amplitude level when digital waveform data is D/A converted. is made reproducible.

[Prior Art] Conventionally, in digital electronic musical instruments, for example, digital waveform data representing a musical sound waveform is inputted to an A/A converter to obtain an analog musical sound signal. In this case, digital waveform data is input to the D/A converter in bit parallel format, but if you want to faithfully reproduce the waveform, it is normal to perform D/A conversion without cutting off the lower bits. Met.

[Problems to be Solved by the Invention] According to the above-mentioned prior art, if the number of digital waveform data is small, the configuration of the D/A converter becomes simple. However, when the number of bits of digital waveform data is large, the configuration of the D/A converter becomes complicated. Further, if the lower bits are truncated, the configuration of the D/A converter can be simplified, but there is a problem in that waveform reproducibility deteriorates.

[Means for Solving the Problems] The present invention has been made to solve the above problems, and includes limiting the number of bits of digital waveform data when digital waveform data is D/A converted. In addition, the data input period is controlled according to the amplitude level.

That is, the D/A converter according to the present invention includes an input means, a level detection means, a bit number limiting means, and a D/A converter.
/A converter is provided.

The input means is for sequentially inputting digital waveform data representing a desired waveform in a focused parallel format, and is constituted by, for example, a latch circuit.

The level detection means detects the amplitude level of the waveform based on the digital waveform data, and generates an output signal when the amplitude level reaches a predetermined level, and is, for example, a logic circuit that receives the upper bits of the digital waveform data as input. configured.

The bit number limiting means is for transmitting the input data with the number of bits n smaller than the number of bits m at the time of input each time digital waveform data is manually input, and when the level detection means does not generate an output signal, the input data is The data is sent from the least significant bit to the nth bit for a predetermined period of time, and when the level detection means generates an output signal, the input data is truncated (m-n) bits from the least significant bit, and the remaining n bits are sent for a predetermined period of time. The transmission period is 2 (m-n) times longer than the period of time. Such bit number limiting means is composed of, for example, a shifter circuit.

The D/A converter performs D/A conversion on n-bit digital waveform data sequentially sent out from the bit number limiting means and sends out an analog output signal.

In such a configuration, the digital waveform data inputted from the input means represents the envelope of the musical tone, and the D/A converter receives as a control input a sound source signal having a frequency corresponding to the pitch of the musical tone, and the D/A converter receives the sound source signal having a frequency corresponding to the pitch of the musical tone. A configuration may also be adopted in which a musical tone signal in which an envelope is applied to the signal is sent out as an analog output signal.

Further, the digital waveform data input from the input means represents the amplitude value of the sound waveform, and the D/A converter receives as a control input a sign bit signal representing the sign of the amplitude value of the sound waveform, and the D/A converter receives the sign bit signal representing the sign of the amplitude value of the sound waveform. A configuration may also be adopted in which a sound signal whose value is given a sign according to the sign bit signal is sent out as an analog output signal.

[Operation] According to the configuration of the present invention, when the digital waveform data is, for example, 8 bins) (m=8), the D/A converter is provided with, for example, 6 bins (y) (n) through the focus number limiting means. =6) data is supplied. Therefore, a 6-bit D/A converter suffices, which simplifies the configuration. Also, D
For example, if the upper 2 bits are 0'', the lower 6 bits are supplied to the /A converter for a predetermined period, and the most significant bit is 1.
” then the upper 6 bits are rounded off the lower 2 bits) (1
/4 data) or 22 times the predetermined period, so the output period of the D/A converter when the lower 1 bit is truncated is 4 times the output period when the lower bit is not truncated.
It will be doubled. Therefore, by acoustically exchanging the D/A converted output obtained in this way using a speaker or the like, it is possible to recover the amplitude decrease due to the bit number limitation.

In the configuration of the present invention, when the envelope data or the sound waveform data is D/A converted as described above, it is possible to generate high-quality sound that is almost the same as when the number of bits is not limited.

〔Example〕

FIG. 1 shows an electronic musical instrument according to an embodiment of the present invention, which has a total of 4,000 yen in manual piano mode, manual scale mode, auto piano mode, and auto scale mode. It is possible to perform the following actions selectively. Here, the general operations for each mode are as follows (1) to (4).

(1) Manual piano mode A piano sound having a pitch corresponding to the pressed key is generated based on a manual performance operation on the keyboard.

(2) Manual floor name mote #! Based on the manual playing operation on the keyboard, scale numbers such as "G", "Shi", "Mi", etc., having pitches corresponding to the pressed keys are generated.

(3) Autopiano mode Piano sounds are automatically generated by reading performance data from the performance data memory. In this case, the pitch of the piano sound is determined according to the pitch data included in the performance data. Furthermore, in the autopiano mode, a scale table can be generated in the same manner as in the manual scale mode described above, and manual scale performance can also be performed in conjunction with the autopiano performance.

(4) Auto scale name mode A scale scale is automatically generated by reading performance data from the performance data memory and reading audio data corresponding to the scale name from the audio data memory. In this case, the pitch of the scale name board is determined according to the pitch data included in the performance data. Furthermore, in the automatic scale mode, piano sounds can be generated in the same manner as in the manual piano mode described above, and manual piano performance can also be performed in conjunction with the automatic scale performance.

In FIG. 1, lO is a mode selection circuit, which includes a mode selection switch 12 and two OR gates 14 and 16. The mode selection switch 12 can be set to any one of manual piano mode MP, manual scale mode MD, auto piano mode AP, and auto scale mode AD. The OR gate 14 is configured to generate an output signal SL="1" when the mode selection switch 12 is set to the MD or AP position. The OR gate 16 also switches the mote selection switch 12 to A'P.
Or when set to AD position, output signal AUT, = “
1”°).

The timing signal generating circuit 18 generates various timing signals for controlling the generating operations of the piano trumpet and the scale stand, and the details thereof will be described later with reference to FIG. 2.

The keyboard circuit 20 includes, for example, a keyboard having 25 keys corresponding to notes F2 to F4, and presses keys by repeatedly scanning key switches corresponding to each key in a predetermined order. The pitch data KPC corresponding to the pitch data KPC is generated.

The keyboard circuit 20 is provided with a single note selection circuit, and when a plurality of keys are pressed at the same time, pitch data KPC corresponding to the one key having the slowest scanning order among the pressed keys is selectively transmitted. Ru. Each pitch data KPC represents the pitch for each key using 5 hits, with the most significant bit being an octave code and the remaining 4 bits being a note code.

It should be noted that each pitch data KPC continues to be transmitted during the period in which the corresponding key is pressed.

The performance data generation circuit 22 includes a performance data memory that stores performance data for, for example, 20 songs, and the performance data for which song is read from this performance data memory is determined by which key on the keyboard is pressed when the power is turned on. It is decided by

That is, when the power is turned on, the pitch data KPC from the keyboard circuit 20 is Fnei! When the pitch corresponding to the key other than the F4 key is indicated, the performance data of the 1st to 20th songs are sequentially read out from the performance data memory, and the pitch data KPC indicates the pitch corresponding to a specific key other than the F4 key. If so, the performance data of the specific song corresponding to the key pressed at this time is read out from the performance data memory. In other words, if you press the F4 key, all songs will be specified (all 20 songs will be read out sequentially), and the F4 key will be pressed.
If you press a desired key other than the 4th key, the specific song preset (20
(selective reading of a desired song among the songs).

Note that when specifying a specific song, which key is pressed to select which song is determined in advance.

Performance Data Reading Operation Here, the data reading operation from the performance data memory will be briefly described. When the song to be read is specified as described above, the tempo data of the specified song (the first song if all songs are specified) is read from the performance data memory, and then the tempo data of the first song of the chain section is read out. The pitch data and note length data of the note are read out.

Regarding performance data reading, the time division processing circuit 24 performs (A
I) Processing for counting reference clock signals for tempo setting to generate reference clock count data, (A2) Processing for counting tempo clock signals and generating tempo clock count data, and (A3) Note length end timing. The process of counting signals and generating address data for reading is executed in a time-division manner.

The performance data generation circuit 22 generates a tempo clock having a frequency corresponding to the tempo of a designated song based on the reference clock counting data sent as the data output DOA from the time division processing circuit 24 and the tempo data read from the performance data memory. Generate a signal. This tempo clock signal is supplied to the time division processing circuit 24 as an output signal PO,
It is counted. The performance data generation circuit 22 generates the note length of the first note based on the tempo clock count data sent as the data output DOA from the time division processing circuit 24 and the note length data of the first note read from the performance data memory. Detects the end timing of the note length and generates a note length end timing signal. This mark length end timing signal is supplied to the time division processing circuit 24 as an output signal Po, and the circuit 2
4 advances the read address by one. The read address data at this time is supplied to the performance data generation circuit 22 as the data output DOA, and in response, the pitch data and note length data of the second note are read from the performance data memory. Thereafter, pitch and note length data are read out for each note in the same manner. For rests, pitch data of all bits "o" and note length data corresponding to the note length are read out.

Through the performance data reading operation as described above, the performance data generation circuit 22 generates pitch data M for each note regarding the specified song.
PC is sent out. Each pitch data MPC uses 4 bits to represent the pitch of each note, with the most significant bit being an octave code and the remaining 3 bits being a note code.

Note that each pitch data MPC continues to be transmitted until the corresponding note length ends.

In the performance data generation circuit 22, reading of data from the performance data memory is prohibited unless any key is pressed on the keyboard when the power is turned on. Therefore, the keyboard operation when the power is turned on is auto piano mode AP.
Or, if you select the auto pronunciation mode AD, you only need to press a key to specify all songs or specify a specific song (selection), and if you select the manual piano mode MP or manual master-1'' MD Just don't press any keys.

Note that the performance data generation circuit 22 to the time division processing circuit 24
contains address data A regarding the subroutine processing described later.
DD is supplied, and at the same time, a readout completion signal SRE is also supplied from the time division processing circuit 24 to the performance data generation circuit 22 regarding audio data readout processing to be described later.

The piano sound generator selector 26 receives the pitch data MPC from the performance data generation circuit 22 and the pitch data KPC from the keyboard circuit 20 as human power A and B, respectively, and selects the pitch data from the output signal SL of the OR gate 14. If the signal SA is l"', the manual input A is selected, and if the selection signal SA is "0'', the input B is selected. Here, OR gate 1
The output signal SL (selection signal SA) of No. 4 becomes °°1 pa in the case of manual scale mode MD and auto piano mode AP, but as mentioned above, in the case of manual scale mode MD, the pitch Since the data MPC is not generated, the selector 26 selectively sends out the pitch data MPC only in the auto piano mode AP. It is also applied to the output signal of the OR gate 14. The decoder 28 is
12 note names of F, Fl...E and 13 corresponding to F4 note
It has a wooden output line, and the note code data N
T is encoded to detect the note name, and a signal "1" is sent to the output line corresponding to the note name.

The 13 output lines of the decoder 28 are connected to the frequency division control data memory 3 consisting of a ROM (read only memory).
0 and the memory 30 is connected to the input side of the decoder 28.
8-bit frequency division control data DVC is sent out in response to the output. Here, the frequency division control data DVC is exemplified with the right end as the most significant bit. For pitch name F, ro 1110110J, pitch name Fl
For the F4 sound, it is generated as ``rollolooooJ'' and ``rloxlloll'' for the F4 sound.

Of the pitch data KPC or MPC from the selector 26, the octave code signal (signal of the most significant bit) OCT is supplied to the time division output circuit 32 in order to control the variable frequency division operation when forming the sound source signal. Further, the OR gate 34, which receives the signal of each bit of the pitch data KPC or MPC from the selector 26, keeps the level "1" during the period when any bit is "1" for each pitch data. This signal PKO is supplied to the time division processing circuit 24 in order to determine the rise timing of the piano envelope.

The time division output circuit 32 selectively supplies the high speed clock signal φ11 and the low speed clock signal φF for envelope data formation to the time division processing circuit 24 according to the frequency switching signal FC from the time division processing circuit 24. It has become.

Here, the high speed clock signal φH is used to obtain a relatively steep decay curve, and the low speed clock signal φF is used to obtain a relatively gentle decay curve.

Regarding piano sound generation, the time division processing circuit 24 (B1)
(B2) A process of counting pulses and generating a frequency-divided output according to the frequency division control data DVC; and (B2) a process of counting the high-speed clock signal φH or the low-speed clock signal φ[ to generate envelope data representing a piano envelope. This is done in a time-divided manner.

The time division output circuit 32 outputs the frequency division output sent as data output DOB from the time division processing circuit 24 and selector 26.
A square wave sound source signal TG having a frequency corresponding to the pitch is generated for each pitch data based on the octave code signal OCT from the 8-bit envelope data sent out as data output DOB. Bit shift processing according to the amplitude level is performed to generate 6-bit envelope data EV. and.

The sound source signal TG and envelope data EV are supplied to a digital/analog (D/A) conversion circuit 36.

The D/A conversion circuit 36 adds a piano envelope to the sound source signal TG in accordance with the envelope data E2. This enveloped sound source signal is supplied to the speaker 40 via the output amplifier 38, so that the speaker 40 generates a piano sound.

The scale note generation section selector 42 receives the pitch data MPC from the performance data generation circuit 22 and the pitch data KPC from the keyboard circuit 2o as inputs A and B, respectively, and converts the output signal SL of the OR gate 14 into an inverter. In response to the selection signal SA inverted by the selector 44, a selection operation opposite to that of the selector 26 described above is performed. That is, the selection signal S
A is "1" in manual piano mode MP and auto scale mode AD, but as mentioned above, in manual piano mode MP, it is pitch 7-ta MP.
Since C is not generated, pitch data MPC is selectively transmitted from the selector 42 only in the automatic scale name mode AD. In addition, the selection signal SA is the manual scale mode MD.
and in the auto-piano mode AP, the value is "O°'. In these cases, when pitch data KPC is generated by key depression, the selector 42 selects and sends out the pitch data KPC.

Pitch data KPC or MP sent from selector 42
C is used for scale note generation, and according to the operation of the selector 42 described above, auto scale mode AD is selected.
, manual scale mode MD and auto piano mode A
In each case of P, scale note generation becomes possible.

The pitch data RPC from the selector 42 is supplied to the audio data generation circuit 46, and is used to select the audio data of the scale name corresponding to the pitch.

The audio data generation circuit 46 generates, for example, "Fa", "
Contains an audio data memory that stores audio data corresponding to the 15th floor name for two octaves of "n"..."do", "shi"..."do"..."fa". . In this embodiment, a digital speech synthesis system using a so-called adaptive delta modulation method is adopted, so the speech data memory stores the speech signal as one bit (“0”°) in time series for each scale note.
or 1'') is stored as audio data.In this case, the encoding involves sampling the audio signal at a constant cycle, calculating the predicted value for each sample point, and then calculating the predicted value. This method is known in itself and assigns a value of ``1'' or 0'' depending on the positive or negative sign of the difference between the value and the actual value.

Regarding scale tone generation, the time division processing circuit 24 performs (C1) counting clock signals to generate address data for reading audio data, and (C2) calculating amplitude changes based on data read from the audio data memory. (C3
) A process of calculating a predicted value of the amplitude based on the step width chi Z to generate predicted value data is executed in a time-sharing manner.

The OR gate 48 which receives the signal of each bit of the pitch data KPC or MPC from the selector 42 inputs the signal of each bit of the pitch data KPC or MPC.
A sound enable signal DKO having a level of ``1'' is generated. This sound generation enable signal DKO is transmitted to the performance data generation circuit 22.
It acts to release the reset of the address counter of the time division processing circuit 24 via. After this reset is released, the address counter counts the clock signal and generates address data, and in response to this, 1
The audio data on the fifth floor name is read out in parallel and in bit serial format for each note.

Then, from among the read audio data, audio data with a scale name corresponding to the pitch indicated by the pitch data at that time is selected.

Based on the audio data selected in this manner, the audio data generation circuit 46 outputs the signals necessary for the step width calculation and predicted value calculation as an output signal SO to the time division processing circuit 46.
Supply to 4.

Based on the output signal SO from the audio data generation circuit 46, the time division processing circuit 24 forms step width data for each sample point in a waveform on a specific scale (for example, "C" in a specific octave). , the predicted value data of each sample point 4θ is formed based on the output signal SO and the formed step width data for each sample point, and each predicted value data is sent out as data output DOB. Each predicted value data sent in this way is 9-bit two's complement coated data, the most significant bit of which is the sign (code).
It has become a hit.

The time-division output circuit 32 code-converts each predicted value data supplied as data output DOB from the time-division processing circuit 24 from a two's complement code to a sine magnitude code, and converts the code-converted data into an amplitude level. By performing corresponding hit shift processing, amplitude data AM and sign bit signal SG for each sample point are sent out.

Here, each amplitude data AM indicates the magnitude of the predicted amplitude value, and each sign bit signal indicates the sign (positive or negative) of the predicted amplitude value as "1'" or "°O''. It is something.

The D/A conversion circuit 36 reproduces a predicted signal by D/A converting the amplitude data AM and sign bit signal SG for each sample point supplied from the time division output circuit 32. This predicted signal, when viewed as an analog signal waveform, is
It shows a waveform that approximately corresponds to the change in the predicted value determined during encoding, and is supplied to the speaker 40 via the output amplifier 38, so that the speaker 40 generates scale tones.

In addition, in the above explanation, each piano note or scale name note is pronounced independently, but in the auto piano mode AP
Alternatively, in the case of the automatic scale name mode AD, the piano sound generation process and the scale name generation process are executed in a time-sharing manner, so that the piano sound and the scale note generation process can be simultaneously generated from the speaker 40.

Timing signal generation circuit FIG. 2 shows a detailed configuration of the timing signal generation circuit 18.

The frequency dividing circuit 50 has a frequency of 1.46 [gs] as shown in FIG.
The master clock signal φH having a cycle is divided to generate clock signals φ1 and φ2 having opposite phases to each other as shown in FIG.

Both clock signals φ1 and φ2 are 2.91 [μ, s
] It has a period of .

A frequency dividing circuit 52 divides the output signal of the frequency dividing circuit 50 to generate a high speed clock signal φ■ and a low speed clock signal φI for forming a piano envelope, and also generates a reference clock signal TCL for setting a tempo.

is generated. High speed clock signal φH is 0.4
71m5], and the low-speed clock signal φl has a period of 9.71m5].
32[Looking at the period of msl, the reference clock signal TCLo
8. , 64 [msl (7) period.

The shift register circuit 54 is reset by an initial clear signal IC generated in synchronization with power-on, and outputs the output signal "1°" of the NOR gate 56 corresponding to the outputs QO to Q7 at the time of reset to the OR gate 58. , and shifts it according to clock signals φ1 and φ2 to generate an output Qo −Q+
As shown in FIG. 3, a sequential timing signal To"r7 is generated as shown in FIG.
7 have a period of 23.3 [gs], and
Each timing pulse has a pulse width corresponding to one period of the clock signal φ1, and is used to control time division processing for eight channels in the time division processing circuit 24.

The OR gate 60 receives timing signals T1, T3, T5.
and T7 as inputs, and the timing signal T Co
occurs as shown in FIG.

Further, the OR gate 62 receives timing signals T2, T3,
T6 and T7 are input, and timing signal TC
, occurs as shown in FIG.

Further, the OR gate 64 outputs timing signals T4 to TI.
The timing signal TC2 is generated as shown in FIG.

The quaternary counter 66 counts the timing signal T7 after being reset by the initial clear signal IC. The NOR gate 68 outputs the output Q of the counter 66.
1 and the output of the inverter 70 that inverts the output Q2 of the counter 66, and the timing signal φ^
occurs as shown in FIG. Also, NOR gate 7
2 receives the outputs QI and Q2 of the counter 66 as inputs, and generates a timing signal φB as shown in FIG. Timing signals φc and φB are both 93.2
It has a period of [gs].

The OR gate 74 inputs the timing signal φ and φB and outputs the timing signal φΔ+φf as shown in FIG.
3 is generated. This timing signal φB is supplied to an AND gate 78 via an input/heater 76, and is ANDed with the timing signal T2. As a result, A
A timing signal T27 is generated from the ND gate 78 as shown in FIG.

Details of Performance Data Reading Operation In the performance data generation circuit 22, as shown in FIG. 4, a performance data memory 80 consisting of a ROM (read only memory) is provided.
Performance data for 20 songs is stored in the format shown in FIG. That is, as shown in FIG. 5(a), the start address data indicating the start address of song A (first song) is stored at address 0, and then songs B, C, D, etc. are stored in the address progression.・Performance data is stored. In addition, the performance data for each performance is shown in Figure 5 (
As shown in b), it includes a main routine section and a subroutine section each consisting of 7-bit data arranged in sequence, and the main routine section includes pitch and note length data for each beginning after the tempo data. In addition, 2-byte data related to the subroutine, that is, subroutine jump data and relative address data, are placed in the middle of the pitch note length data array, and the pitch and note length data at the beginning of each subroutine are placed in the subroutine section. The subroutine return data is arranged sequentially and at the end of the pitch-note length data array.

In the main routine section, after the pitch and note length data of the final note, song end data and start address data of the next song (in this case, song B) are sequentially arranged. Note that since the last song (the 20th song) is not the next song, stop data for stopping reading is placed at a position corresponding to the start address data of the next song.

Tempo data is used to set the tempo of a song.
The top 4 hits are the identification code (1110),
The remaining 3 bits represent the tempo value.

Each pitch/note length data represents the pitch and note length at the beginning of each note, with the top 4 bits and 2 points being the pitch code and the remaining 3 bits being the ml code. The most significant bit of the pitch code is an octave code, and the remaining three bits are a note code, and for rests, all bits of the pitch code are used as an octave code.

The subroutine jump data is for instructing a jump to the subroutine section, and the third four bits are an identification code (1100), and the remaining three bits are unused. The reason for providing the subroutine section is: - When playing the same part of a song repeatedly, storing the performance data corresponding to that part for the number of times will increase memory capacity, so the performance data of that part is stored in the subroutine section. The memory capacity can be reduced by storing the data in the subroutine section, jumping to the subroutine section as needed, playing, and when the performance is finished, returning to the original position (subroutine return) and playing. This is for the purpose of achieving this goal.

The relative address data is used to enable specification of the start address of the subroutine section, and indicates an address value that is determined relatively according to the address where the relative address data is stored. That is, the starting address of the subroutine section is set to address A3, and the storage address of relative address data is set to AR.
If it is a street address, the relative address data is (As -AR)
This shows the address value.

The song end data is just something that indicates the end of the song.
The upper 4 bits are the identification code (1111), and the remaining 3 bits are unused.

The start address data of the next song indicates the address where the first data (tempo data) of the performance data of the next song is stored.The top two bits are all 0''', and the remaining five bits are the start address. It is designed to represent an address value.

The subroutine return data is for instructing a return from the subroutine section to the main routine section, and the upper 4 bits are an identification code (1101:1. The remaining 3 bits are unused).

As mentioned above, regarding performance data reading, the time division processing circuit 24 executes the reference clock count data generation process (AI), the tempo clock count data generation process (A2), and the read address data generation process (A3) in a time division manner. That's right. Here, the processing timing and output timing in each process (A1) to (A3) are shown in Table 1 below for the above-mentioned timing signal To -T7.

Table 1 According to Table 1, it can be seen that the output timing is delayed by two pulses in a timing signal such as To -T7, that is, by two periods of the clock signal φ1, compared to the processing timing.

In the time division processing circuit 24, as shown in FIG.
A 12-bit full adder 82 and an 8-stage/12-bit shift register circuit 84 are provided for feeding back the outputs S1 to 312 of this full adder 82 as human power A1 to A12, respectively. circuit 84
has a configuration in which eight 1-stage/1-bit two-phase shift registers SF are connected in cascade, taking in input for each bit with a clock signal φ2 and sending out with a clock signal φ1. Number r written in the block of shift register SF
For example, when a timing signal such as TO in Fig. 3 is input, lJ is one pulse of one minute (clock signal φl
This means that an output signal such as T1 is obtained which is delayed (by one period of 1), and this applies by analogy to similar blocks numbered inside in FIG. 6 or FIG.

For example, a block marked with "6" is a 6-stage/l-bit shift register that provides a delay of 6 pulses.

As the output signals of the time division processing circuit 24, the outputs D1 to D12 of the second stage of the shift register circuit 84 are taken out. This corresponds to the fact that there is a pulse delay.

In the performance data read operation, the full adder 82 and the lower 6 bits of the shift register circuit 84 are used as an 8 stage/6 bit time division counter.

Assuming that the power is turned on by pressing the F4 key on the FI keyboard, in the circuit shown in FIG. 4, the latch circuit 86 latches the high tone data KPC from the keyboard circuit 20 in response to the initial clear signal IC.

This pitch data KPC indicates the pitch corresponding to the F4 key, and in response to this, the code detection circuit 88 generates the F11 key detection signal F4="1°°, and inputs the selector 90 to the input A.
Make it selected. At this time, the non-key pressed signal NK sent from the code detection circuit 88 is "0" because the key is pressed tomorrow, and this signal "0°" is transmitted through the inverter 92 as the chip enable signal CE='"1". The performance data is supplied to the performance data memory 80. Therefore, from the memory 80, 0
The address data, ie, the start address data of song A, is read out and supplied to the latch circuit 94 via the selector 90, where it is latched in response to the initial clear signal IC from the OR gate 96.

Then, when the timing of T1 and φ2 comes,...

Since the AND gate 98 generates an output signal "1pa," the latch circuit 100 latches the pitch data corresponding to the F4 key from the latch circuit 94, and the latch circuit 102 receives the pitch data shown in FIG. Address data D1-D6 from the time division counter is latched. All bits of this address data D1-D6 are "0". because,
In FIG. 4, when the R-S flip-flop 101 is reset by the initial clear signal IC, the sixth
This is because the full adder 82 shown in the figure is released from reset at the timing TI by the output signal "0" of the AND gate 103 shown in FIG. 4, and the TI channel of the time division counter has a count value of zero.

Latch data of latch circuit 100 and latch circuit 102
Since the latch data of ``3'' is supplied to the memory 80 as ``3rd place address data'' and ``lower address data'', the tempo data of song A is read from the memory 80.

This tempo data is supplied to the decoder 104, and in response, the decoder 104 outputs a tempo data detection signal TEM-
Generates “1°”. This detection signal TEM is supplied to an AND gate 106, which generates an output signal ``1'' at the timing To, and this output signal ``1''.
The latch circuit 108 latches the tempo data from the memory 80 in response to °'.

The tempo data detection signal TEM is supplied as the address advancement signal ADU to the AND gate 112 in FIG. 6 via the OR gate 110, and the AND gate 112 generates the output signal "1" at the timing of TI. This output signal “1°
° to full adder 82 via OR gates 114 and 116
Since the carry power C1 is supplied to the TI channel of the time division counter, the count value becomes 1. Address data D] to D6 indicating the count value 1 are sent out from the shift register circuit 84 at the timing of TI, and are sent out from the shift register circuit 84 at the timing of TI and
It is latched by the latch circuit 102 in FIG. 4 at the timing of φ2. Therefore, the pitch and note length data of the first note of the song A are read out from the memory 80.

Among the read takes at this time, the pitch data is from decoder 1.
04 and the latch circuit 118, and the symbol length data is supplied to the decoder 120. When the decoder 104 receives the pitch take, all of its five output signals become 0, and in response, the NOR case 122 generates the pitch data detection signal PC='1'.This detection signal PC is A
ND gate 124 and AND gate 124
The latch circuit 118 generates an output signal "l" at the timing of "o", and in response to this, the latch circuit 118 latches the pitch data from the memory 80. Therefore, from the latch circuit 118, the first
The pitch data of the note is sent out as pitch data MPC.

Also, the same T as the sending timing of this pitch data MPC.
Since the gate circuit 126 becomes conductive at timing o, the output of the decoder 120 that has decoded the note length data of the first note is supplied via the gate circuit 126 to a note length code memory 128 consisting of a ROM. This memory 128 encodes the output of the decoder 120 according to the note length type (for example, quarter note length) so that it can be compared with the count output of the time division counter shown in FIG. The code length code data from is supplied to a comparison circuit 132 via an OR circuit 130.

By the way, the tempo data previously latched by the latch circuit 108 is transferred to R via the gate circuit 136 which becomes conductive at a timing other than T6 in accordance with the output signal of the inverter 134.
The tempo code memory 13B consisting of OM is supplied.

This memory 138 converts the tempo value data consisting of the lower 3 bits of the tempo data so that it can be compared with the count output of the time division counter shown in FIG. 6, and the tempo code data from this memory 138 is OR circuit 13
0 to the comparison circuit 132.

In FIG. 6, AND gate 140 is T.

Reference clock signal TCL for tempo setting at the timing of
This reference clock signal TCL is supplied to the full adder 82 as a carry signal Ci via OR gates 114 and 116. Therefore, the To channel of the time division counter is the reference clock signal TCL.

The count value increases by 1 each time it is counted. Then, reference clock counting data D based on such counting operation]
~D6 is the comparison circuit 132 in FIG. 4 at each timing of T2.
and is compared with tempo code data from memory 138.

In the comparison circuit 132, when the reference clock count data and the tempo code data match, a match signal EQ is generated. This match signal EQ is sent to the shift register 142.
and 144 as the tempo clock signal TCL to the AND gate 146 in FIG.
From 46 onwards, the tempo clock signal TC is generated at the timing of T4.
L is sent.

Further, in FIG. 4, the tempo clock signal TCL sent from the shift register 114 is
8 to an AND gate 150. At this time, the AND gate 150 is supplied with an output signal "1°" from the OR gate 16 in FIG. Clock signal TCL
Send out. This tempo clock signal TCL is supplied to the full adder 82 of FIG. 6 as a reset signal R3T via an OR gate 152, thereby resetting it. Therefore, the To channel of the time division counter has all pits 0"
After that, as described above, the reference clock signal T
Count CLo.

As a result of the comparison and counting operations as described above, a tempo clock signal TCL having a frequency corresponding to the tempo value indicated by the tempo data of song A is sent out from the AND gate 146 in FIG. This tempo clock signal TCL is input to the full adder 82 via OR gates 114 and 116, so that the T4 channel of the time division counter increases the count value by 1 every time the tempo clock signal TCL is counted.
It increases gradually.

The tempo clock count data D1 to D6 based on such counting operation is sent to the comparator circuit 1 of FIG. 4 at every timing T6.
32 and is compared with the note length code data of the first note from the memory 128.

When the tempo clock count data and the 'j:fH code data match in code in such a comparison operation, a match signal EQ is generated. This coincidence signal EQ is passed through the shift register 142 to the note length end timing signal L.
A of FIG. 6 is supplied as an address increment signal ADU from this OR gate 110 as an
The signal is supplied to the ND gate 112.

The note length end timing signal LET at this time indicates the end timing of the note length of the first note, and is input to the full adder 82 from the AND gate 112 via the OR gates 114 and 116 at the timing of T I . Ru. Therefore, the count value of channel T7 of the time division counter increases by one. Address data D corresponding to this increase in count value
1 to D6 are shift register circuits 84 at the timing of T1.
, and is latched by the latch circuit 102 in FIG. 4 at timings T1 and φ2. Therefore, the pitch and note length data of the second note of the song A are read out from the memory 80.

Further, the mark length end timing signal LET from the shift register 142 is supplied to the AND gate 153 via the shift registers 144 and 148, and in response, the AND gate 153 generates an output signal "1" at the timing of T4. . This output signal "1" DEG is supplied as a reset signal R3T to the full adder 82 in FIG. 6 via the OR gate 152 to reset it. Therefore, all bits of the T4 channel of the time division counter become "o'",
Thereafter, as described above, the tempo clock signal TCL is counted with respect to the note length data of the second note.

Then, by repeating the same note length measurement and address increment operations as described above, pitch data MPC is sent out one after another from the latch circuit 118.

As the above pitch/note length data reading operation progresses, subroutine jump data is eventually read out from the memory 80 at timings Tl and φ2, and in response to this, the decoder 104 outputs the subroutine jump detection signal 5U.
Generates B-J='“1”. This detection signal 5UB-
J is latched by the latch circuit 154 at timing T6. Further, the detection signal SUBΦJ is supplied to the AND gate 112 in FIG. 6 via the OR gate 110, and this AN
The signal is input from the D gate 112 via the OR gates 114 and 116 to the full adder 82 at the timing of TI. Therefore, the count value of the TI channel of the time division counter is 1.
address data D1 to D6 corresponding to this increase in count value are sent out from the shift register circuit 84 at timing TI (7). This address data D1-D
6 indicates a storage address A of relative address data.

At this timing of TI, the latch signal SUB.J of the latch circuit 154 is latched by the latch circuit 156, while the latch signal SUB.J of the latch circuit 154 is latched to the launch circuit 158. Based on the output signal generated at the timing of φ2,
Address data indicating address AR is latched. Also,
At the same time, address data indicating the address AR is latched into the latch circuit 102 at timings T1 and φ2, and relative address data is read out from the memory 80 in response. This relative address data indicates an address (As-AR), where As is the starting address of the subroutine section.

Next, at the timing of TI, the AND gate 162
generates an output signal "l'" in response to the latch signal SUBJ of the latch circuit 156, and in response, the gate circuit 16
4 is conductive. Therefore, the relative address data read from the memory 80 is transmitted to the gate circuit 164 and the OR circuit 1.
66 and further via OR gate group 168 of FIG. 6 to full adder 82 as inputs B1-B6. At this time, the input AI −A6 of the full adder 82 is as follows:
Since address data indicating address AR is supplied,
As the output 31-s6 of the full adder 82, address data indicating the start address As of the subroutine section is obtained, and this address data is sent from the shift register circuit 84 at the timing T1 and sent to the latch circuit 102 in FIG. T1
and latched at the timing of φ2. As a result, the pitch Φ note length data of the subroutine section is sequentially read out from the memory 80 in the same manner as in the case of the main routine section described above.

After that, when the note length end timing of the last note of the subroutine section is reached, the subroutine return data is read out from the memory 80 at timings T1 and φ2, and in response to this, the decoder 104 outputs the subroutine return detection detection signal SUB -R- This detection signal 5UB
-R is supplied to the AND game) 170, and accordingly A
The ND gate 170 outputs the output signal °“l at the timing of TI.
” and makes the gate circuit 172 conductive. Therefore, the address data indicating the address AR latched in the latch circuit 158 is transferred to the gate circuit 172 and the OR circuit 1.
66 and further via OR gate group 168 of FIG. 6 to full adder 82 as inputs B1-B6. At this time, the detection signal SUBφR makes the output signal of the NOR gate 174 "O" and the ANDNO gate 174 outputs each AND.
Since the gate is rendered non-conductive, the input A of the full adder 82
1 to AI2 are all "0".

Further, the detection signal 5UB-R is output from the OR gate 110 in FIG.
is supplied to the AND gate 112 in FIG.
The output signal "1" is generated at the same TI timing as 0. This output signal "l" is an OR game) 114 and 11
6 to the full adder 82 as a carry input C4, the output Sl -36 of the full adder 82 is an address indicating the (AR+1) address (that is, the address next to the storage address of the relative address data). Data is obtained.

This address data is sent out from the shift register circuit 84 at timing T1, and latched by the latch circuit 102 in FIG. 4 at timing TI and φ2. As a result,
The pitch/note length data next to the relative address data of the main routine part is read out from the memory 80, and thereafter, the pitch/note length data reading operation is performed in the same manner as before the subroutine jump.

Thereafter, at the end of the note length of the final note in the main routine section, the song end data is read out from the memory 80, and in response to this, the decoder 104 outputs the song end detection signal E.
Generates ND="1".

Since this detection signal END is supplied to the AND gate 112 in FIG. 6 via the OR gate 110, the count value of the channel T7 of the time division counter increases by one. Then, based on the address data corresponding to this increase in count value, the next song B is sent from the memory 80 at timings T1 and φ2.
The first address data of is read out.

Furthermore, the detection signals EN and D are supplied to the delay (D) circuit 178.
supplied to This delay circuit 178 takes in the input at timing T6 and sends it out at timing T1.
It consists of a phase shift register, and its output signal is AN
The signal is supplied to the D gate 180 and is ANDed with the F4 key detection signal F4 and the timing signal T6. Therefore, at the next T6 time, the AND gate 180 generates the output signal LT="l"'.

This output signal LT is supplied to the latch circuit 94 via the OR gate 96, and in response, the latch circuit 94 latches the start address data of the next song B supplied from the memory 80 via the selector 90.

Output signal LT is also provided to AND gate 182;
In response, the AND gate 182 generates an output signal "°1" at the timing T7. This output signal "1" resets the full adder 82 in FIG. 6 via the OR gate 152, so that The count value of channel T7 of the time division counter becomes zero.

The address data corresponding to this count value of zero is 'T +
is sent from the shift register circuit 84 at the timing of
At the timing of T1 and φ2, the AND gate 98 in FIG.
The output signal "1" of the AND gate 98 is latched by the latch circuit 102.The output signal "1" of the AND gate 98 at this time is supplied to the latch circuit 100, and the latch circuit latches the start address data of the next song B from the latch circuit 94. For this reason, the memory 80
From there, the tempo data of the next song B is read out, and thereafter, the same performance data reading operation as in the case of the song A described above is performed for the song B.

Then, the performance data reading operation similar to that described above is performed for song C,
D... is performed sequentially, and eventually the memory 8
The stop data at the end of the final song is read from 0, and in response to this, the decoder 104 outputs a stop detection signal 5TP=
This detection signal STP is supplied to a delay circuit 186 similar to the delay circuit 178 described above through an OR gate 184. Therefore, the flip floral 7'lO1 It is set at the timing of T1, and in response to the output Q='''1'', the AND gate 103 generates the output signal "1" at the timing of T7.
do. This output signal .degree. "l" resets the full adder 82 of FIG. 6 through the OR gate 152, so that the T7 channel of the time division counter becomes a count value of zero and remains in this state thereafter. Therefore, reading data from memory 80 is stopped.

What has been described above is the performance data reading operation in the case of a complete performance, but the performance data reading operation in the case of a single picture selective performance is as follows.

In this case, a key other than the Fa key corresponding to the desired song is pressed on the keyboard. Then, in the circuit shown in FIG. 4, pitch data KPC corresponding to the pressed key is generated in accordance with the initial clear signal IC.
is latched by the latch circuit 86. This pitch data KP
Since C indicates the pitch corresponding to keys other than the F4 key, the F4 key detection signal F4 of the chord detection circuit 88 is "'0".
゛°, and the selector 90 is in a state of selecting input B. Therefore, the pitch data KPC from the latch circuit 86
is supplied to a latch circuit 94 via a selector 90 and latched therein in response to an initial clear signal IC from an OR gate 96. Further, since the key-not-pressed signal NK from the code detection circuit 88 is . . . o, the chip enable signal CE of the memory 8o becomes “1pa”.

Then, at the timing of TI and φ2, the latch circuit lOO
The pitch data corresponding to the selected song is latched from the latch circuit 94, and the atre stator of all pitches "O" from the time division counter shown in FIG. 6 is latched into the latch circuit 102. For this reason, the tempo data of the performance data of the selected song is first read out from the memory 80, and then the pitch, note length data, etc. for each note are read out in the same manner as in the case of song A described above.

As this read operation progresses, eventually the memory 8
Song end data is read from 0, and in response, the decoder 104 generates a song end detection signal END-'"1".In response to the generation of this detection signal END, the memory 8
As described above, the start address data of the next song is read from 0, but since the selector 90 is in the input B selection state, this start address data is not supplied to the latch circuit 94. The latch circuit 94 also receives the F4 key detection signal F4.
Since the AND gate 180 is non-conductive due to =°“0”, there is no latch operation.

Detection signal END is supplied to AND gate 188 and F
It is ANDed with the output of the inverter 190 which inputs the 4-key detection signal F4. At this time, since the F4 key detection signal F4 is O'', the AND gate 188 outputs the output signal "1".
', and this output signal "1" is supplied to the delay circuit 186 via the OR gate 184. Therefore, in the same way as in the case of reading the stop data described above, the time division counter Tl of FIG. The channel is placed in a reset state and further reading of data from memory 80 is stopped.

Note that if no key is pressed on the keyboard when the power is turned on, a no-key-pressed signal NK is sent from the code detection circuit 88.
Since the value becomes "°1"', the chip enable signal CE becomes "0'°, and data reading from the memory 80 is prohibited.

Details of piano sound generation operation Regarding piano sound generation, the time division processing circuit 24 performs frequency division output generation processing (Bl) and envelope data generation processing (B2).
) is executed in a time-sharing manner as described above. Here, the processing timing and output timing in each process (B1) and (B2) are determined by the above-mentioned timing signal To.
-Tl is shown in Table 2 below.

According to Table 2, it can be seen that the delay in output timing with respect to processing timing is the same as in Table 1.

In FIG. 6, a full adder 82 and a shift register circuit 8
4, at the timing of T5, the part from the least significant bit to the 7th bit is used as a 7-bit counter to send out the divided output Do, and at the timing of T6, the part from the least significant bit to the 9th bit is used as a 7-bit counter. It is used as a bit counter and sends out 8-bit envelope data D2 to D9.

In the frequency division output generation process, the AND gate 192 has
The 9th least significant bit signal of the frequency division control data DVC is input from the frequency division control data memory 30 in FIG.
At timing 5, the signal is input to the shift register SF via the OR gate of the least significant bit in the OR gate group 194. Further, the ANDNO gate 198 receives the outputs 31, 32, . . . The signals from the 2nd bit to the 7th bit of the cycle control data DVC are respectively input, and the output signal of each AND gate is input to the NOR gate 1.
98.

The latch circuit 200 outputs AN at timing T5 and φ2.
It latches the output signal of the NOR gate 198 in response to the output signal “1°” of the D gate 202, and when the output signal of the NOR gate 198 is “1”, it sends out the latched signal “1°”. It looks like this. This signal “°
1''' is supplied as a carry input Ci to the full adder 82 via the AND gate 204 and further via the OR gate 116 at the timing of T5.Therefore, it is difficult to determine whether a pulse should be input to the full adder 82 or not. is the NOR game) 198 output signal ``l''' or ``0'' at each timing of T5.
controlled accordingly.

As a result of the above configuration, the counting operation of the T5 channel of the 7-bit counter is controlled according to the frequency division control data DVC, and from the 5th to 7th bits of the counter, the desired note name (for example, F) is input. Corresponding frequency-divided signals D5, Db and D7 are obtained. These frequency-divided signals D5 to D7 have frequencies 1/2 lower in Db than D5 and 1/2 lower in frequency than D7, respectively, and are supplied to the time-division output circuit 32 in FIG. 7 as a frequency-divided output DO. Note that when the frequency-divided output Do is viewed as count data at timing T5, this count data is supplied from the shift register circuit 84 to the circuit shown in FIG. 7 at timing T7.

In FIG. 7, the frequency-divided signals D5 and Db
6 as human power A and B, respectively, and the divided signal D
6 and D7 are provided to selector 208 as inputs A and B respectively. The selection operation of selectors 206 and 208 is performed using octave code signal OCT and timing signal T.
It is controlled in accordance with a selection signal SA consisting of an output signal of an AND gate 210 which receives 7 as an input.

When the octave code signal OCT is “0” (F2
- When the octave to which the F2 note belongs), the selection signal SA is 0"', so the selector 206 selects the divided signal D6 as
The selector 208 selectively sends out the divided signals DI. The AND gate 212 generates an output signal "1" every time the outputs of the selectors 206 and 208 both become "1", and this output signal "1" is sent to the shift register 214 similar to SF in FIG. is transmitted at the timing of To. In this case, - as an example, the frequency-divided signal D with respect to the note name F
5 to D7 are generated, shift register 2
14, a square wave sound source signal TG having a frequency corresponding to the F2 sound is obtained.

Also, when the octave code signal OCT is 1゛ (
In the octave to which notes F3 to E3 belong, and in the case of note F4), the selection signal SA changes °゛1' at every timing of T7.
Therefore, the selector 206 selectively transmits the frequency-divided signal D5, and the selector 208 selectively transmits the frequency-divided signal D6. AN
The D gate 212 generates an output signal ``1'' every time the outputs of the selectors 206 and 208 both become ``l'', and this output signal ``1'' is sent to the shift register 214.
is transmitted at the timing of To. In this case, assuming that frequency-divided signals D5 to D7 are generated for pitch name F as in the previous example, F3 is output from shift register 214.
A square wave sound source signal TG having a frequency corresponding to the sound is obtained. Note that for the F4 note, the value of the frequency division control data DVC is determined so that the frequency of the frequency division signal D5 is twice that of note name F, so the octave code signal O
When CT is "°1'", a sound source signal TG having a frequency corresponding to the F4 sound is obtained.

In the envelope data generation process, in the circuit shown in FIG. 6, the ANI) gate 216 generates the output signal 1P at the timing To in response to the initial clear signal IC.

This output signal "1" is passed through the OR gate group 194 to 9
All bits “1°’” of To channel of hit counter
Make it. This is because when the power is turned on, the amplitude level of the piano envelope is set to zero to prohibit piano sound.

Thereafter, when a sound generation enabling signal PKO for generating a piano sound is generated, this signal PKO is differentiated by the differentiation circuit 218. In response to the differential output of the differential circuit 218, the AND gate 220 generates an output signal "1" at the timing To. This output signal ``1''' is O
It is input to the 9th bit shift register of the first stage of the shift register circuit 84 via the 9th bit OR gate in the R gate group 194, while the NOR gate 174
The output signal of the ANDNO gate 174 is set to 0 and each A
By making the ND gate non-conductive, all bits of the inputs A1 to A9 of the full adder 82 are set to "0'°."

As a result, when the sound generation enable signal PKO rises, the 9th bit of the To channel of the 9-bit counter becomes "L", and all bits from the least significant bit to the 8th bit become OPEN. 8-bit data from the 2nd bit to the 9th bit roo000001J
are supplied to the circuit of FIG. 7 as envelope data D2 to D9 via the shift register circuit 84 at the timing of TO.

When the next To timing comes, the shift register circuit 8
An output signal "o" is sent out from the 8th bit shift register of the 8th stage of 4, and this output signal "0" is supplied to the selector 222 in FIG. 7 as a frequency switching signal FC.

In the fItJZ diagram, the latch circuit 224 receives the timing signal To from the OR gate 226 and the clock signal φ.
The envelope data D2~ at the timing of To and φ2 according to the output signal of the AND gate 228 which inputs
D9 and sound source signal TG (output of shift register 214)
-, which latches the sound enable signal PKO mentioned above.
At the time of startup, only the most significant bit (corresponding to D9) is sent out as 8-bit envelope data. generates an output signal “1”, and this output signal “1” is T2
is latched by the latch circuit 232 at the timing of AND
A gate 234 is provided. Therefore, AND gate 2
34 is an output signal "1" at the timing of To and φ^
This output signal "1°" is supplied to the selector 222 as the enable signal EN.

When the selector 222 is enabled in response to the enable signal EN, it selectively sends out the high-speed clock signal φH as input B in response to the selection signal SA=“O” consisting of the frequency switching signal FC, and this high-speed clock signal φH 6th
Full adder 82 via OR gates 114 and 116 in the figure.
is supplied as carry human power C1. Therefore, the To channel of the 9-bit counter receives the high-speed clock signal φ
The count value increases at a relatively high speed in accordance with H.

As the count value continues to increase in this way, an output signal "i" is eventually sent from the 8th bit of the shift register in the 8th stage of the shift register circuit 84.

This output signal "1°" is supplied to the selector 222 in FIG. 7 as the frequency switching signal FC.

Therefore, the selection signal SA becomes "1" in the selector 222, and the low-speed clock signal φL as the input A is selectively sent out. Therefore, the To channel of the 9-bit counter is
Thereafter, the count value increases at a relatively slow speed in response to the low-speed clock signal φL. And 2 of the 9 bit counter
When all bits up to the 7th bit become "1", all eight input bits of the NAND gate 230 in FIG. 7 become "1", so the NAND gate 230
generates an output signal "o", and in response to this, the cell/actor 222 is disabled at timings To and φ^ after T2. Therefore, T of the 9-bit counter
Count increase in the o channel is prevented.

The individual count data corresponding to the above-mentioned changes in the count value of the 9-bit counter are supplied as envelope data D2 to D9 to the inverting circuit 236 via the latch circuit 224, and each bit is inverted by an exclusive OR gate. undergo processing. This inversion process is performed by the latch circuit 22
The numerical change in envelope data from 4 is rooooo
o.

l'' to rl 1111111J, from rllllllllOJ to roooooo.

00'', which corresponds to changing the piano envelope from an inverted shape to an upright shape.

In the inverting circuit 236, a signal TC2 obtained by inverting the timing signal TC2 by an inverter 238 is applied to the OR gate 24.
Inversion processing is performed in response to being supplied from 0. That is, the timing signal TC2 is output from the inverting circuit 236.
T is O゛.

The envelope data that has undergone the inversion process is sent out during the period from ~T3.

In this way, the envelopes are sent out sequentially.
The data is a piano envelope that rises from the zero level to a predetermined attack level, then falls to a predetermined value according to a relatively steep decay curve, and then further decreases to the zero level according to a relatively gentle decay curve. It becomes something that expresses. Here, the zero level corresponds to the state in which all 7 of the output K]~ of the inverting circuit 236 are -oll (all D2 to D8 are 1), and the predetermined attack level corresponds to the state that the output of the inverting circuit 236 is 1.
All 7s in ~ are “1” (all D2 to D8 are “0°”)
The predetermined value corresponds to the state of 1 to + at the output of the inverting circuit.
Among them, only 7 corresponds to the state of 0'' (only D8 of D2 to D8 is ``1''). Also, the relatively steep decay curve is expressed by the count data of the high speed clock signal φH, The relatively gentle decay curve is expressed by the count data of the low-speed clock signal 2φ.

The AND gate 242 receives the output signal of the NAND gate 230, the tone source signal TG, and the output signal TC of the inverter 238.
2, and the timing signal TC2 is '0' during the envelope data formation process.
The sound source signal -TG is transmitted during period 3. This sound source signal TG is passed through an OR gate 244 to an AND gate 246.
supplied to

The shifter circuit 248 performs bit shift processing in accordance with control inputs A, B, and C in order to enable D/A conversion processing, which will be described later, with a small number of bits.
1″, sends 3 to 8 to the output of the inversion circuit 236,
If the control input B is 1', 2 to 7 are sent to the output of the inverting circuit 236, and if the control input C is 1'', the inverting circuit 23
6 is sent to the output of 1 to 6. During the piano sound generation process, as mentioned above, the signal D9 is always "1", so the output of the inverting circuit 236 is always "o", and the control human power A, which also has the output "8", is "0".
''. Therefore, the shifter circuit 248 is operated by the control human power B.
and shift processing corresponding to C is performed.

In the circuit for forming control power B, the AND gate 288 inverts the output of the inverter 290 which inverts 8 to the output of the inverting circuit 236, and the output of the inverting circuit 236 to inverts 7.
It receives the timing signal TCo as input, detects that the second most significant pitch) K7 is "i" (the amplitude level is relatively high), and outputs the timing signal TCo twice during the To-T3 period. The output signal “1”° is generated at the timing of . These output signals "l" are supplied to the shifter circuit 248 as control input B, and in response to this, the shifter circuit 248 converts the 6-bit data 2 to 7 into 2 as envelope data EV during the period To=T3. Send twice.

Furthermore, in the circuit for forming the control input C, AN
The D gate 292 receives the output of the inverter 290, the output of the inverter 294 that inverts 7, and the timing signals TCo and TCI. (the amplitude level is relatively low) and generates an output signal "1" at the timing of T3 during the period of To-73.This output signal "1'
' is supplied to the shifter circuit 248 as control human power C,
In response, the shifter circuit 248 sends out 6-bit data 1 to 6 once as envelope data EV during the period To-T3.

OR gate 296 connects 8 and A to the output of inverting circuit 236.
The output of the ND gate 288 and the output of the AND gate 1292 are input, and during the period from To to T3,
When K , =I゛1'' is detected, output signal “1'' is generated twice at timing T1 and T3, and K7
When ="0Pa" is detected, an output signal "1Pa" is generated at the timing of T3. In this way, OR gate 296
The output signal “l゛° generated from the AND gate 246
conducts, so the sound source signal T from the OR gate 244
G is sent out from the AND gate 246 twice or once during the period of ``ro-T3'' in synchronization with the aforementioned envelope data sending.

The sound source signal TG from the AND gate 246 and the envelope data EV from the shifter circuit 248 are converted to D/D in FIG.
The signal is supplied to the A conversion circuit 36.

The D/A conversion circuit 36 includes a first decoder 298 that decodes the upper 2 bits of 6-bit input data (EV or AM), and a second decoder 300 that decodes the remaining 4 bits of the input data. , these decoders 298
and 300 constitute a D/A converter, a power supply circuit 304 that supplies a power supply voltage according to a control input (TG or SG) to this analog voltage generation circuit 302, and an analog voltage generation circuit 302. A pulse width regulation circuit 306 that regulates the pulse width of the output voltage according to clock signals φ1 and φ2, and a buffer amplifier 308 that derives the voltage output VOυ■ from the pulse width regulation circuit 306 are provided.

Of the 6-bit envelope data EV, the upper 2-bit signal including the most significant bit (MSB) is sent to the decoder 29.
The remaining 4-bit signal is input to the decoder 300. The four output lines of the decoder 298 are respectively connected to control input terminals of four gate elements GA+ to GA4 in the analog voltage generation circuit 302.

In the analog voltage generation circuit 302, four gate element groups 01 to G4 each including 16 gate elements are provided, and the 16 output lines of the decoder 300 correspond to the 16 gate elements for each gate element group. Connected to the control input of the element.

The analog voltage generation circuit 302 has first and second power supply lines PSz and PS2, and 64 resistors R having approximately the same resistance value are connected between these power supply lines.
1-R64 are connected in series. The 16 gate elements of the gate element group G1 are connected between one end of each of the resistors R1 to R16 and the gate element G A l , and the 16 gate elements of the gate element group G
The 16 gate elements of the gate element group G3 are connected between one end of each of the resistors R17 to R32 and the gate element GA2, and the 16 gate elements of the gate element group G3 are connected to one end of each of the resistors R33 to R48 and the gate element GA3. The 16 gate elements of gate element group G4 are connected between resistors R49 to R64.
and gate element GA4, and gate elements GA+ to GAa are configured to send an analog voltage to output point M according to input data.

In the power supply circuit 304, the voltage source +■ and the reference potential point (
A resistor RO and resistors RA and RB having substantially equal resistance values are connected in series between the resistor R
An intermediate voltage VC taken out from the interconnection point of ^ and RB is supplied to the power supply line PSI. A gate element GH is connected between the interconnection point of the resistors R8 and R^ and the power supply line PS2, and a gate element G is connected between the reference potential point and the power supply line PS2. The control input terminal of the element G1 is supplied with the tone source signal TG or the sign bit signal SG, and the control input terminal of the gate element G is supplied with the tone source signal TG or the sign bit signal SG via the inverter IV. ing. Therefore, a voltage vL lower than the intermediate voltage VC is supplied to the power supply line PS2 via the gate element G if the control input (TG or SG) is 1'', and a voltage vL lower than the intermediate voltage VC is supplied to the power supply line PS2 if the control input (TG or SG) is 1''. Intermediate voltage Vc through June
A higher voltage V■ is supplied. By switching the supply voltage to the power supply line PS2 to VL or VH in this way, it becomes possible to add an envelope according to the envelope data to the sound source signal TG during D/A conversion of the envelope data EV, which will be described later. amplitude data AM
During D/A conversion, it is possible to determine the direction of amplitude according to the sign bit signal SG.

The pulse width regulation circuit 306 includes gate elements Gll and GI2 that receive clock signals φ1 and φ2 at their control inputs, respectively.
These gate elements G11 and G12 are connected to the output point M of the analog voltage generation circuit 302 and the power supply circuit 30.
The interconnection point N of the gate elements Gll and G12 is connected in series with the interconnection point N of the resistors RA and RB of 4.
Voltage output V OUT via buffer amplifier 308
is now being taken out. At the output point M, “ro”
There is a possibility that an analog voltage (a voltage that swings from Vc to VH side or Vt side) is generated every period corresponding to one pulse of a timing signal such as -77, but in the pulse width regulation circuit 306, At the same time, the analog voltage of the output point M is sent out at the timing, and at the timing of φ2, the intermediate voltage V is sent out.
By sending out signal c, the width of the output pulse is limited to half that at output point M.

The reason why such a pulse width regulation circuit 306 is provided is that the 8-bit input data Kl-
The data of 6 people (EV/
This is due to the fact that the D/A conversion is performed after the D/A conversion is performed. That is, in FIG. 7, when 6 bits of data are extracted via the shifter circuit 248, data 2 to 7 is only 1 bit, whereas data 2 to 7 is 6 bits.
Since data 3 to 8 are shifted downward by 2 bits, the data 2 to 7 is l
/2, and the value of 3 to 8 in the data becomes 1/4. Therefore, in the D/A conversion circuit shown in Fig. 8, the data is
For , the data is tripled so that the amplitude level is doubled.
For ~8, D/A so that the amplitude level is quadrupled
In order to make this possible, the circuit shown in Figure 7 generates the same data twice for data 2 to 7, and four times for data 3 to 8. The pulse width regulation circuit 306 in Fig. 8 sends out the same analog voltage as two pulses in response to the same data twice, and sends out the same analog voltage as four pulses in response to the same data four times. This is what I did.

When such a /A conversion operation is illustrated for piano sound generation, it is as shown in FIGS. 9(1) to 9(d). Figure 9(a)
1 shows the sound source signal TG as a continuous waveform for convenience, and FIG. 2B shows the sound source signal to which a piano envelope has been added as a continuous waveform for convenience. In addition, (C) in the same figure is a macroscopic view of the signal in (b), and (d) in the same figure is a microscopic view of a part of the signal in (C), which shows the actual pulse. This corresponds to the signal waveform obtained from the output point N of the width regulation circuit 306.

At the rise of the piano envelope, an analog voltage corresponding to the attack level appears at the output point M, but as shown in FIGS. 9(1) and (b), this analog voltage If the sound source signal TG is 0''', the voltage is swung toward the VH side. Looking at this at the output point N, as shown in Figure 9(d), any voltage that swings to the VL side or the VH side is To
-It is sent out as two pulses at timings T1 and T3 during period T3. Then, when the amplitude level of the piano envelope falls below the level at which the above-mentioned second highest pitch K7 becomes 0'', only one pulse is sent out during the period To-T3 at the timing T3.

” As a result of the above, the voltage output V from the buffer amplifier 308 is
As OUT, a sound source signal with a piano envelope added as shown in FIGS. 9(b) to (d) is obtained, and this sound source signal is sent to the output amplifier 3 with or without a low-pass filter.
8 and is supplied to the speaker 40, where it is produced as a piano sound. In this case, time division processing and clock signal φ1,
The high frequency component based on φ2 is passed through a low pass filter or speaker 4.
It is substantially the piano sound signal as shown in FIG. 9(b) that is removed by the speaker 4o and produced as a piano sound by the speaker 4o. This piano sound signal has a relatively high attack level and a relatively high amplitude level in the vicinity thereof.
Since two pulses are included in the period T3, the energy is doubled and the sound intensity is also doubled compared to the case of one pulse. Therefore, the amplitude drop caused by bit shifting is recovered.

Details of scale note generation operation Regarding scale note generation, the time division processing circuit 24 performs address data generation processing (CI), step width data formation processing (c2
) and the predicted value data generation process (C3) are executed in a time-sharing manner as described above. Here, each process (cl
The processing timing and output timing in ) to (c3) are shown in Table 3 below for the above-mentioned timing signal To-T7.

According to Table 3, it can be seen that the delay in output timing with respect to processing timing is the same as in Table 1. Note that the step width data formed in process C2 is
It is subjected to predicted value data generation processing C3 at timing T2, and is not output from the time division processing circuit 24.

In FIG. 6, full adder 82 and shift register circuit 84 are used as a 12-bit address counter at timing T3 to send out address data D1 to DI2 for reading audio data. Further, the full adder 82 is
Timings T1 and T2 are used to perform addition or subtraction processing.

In FIG. 4, a differentiating circuit 310 differentiates the sound generation enable signal DKO for generating scale notes at the rising edge and generates a differential output. This differential output is the R-S flip float 7'3
12, the output Q of the flip-flop 312 becomes 0''.

This output Q is supplied to an AND gate 316 via a shift register 314.

Since the AND gate 316 is supplied with the timing signals TI, T2, and T3 from the OR gate 318, A
The ND gate 316 generates output signals "0" at timings T, , T2, and T3, and these output signals 0
The signals are sequentially provided through OR gate 152 to full adder 82 of FIG. Therefore, the full adder 82 has T,...
The reset is canceled at timings T2 and T3, respectively.

After the T3 channel of the address counter is released from reset in this manner, it starts counting. That is, the AND gate 320 generates an output signal "1" at timing T3 in response to the timing signal φ^+φB, and this output signal is supplied as a carry input Ci to the full adder 82 via the OR gates 114 and 116. Therefore, the count value of the address counter channel T3 increases each time it receives a carry input Ci. Then, the count data based on such counting operation is transferred from the shift register circuit 84 to the address data D1 to D at the timing of T5.
It is supplied as I2 to the latch circuit 322 of FIG. 1O.

The latch circuit 322 performs a latch operation in response to the output signal of the AND gate 324 which receives the timing signal T5 and the clock signal φ2, and latches address data at each timing of T5 and φ2.

The audio data memory 326 is, for example, R9M, and stores audio data (serial data) corresponding to the 15th scale major notes of F2 to F4 as described above. From the audio data memory 326, the latch circuit 3
According to the address data from 22, the audio data for the 15th scale major note is read out in parallel and in bit serial format at the beginning of each, and is supplied to the selector 328.

The decoder 330 decodes the pitch data RPC or MPC, and supplies the decoded output to the selector 328.

The selector 328 selects audio data corresponding to the scale name specified by the output of the decoder 330 from among the data read from the memory 326. The selected audio data is supplied to the latch circuit 332 and is output at timing T5. Latched.

The bit serial format audio data from the latch circuit 332 is supplied to the 3 consecutive detection circuit 334, and the delay circuit 3
36 and one input terminal of exclusive OR gate 338 . The delay circuit 336 is composed of a two-phase shift register that takes in an input at timing T22 and sends out at timing T5, and its output signal is supplied to the other input terminal of exclusive OR gate 338. . Therefore, the exclusive OR gate 338 determines whether the consecutive 2-bit signals are either "0" or "1".
If so, an output signal "0°" is generated, and otherwise an output signal "1'' is sent out.

The output signal of exclusive OR gate 338 is the output signal of OR gate 340
is supplied to one input terminal of the delay circuit 34.
2. Delay circuit 342 is similar to delay circuit 336 described above, and its output signal is supplied to the other input terminal of OR gate 340.

Therefore, the OR gate 340 is the exclusive OR gate 33
When the output signal of 8 is "0" and the output signal of the delay circuit 342 is 0", that is, when all consecutive 3-bit signals are 0" or "°1'", the output signal is "0".
”°, and otherwise sends out an output signal “1”.

The reason for providing such three consecutive detection circuits 334 is to change and control the step width according to the signal state of the audio data (“
This is to make it possible to increase the step width (if 3 bits of °0" or "°1" continue for 3 bits).

AND gate 344 connects timing signal T1 and φ to
B as an input, and its output signal is sent out as a timing signal TMI and also sent out as an output signal SQL via an OR gate 346. Also, the AND gate 348 operates at T according to the output signal of the AND gate 344.
3 consecutive detection circuits 334 at the timing of 1 and φ^+φB
This output signal is an OR signal.
350 as an output signal SO2.

AND gate 352 receives timing signal T2 and φ^+φ
B as input, and its output signal is at timing TM
Sent as 2. Also, the AND gate 354 is an
T2 and φ^+φB according to the output signal of the D gate 352
This audio data is sent out as an output signal Sol via an OR gate 346, and an output signal S02 via an OR gate 350. Sent as . and timing signals TMI and T
M2 and output signals Sol and SO2 are supplied to the circuit of FIG.

One circuit in FIG. 6 performs step width data formation processing at timing T1. This process is performed using the signals TM1. from FIG. This is done based on Sol and S02. In this case, the signals TMI and Sol are both the output signal T of the AND gate 344 in FIG.
B), and the signal S02 consists of the output signal of the three consecutive detection circuit 334 in FIG.

The step width calculation is generally performed as shown in (A) and (B) below.

(A) When "0pa" or "1" continues in serial audio data (amplitude change is large) Δ-ax -Δt-1 Δt-Δ1-+ +□ ...(1) (B) Above (A ) In these equations (1) and (2), Δt is the step width to be bundled this time, Δt-1 is the step width calculated last time,
Δmax is the maximum value of the step width, and n is a power constant that determines the rate of change of the step width and is a time constant in units of sampling periods.

In this embodiment, if there are three consecutive 0'' or "1°", an operation equivalent to the above equation (1) transformed into the following equation (3) is performed, and in other cases, is the above (2
) is transformed into the following equation (4), and the operation (2
(complement addition) is performed.

In FIG. 6, at the timing of 10φB to TI and φ, all six selectors in the selector group 356 are in a state of selecting input B in response to a selection signal consisting of the timing signal TMI.

Therefore, the upper 6 bits of the previous step width data from the 8th stage of the shift register circuit 84 (corresponding to 37 to 512) are sent to the selector group 356, ANDN
- is supplied to the exclusive OR gate group 358 via the exclusive OR gate group 6 and undergoes inversion processing in response to the signal 5O1='1''°.Then, the 6-bit data (inverted processed data) is OR gate group 1
68 to a full adder 82 as inputs B1-B6. At this time, the previous step width data from the eighth stage of the shift register circuit 84 is supplied as inputs A1 to AH of the full adder 82.

In such a state, the three consecutive detection circuits 3 in FIG.
Assuming that three consecutive "0" or "1" signals are detected in 34, the signal SO2 becomes "0" as described above, so the carry input C1 and the input B1'BI2 of the full adder 82 are both Therefore, the calculation of equation (3) above is executed.Also, assuming that the above three consecutive sequences are not detected, the signal SO2 is "1", and this signal “1” is an OR game for the full adder 82) 114 and 1
16 as the carry human power C1, and inputs as inputs B1-B12.

Therefore, the calculation of equation (4) above is executed.

Note that regarding equations (3) and (4) above, the constant n has the upper 6 bits shifted 6 bits in the lower direction, so
It becomes 26.

According to such a calculation, when three consecutive detections continue (when the amplitude rapidly decreases or increases), the step width increases, but o°゛ and "l"' are alternately unified. In such a case (when the vibration @ change is gradual), the step width becomes small and the followability of the predicted signal to the original sound signal is improved.At the timing of 6T2, the circuit in Figure 6 performs the predicted value data generation process. will be carried out. This processing is performed based on the signals TM2, Sol and SO2 from FIG. In this case, the signal TM2 is the output signal T2 of the AND gate 352 in FIG. 10 (φ^+φB)
The signals Sol and SO2 both consist of serial audio data from the AND gate 354.

The predicted value calculation is performed according to the following equation (5) if the signals Sol and 502 (serial audio data) are "0'", and is performed according to the following equation (6) if the signals Sol and 502 (serial audio data) are "1".

5t=St-1+Δt-1...(5) St, "5L-
1-ΔL-1 = St, +(Δt-1)+1 (6) Here, S
t is the predicted value to be bundled this time, 5t-1 is the predicted value obtained last time, and Δt-1 is the step width obtained last time.

In FIG. 6, at timings T2 and φC+φB, all six selectors in the selector group 356 are in a state of selecting input A in response to a selection signal a consisting of a timing signal TM2.

Now, the signals SO1 and SO2 are both "O'.

Assuming that, the upper 6 bits of the previous step width data from the first stage of the shift register circuit 84 (corresponding to 37 to 312) are sent to the selector group 356, the exclusive OR gate group 358, and the OR gate group 168. are supplied to the full adder 82 as inputs B, -B6.

At this time, the previous predicted value data is supplied from the 8th stage of the shift register circuit 84 as the input AI ``Al1 of the full adder 82.
In 58, since the signal SOI is 0'', no inversion processing is performed.Furthermore, the carry input CI and inputs B7 to BI2 of the full adder 82 are all 0'' because the signal SO2 is 0''. Therefore, the calculation of equation (5) above is executed.

Furthermore, if the signals Sol and 302 are both 1, then the upper 6 bits of the previous step width data from the first stage of the shift register circuit 84 (5
7 to SI2) are provided as inputs B1 to B6 to full adder 82 via selector group 356, exclusive OR gate group 358, and OR gate group 168. At this time, in the exclusive OR gate group 358, since the signal SO2 is "1°", inversion processing is performed.Furthermore, the carry input Ci and inputs B7 to B+2 of the full adder 82 are the signal 5O2=
“In response to 1pa, both become l”. Furthermore, the previous predicted value data is supplied from the eighth stage of the shift register circuit 84 as inputs A1 to AI2 of the full adder 82. Therefore, the operation of equation (6) above (two's complement addition)
is executed.

Note that AND gate Ao, OR gates 01 and 02,
The input is provided to set the minimum value of the step width. The upper 5 bits (corresponding to So to SI2) of the 6-bit step width data are all "'"
O”, the output signal of OR Kate 0 is “°0”
', and this output signal "0゛° is the AND gate Ao
is made non-conductive, and the signal °“1
Therefore, the step width data sent out via the selector group 356 at this time is expressed as r
olooo(N).

Based on the arithmetic processing of the step width and predicted value as described above, the shift register circuit 84 sends out 9-bit predicted value data D2 to Dlo for each sample point at timing T4, and supplies it to the circuit shown in FIG. be done.

In the circuit of FIG. 7, the predicted value data D2 to DIO are T
It is latched by the latch circuit 224 at the timing of 4 and φ2. This latched data is two's complement code data, and the bit corresponding to D+o is a sign bit. This sign bit signal SG is supplied to an AND gate 360 and ANDed with the timing signal TC2. AND gate 360 receives timing signal TC
conducts during the period T6 to T7 when 2 takes the “1′” level,
A sign bit signal SG is sent out. This sign hit signal SG is sent to an AND gate 246 via an OR gate 244.
is supplied to

Also, the sign bit signal SG from the AND game 1360
is provided to inversion circuit 236 via OR gate 240 and is used to control the code conversion process. That is, when the sign bit signal SG is “0°”, the inverting circuit 236 receives the 8-bit data (D
2 to D9) are sent as is. On the other hand, when the sign bit signal SG reaches 11 degrees, the inversion circuit 236 inverts the 8-bit data from the latch circuit 224, adds 1 to the least significant bit, and sends it out. As a result,
The inversion circuit 236 outputs 8-bit data 1 to KB converted from a two's complement code to a sine magnitude code, and is supplied to a shifter circuit 248 .

The shifter circuit 248 performs data transmission operations in different ways depending on whether the control force A, B, or C reaches "1°", as described above regarding piano sound generation. Data transmission from 248 is A,
This is done in synchronization with the sending of the sign bit signal SG from the ND gate 246.

The control input A becomes "1" when the output Kg (most significant bit) of the inversion circuit 236 becomes "1", and when the control input A becomes 1" in this way, the shifter circuit 24
8 continues to send 6-bit data consisting of 3 to 8 to the output of the inversion circuit 236 as amplitude data AM during the period T4 to T7. Also, the output 8-If t I'' is OR
AND-gate 246 is made conductive via gate 296, so that AND-gate 246 continues to deliver the sign bit signal SG from OR gate 244 during the period T4-T7.

The control power B consists of the output signal of the AND gate 288, and this output signal is T in response to the timing signal T Co when the output 8 is "0'° and the output 7 is 1".
It becomes 1゛° at the timing of 5 and T7. Therefore, from the shifter circuit 248, based on the control input B="1'", the 6-bit data of K2 to 7 is sent to the amplitude data AM at two timings of T5 and T7 during the period of T4 to T7.
Sent as . Further, the output signal "1" of the AND gate 288 is passed through the OR gate 296 to the AND gate 2.
46 conducts, the AND gate 246 outputs O.
The sign bit signal SG from the R gate 244 is T4 to T.
It is transmitted at the timing of T5 and T7'2 during the period of 7.

The control input C consists of the output signal of the AND gate 292, and this output signal becomes "1" at the timing of T7 in response to the timing signals T Co and T C+ when both the outputs 7 and 8 are "0". Therefore, the shifter circuit 248 outputs K based on the control human power C="1".
The 6-bit data of 6 to 1 is T7 during the period of Ta''T7.
It is sent out as amplitude data AM at the timing of . Further, the output signal of the AND gate 292 makes the AND gate 246 conductive via the OR gate 296, so the sign bit signal SG from the OR gate 244 is sent from the AND gate 246 at the timing of T7 during the period from T4 to T7. be done.

The 6-bit amplitude data AM and sign bit signal SG for each sample point sent in any of the above-mentioned modes are supplied to the circuit shown in FIG.

In the circuit of FIG. 8, the top two of the amplitude data AM
The 4-bit signal is input to the first decoder 2-98, and the remaining 4-bit signal is input to the second decoder 300.
The sign bit signal SG is supplied as a control input directly to the gate element GL and to the gate element GH via the inverter IV. Therefore, an analog voltage corresponding to the input amplitude data AM is generated at the output point M of the analog voltage generation circuit 302.

As illustrated in FIG. 11, the analog voltage generated in this way swings to the positive side with respect to the intermediate voltage Vc, such as vl(1, VH2) if the sign bit signal SG is "0", and the sign bit signal SG is "0". If SG is “1”, VL
I, VL2, it swings to the negative side with respect to the intermediate voltage VC. In FIG. 11, wA is the voltage VHI, VH2...VLI, VL2... sequentially sent from the output point M.
The predicted signal consisting of ... is shown as an analog signal waveform.

The analog voltage at the output point M is converted into one, two, or four pulses depending on the output timing by the pulse width regulation circuit 306. The pulse conversion operation in this case is performed using the clock signals φ1 and φ as described above regarding piano sound generation.
2 alternately switches the gate elements G11 and GI2, and when the analog voltage is generated from the output point M at the timing of T7 during the period of Ta=T7 in FIG. When the pulse is generated twice, two pulses are generated, and when the pulse is generated four times, T4, T5, T6, and T7, four pulses are generated. That is, in FIG. 11, the analog voltage below level L1 (corresponding to data Kl''K6 in FIG. 7) is sent out as one pulse at timing T7, and the analog voltage above level L1 and below level L2 ( The analog voltage above level L2 (corresponding to 3 to 8 in the data in Figure 7) is sent out as two pulses at two timings, T5 and T7. Compatible with T4, T5.T6 and T7
It is sent out as four pulses at a timing of four degrees.

As a result of the above, from the pulse width regulation circuit 306.

A predicted signal corresponding to, for example, the scale name "do" is obtained, which is composed of a pulse train that swings positive and negative with respect to the intermediate voltage Vc. This predicted signal is supplied to the speaker 40 via the buffer amplifier 308, the output amplifier 38 in FIG. 1, etc., and is produced as a first-order note, in the same manner as described above regarding piano sound generation. In this case, the predicted signal has twice the sound intensity at the point where it includes two pulses in the period T4 to T7, and
Since the sounding intensity is quadrupled where four pulses are included in the period T7, the decrease in amplitude caused by the bit shift is recovered.

In addition, in FIG. 6, the output S12 of the full adder 82 is T
When the signal becomes 1' at the timing of 3, the AND gate 362 generates an output signal "1". This output signal ``l'' is supplied to the circuit of FIG. 4 as a read completion signal SRE, and resets the flip-flop 312 via the shift register 364.

Therefore, the output Q of the flip-flop 312 becomes 1p, and this output Q is passed through the shift register 314 to A
ND gate 316 is supplied. AND gate 316 receives timing signal T+ from OR gate 318.
, T2, and T:, and these signals "1" are supplied to the full adder 82 via an OR gate 152 as a reset signal R5T. As a result, the full adder 82 transmits the address data indicating the last read address of the audio data memory 326 in FIG. 10, and then T1. They are reset sequentially at timings T2 and T3, and thereby the operation of generating scale notes for the first scale note is completed.

Thereafter, the scale tone generation operation described above is performed every time the tone generation enable signal DKO is generated.

[Effects of the Invention] As described above, according to the present invention, when digital waveform data is converted to/from A/A, the number of bits of digital waveform data is limited and the data input period is controlled according to the amplitude level. Therefore, it is possible to use a simple-configured /A converter with a small number of bits, and it is possible to recover the amplitude drop caused by the limitation on the number of bits.

In addition, as shown in the example, when envelope data or sound waveform data is D/A converted in a device that generates sounds such as musical instrument sounds and human voice sounds, the performance is almost comparable to the conventional case where the number of bits is not limited. You can get good sound quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a timing signal generation circuit, and FIG. 3 is a time chart showing various timing signals. Figure 4 is a circuit diagram of the performance data generation circuit, Figure 5 (a)
and (b) is a format diagram of the performance data. Figure 6 is a circuit diagram of the time division processing circuit. Figure 7 is a circuit diagram of the time division output circuit. Figure 8 is a circuit diagram of the D/A conversion circuit. , Figures 9(a) to (d) show D/A regarding piano sound generation.
FIG. 10 is a signal waveform diagram for explaining the conversion operation. FIG. 10 is a circuit diagram of the audio data generation circuit. FIG. 11 is a signal waveform diagram for explaining the D/A conversion operation regarding scale note generation. 32... Time division output circuit, 36... D/A conversion circuit, 224... Latch circuit, 248... Shifter circuit, 288, 292... AND gate. Applicant Nippon Musical Instruments Manufacturing Co., Ltd. Agent Patent Attorney Toshiaki Izawa

Claims (1)

[Claims] 1. (a) input means for sequentially inputting digital waveform data representing a desired waveform in bit parallel format; (b) detecting the amplitude level of the waveform based on the digital waveform data; , level detection means that generates an output signal when the amplitude level reaches a predetermined level, and (C) each time the digital waveform data is input, the input data is sent out with a focus number n smaller than the focus number m at the time of input. and 2 bit number limiting means, which transmits the input data from the lowest focus to the n-th bit for a predetermined period when the output signal is not generated, and transmits the input data from the lowest focus to the nth bit when the output signal is generated. (m-n) bits of data are truncated from the least significant bit, and the remaining n bits are transmitted for a period of 2 (11-n) times the predetermined period; (d) sequentially from the bit number limiting means; A D/A conversion device that includes a D/A converter that D/A converts transmitted n-bit digital waveform data and outputs an analog output signal. 2. In the D/A converter according to claim 1, the digital waveform data inputted from the input means represents an envelope of a musical tone, and
The /A converter receives as a control input a sound source signal having a frequency corresponding to the pitch of the musical tone, and outputs a musical tone signal obtained by adding the envelope to the sound source signal as the analog output signal. A D/A conversion device characterized by: 3. In the D/A converter according to claim 1, the digital waveform data inputted from the input means represents an amplitude value of a sound waveform, and
The converter receives as a control input a sign bit signal representing the sign of the amplitude value of the sound waveform, and converts a sound signal in the form of giving a sign to the amplitude value of the sound waveform in accordance with the sign bit signal into the analog output signal. A D/A conversion device characterized in that the D/A conversion device is configured to transmit data as a D/A conversion device.