JPH0312491B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a D/A converter, and more particularly to a D/A converter suitable for processing digital waveform data related to sound in a sound generating device such as an electronic musical instrument. [Summary of the Invention] When digital waveform data is D/A converted, the present invention limits the number of bits of the digital waveform data and controls the data input period according to the amplitude level, thereby achieving a large amplitude value with a small number of bits. is made reproducible. [Prior Art] Conventionally, in the case of digital electronic musical instruments, for example, digital waveform data representing a musical sound waveform is inputted to a D/A converter to obtain an analog musical sound signal. In this case, the D/A converter has
Digital waveform data is input in bit parallel format, but when it is desired to faithfully reproduce the waveform, it is common to perform D/A conversion without truncating the lower bits. [Problems to be Solved by the Invention] According to the above-mentioned prior art, if the number of bits of digital waveform data is small, the configuration of the D/A converter becomes simple. However, when the number of bits of digital waveform data is large, the structure of the D/A converter becomes complicated. Furthermore, although the configuration of the D/A converter can be simplified by truncating the lower bits, there is a problem in that the reproducibility of the waveform deteriorates. [Means for Solving the Problems] The present invention has been made to solve the above problems, and includes limiting the number of bits of digital waveform data when digital waveform data is D/A converted. In addition, the data input period is controlled according to the amplitude level. That is, the D/A converter according to the present invention is provided with input means, level detection means, bit number limiting means, and a D/A converter. The input means is for sequentially inputting digital waveform data representing a desired waveform in bit parallel format, and is constituted by, for example, a latch circuit. The level detection means detects the amplitude level of the waveform based on the digital waveform data, and generates an output signal when the amplitude level reaches a predetermined level, and is composed of, for example, a logic circuit that inputs the upper bits of the digital waveform data. be done. The bit number limiting means converts the input data into a bit number n smaller than the number of bits m at the time of input and sends out the digital waveform data every time the digital waveform data is input, and when the level detection means does not generate an output signal, the input data is The data from the least significant bit to the nth bit is sent out during a predetermined period of time, and when the level detection means generates an output signal, the input data is truncated by (m-n) bits from the least significant bit, and the remaining n bits are sent out for a predetermined period of time. The period is now 2 ^(mn) times longer. Such bit number limiting means is constituted by, for example, a shifter circuit. The D/A converter performs D/A conversion on n-bit digital waveform data sequentially sent from the bit number limiting means and sends out an analog output signal. In such a configuration, the digital waveform data inputted from the input means represents the envelope of the musical tone, and the D/A converter receives as a control input a sound source signal having a frequency corresponding to the pitch of the musical tone, and the D/A converter receives the sound source signal having a frequency corresponding to the pitch of the musical tone. A configuration may also be adopted in which a musical tone signal with an envelope added to the signal is sent out as an analog output signal. Further, the digital waveform data inputted from the input means represents the amplitude value of the sound waveform, and the D/
The A converter is configured to receive a sign bit signal representing the sign of the amplitude value of the sound waveform as a control input, and to send out as an analog output signal a sound signal in the form of giving a sign to the amplitude value of the sound waveform in accordance with the sign bit signal. Good too. [Operation] According to the configuration of the present invention, when the digital waveform data is, for example, 8 bits (m=8),
For example, 6-bit (n=6) data is supplied to the D/A converter via a bit number limiting means. Therefore, a 6-bit D/A converter suffices, which simplifies the configuration. Also, in the D/A converter, for example, if the upper 2 bits are “0”, the lower 6 bits are “0”.
Bits are supplied for a predetermined period, and if the most significant bit is "1", the upper 6 bits (1/4 data) with the lower 2 bits discarded are supplied for a period of ²² times the predetermined period, so the lower 1 bit is D/ when rounded down
The output period of the A converter is four times the output period when the lower bits are not truncated. Therefore, by acoustically exchanging the D/A converted output obtained in this way using a speaker or the like, it is possible to recover the amplitude decrease due to the limitation on the number of bits. In the configuration of the present invention, as described above, by D/A converting the envelope data and the sound wave data, it is possible to generate sound of almost the same quality as when the number of bits is not limited. [Embodiment] FIG. 1 shows an electronic musical instrument according to an embodiment of the present invention. This electronic musical instrument has a total of manual piano mode, manual scale mode, auto piano mode, and auto scale mode. It is designed to be able to selectively operate in four modes. Here, the general operations for each mode are as follows (1) to (4). (1) Manual piano mode Generates a piano sound with a pitch corresponding to the pressed key based on manual performance operations on the keyboard. (2) Manual scale name mode Based on manual playing operations on the keyboard, the pitches of "C", "R", and "Mi" are selected based on the pitch corresponding to the pressed key.
Generate scale notes such as (3) Auto piano mode Automatically generates piano sounds by reading performance data from the performance data memory. In this case, the pitch of the piano sound is determined according to the pitch data included in the performance data. Also,
In the autopiano mode, scale notes can be generated in the same manner as in the manual scale mode described above, and manual scale notes can also be performed in conjunction with the autopiano performance. (4) Auto scale name mode Scale name notes are automatically generated by reading performance data from the performance data memory and reading audio data corresponding to the scale name from the audio data memory. In this case, the pitch of the scale note is determined according to the pitch data included in the performance data. Furthermore, in the automatic scale mode, piano sounds can be generated in the same manner as in the manual piano mode described above, and manual piano performance can also be performed in conjunction with the automatic scale performance. In FIG. 1, a mode selection circuit 10 includes a mode selection switch 12 and two OR gates 14 and 16. The mode selection switch 12 includes manual piano mode MP, manual scale mode MD, auto piano mode AP,
Auto floor name mode can be set to any position in AD. The OR gate 14 is designed to generate an output signal SL="1" when the mode selection switch 12 is set to the MD or AP position.
In addition, the OR gate 16 is connected to the mode selection switch 1.
2 is set at the AP or AD position, output signal AUT="1" is generated. The timing signal generation circuit 18 generates various timing signals for controlling the generation operation of piano tones and scale tones, the details of which will be described later with reference to FIG. 2. The keyboard circuit 20 includes, for example, a keyboard having 25 keys corresponding to notes _F2 to _F4 , and is pressed by repeatedly scanning a key switch corresponding to each key in a predetermined order. It is designed to generate pitch data KPC corresponding to the key. The keyboard circuit 20 is provided with a single note selection circuit,
When a plurality of keys are pressed at the same time, pitch data KPC corresponding to the one key having the slowest scanning order among these pressed keys is selectively transmitted. Each pitch data KPC
represents the pitch of each key using 5 bits, with the most significant bit being an octave code and the remaining 4 bits being a note code. In addition, each pitch data
The KPC continues to be sent while the corresponding key is pressed. The performance data generation circuit 22 includes, for example, a performance data memory that stores performance data for 20 songs, and the performance data for which song is read from this performance data memory depends on which key is pressed on the keyboard when the power is turned on. It has come to be determined by In other words, when the power is turned on, if the pitch data KPC from the keyboard circuit 20 indicates the pitch corresponding to the _F4 key, the performance data memory will record the pitch data from the first to
Performance data for 20 songs is read out sequentially, and pitch data is
If the KPC indicates a pitch corresponding to a specific key other than the _F4 key, performance data of the specific song corresponding to the key pressed at this time is read from the performance data memory. In other words, if you press the _F4 key, all songs will be specified (all 20 songs will be read out sequentially), and if you press any desired key other than the _F4 key, you will be able to specify a specific song (the desired one of the 20 songs will be read out). (selective readout). Note that when specifying a specific song, which key is pressed to select which song is determined in advance. Performance Data Reading Operation Here, the data reading operation from the performance data memory will be briefly described. When a song to be read is specified as described above, the tempo data of the specified song (the first song if all songs are specified) is read from the performance data memory, and then the tempo data of the first song of the song is read out from the performance data memory. The pitch data and note length data of the note are read out. Time division processing circuit 24 for reading performance data
(A1) Counting the reference clock signal for tempo setting to generate reference clock count data, (A2) Counting the tempo clock signal to generate tempo clock count data, and (A3) Ending note length. The process of counting timing signals and generating address data for reading is executed in a time-division manner. The performance data generation circuit 22 includes the time division processing circuit 2
A tempo clock signal having a frequency corresponding to the tempo of a designated song is generated based on the reference clock count data sent as data output DOA from 4 and the tempo data read from the performance data memory. This tempo clock signal is the output signal.
It is supplied as PO to the time division processing circuit 24 and counted. The performance data generation circuit 22 calculates the note length of the first note based on the tempo clock count data sent as the data output DOA from the time division processing circuit 24 and the note length data of the first note read from the performance data memory. The end timing is detected and a note length end timing signal is generated. This code length end timing signal is supplied as an output signal PO to the time division processing circuit 24, and in response, the circuit 24 advances the read address by one. The read address data at this time is supplied to the performance data generation circuit 22 as the data output DOA, and in response, the pitch data and note length data of the second note are read from the performance data memory. Thereafter, pitch and note length data are read out for each note in the same manner. For rests, pitch data with all bits "0" and note length data corresponding to the rest length are read out. By the performance data reading operation as described above, the performance data generation circuit 22 sends out pitch data MPC for each note regarding the designated song. Each pitch data
MPC uses 4 bits to represent the pitch of each note, with the most significant bit being an octave code and the remaining 3 bits being a note code. Note that each pitch data MPC continues to be transmitted until the corresponding note length ends. In the performance data generation circuit 22, reading of data from the performance data memory is prohibited unless any key is pressed on the keyboard when the power is turned on. Therefore, when the power is turned on, the keyboard operations only need to be performed to specify all songs or specific songs (selection) when auto piano mode AP or auto scale mode AD is selected; manual piano mode When MP or manual hierarchy mode MD is selected, it is sufficient not to press any keys. Note that address data ADD is supplied from the performance data generation circuit 22 to the time division processing circuit 24 for subroutine processing to be described later, and address data ADD is supplied from the time division processing circuit 24 to the performance data generation circuit 22 for the audio data readout processing to be described later. completion signal
SRE is supplied. The piano sound generator selector 26 receives the pitch data MPC from the performance data generation circuit 22 and the pitch data KPC from the keyboard circuit 20 as inputs A and B, respectively, and selects the output signal SL from the OR gate 14. If the signal SA is “1”, input A is selected as the selection signal.
If SA is "0", input B is selected. Here, the output signal SL (selection signal SA) of the OR gate 14 is "1" in the case of manual scale mode MD and auto piano mode AP, but as described above, in the case of manual scale mode MD Since the pitch data MPC is not generated in , the selector 26 selectively sends out the pitch data MPC only in the auto piano mode AP. In addition, the output signal (selection signal SA) of the OR gate 14 becomes "0" in the manual piano mode MP and in the auto scale mode AD, and in these cases, pitch data KPC is generated by key press operation. Then, the selector 26 selectively sends out pitch data KPC. Pitch data KPC sent from selector 26
Alternatively, the MPC is used to generate piano sounds, and according to the operation of the selector 26 described above, piano sounds can be generated in each of the auto piano mode AP, manual piano mode MP, and auto scale mode AD. . Pitch data KPC or MPC from selector 26
Of these, the note code data NT is sent to the decoder 28.
is supplied to The decoder 28 has F, F#...E
It has 13 output lines corresponding to the 12 note names and the ₄ notes of F. It decodes the note code data NT to detect the note name and sends out an output line signal "1" corresponding to the note name. It's becoming like that. The 13 output lines of decoder 28 are ROM
(read-only memory), and the memory 30 is adapted to send out 8-bit frequency division control data DVC in response to the output of the decoder 28. .
Here, the frequency division control data DVC is exemplified with the right end as the most significant bit.For pitch name F, it is "01110110", for pitch name F#, it is "01101000", and for _F4 note, it is "10111011". It is generated as follows. Pitch data KPC or MPC from selector 26
Of these, the octave code signal (signal of the most significant bit) OCT is supplied to the time division output circuit 32 in order to control the variable frequency division operation when forming the sound source signal. Further, the OR gate 34 which receives the signal of each bit of the pitch data KP or MPC from the selector 26 takes the "1" level during the period when any bit is "1" for each pitch data. A sound generation enabling signal PKO is generated, and this signal PKO is supplied to the time division processing circuit 24 in order to determine the rise timing of the piano envelope. The time division output circuit 32 selectively supplies a high speed clock signal φ _H and a low speed clock signal φ _L for forming envelope data to the time division processing circuit 24 according to the frequency switching signal FC from the time division processing circuit 24. It's getting old. Here, the high speed clock signal φ _H is used to obtain a relatively steep decay curve, and the low speed clock signal φ _L is used to obtain a relatively gentle decay curve. Regarding piano sound generation, the time division processing circuit 24:
(B1) Processing that counts pulses and generates a divided output according to frequency division control data DVC, (B2) Counts high-speed clock signal φ _H or low-speed clock signal φ _L to generate envelope data representing a piano envelope. This process is executed in a time-sharing manner. The time division output circuit 32 outputs the frequency division output sent as data output DOB from the time division processing circuit 24 and the octave code signal from the selector 26.
Based on OCT, a square wave sound source signal TG having a frequency corresponding to the pitch is generated for each pitch data, and the 8-bit envelope data sent as data output DOB is inverted and processed according to the amplitude level. Bit shift processing is performed to generate 6-bit envelope data EV. Then, the sound source signal TG and envelope data EV are
The signal is supplied to a digital/analog (D/A) conversion circuit 36. The D/A conversion circuit 36 converts envelope data
A piano envelope is added to the sound source signal TG according to EV. This enveloped sound source signal is supplied to the speaker 40 via the output amplifier 38, so that the speaker 40 generates a piano sound. The scale note generation section selector 42 receives pitch data MPC from the performance data generation circuit 22 and pitch data KPC from the keyboard circuit 20 as inputs A and B, respectively, and outputs the output signal SL of the OR gate 14 from the inverter. The selector 44 performs a selection operation opposite to that of the selector 26 described above in response to the selection signal SA inverted by the selector 44. That is, the selection signal SA is "1" in the manual piano mode MP and the auto scale mode AD, but as mentioned above, the pitch data MPC is not generated in the manual piano mode MP. selector 42
From here, pitch data MPC is selectively transmitted only in the case of auto scale mode AD. In addition, the selection signal SA
is "0" in manual scale mode MD and auto piano mode AP, and in these cases, when pitch data KPC is generated by key press operation, pitch data is output from selector 42.
KPC is selectively sent. Pitch data KPC sent from selector 42
Alternatively, the MPC is used for generating scale notes, and according to the operation of the selector 42 described above,
Auto floor name mode AD, manual floor name mode
Scale notes can be generated in each case of MD and autopiano mode AP. The pitch data KPC from the selector 42 is supplied to the audio data generation circuit 46, and is used to select the audio data of the scale name corresponding to the pitch. For example, the audio data generation circuit 46 generates audio data corresponding to two octaves of 15th-order notes such as "hua", "g"..."do", "re"..."do"..."hua". Contains stored audio data memory. In this embodiment, a so-called adaptive delta modulation digital speech synthesis system is adopted, so the speech data memory stores the speech signal as one bit (“0” or “1”) for each scale tone in time series. The serial code data encoded in is stored as audio data. In addition, the encoding in this case is
A method that samples an audio signal at a fixed period, obtains a predicted value for each sample point, and assigns "1" or "0" depending on the positive or negative sign of the difference between the predicted value and the actual value. It is known per se. Regarding the scale tone generation, the time division processing circuit 24:
(C1) Processing of counting clock signals to generate address data for reading audio data, and (C2) Calculating step width corresponding to amplitude change based on data read from audio data memory to generate step width data. and (C3) the process of calculating a predicted value of amplitude based on step width data to generate predicted value data are executed in a time-sharing manner. Pitch data KPC or MPC from selector 42
OR gate 48 which receives the signals of each bit of
is, one bit is “1” for each pitch data.
A sound generation enable signal DKO is generated which takes the "1" level during a certain period. This soundable signal DKO
acts to reset and cancel the address counter of the time division processing circuit 24 via the performance data generation circuit 22. After this reset is released, the address counter counts the clock signals and generates address data, and in response, the audio data for the 15th scale note is sent in parallel from the audio data memory, and each note is stored in bit serial format. is read out. Then, from among the read audio data, audio data with a scale name corresponding to the pitch indicated by the pitch data at that time is selected. Based on the audio data selected in this way, the audio data generation circuit 46 supplies the signals necessary for the above-described step width calculation and predicted value calculation to the time division processing circuit 24 as the output signal SO. The time division processing circuit 24 includes the audio data generation circuit 4
Based on the output signal SO from 6, step width data for each sample point in the waveform of a specific scale note (for example, "C" of a specific octave) is formed, and the output signal SO and each sample point formed are Predicted value data for each sample point is formed based on step width data for each step, and each predicted value data is sent out as a data output DOB. Each predicted value data sent out in this manner is 9-bit two's complement code data, the most significant bit of which is a sign bit. The time-division output circuit 32 code-converts each predicted value data supplied as data output DOB from the time-division processing circuit 24 from a two's complement code to a sine magnitude code, and also converts the code-converted data into a sine magnitude code. By performing bit shift processing according to the level, amplitude data AM and sign bit signal SG for each sample point are sent out.
Here, each amplitude data AM indicates the magnitude of the predicted amplitude value, and each sign bit signal indicates the sign (positive or negative) of the predicted amplitude value as "1" or "0".
This is shown in . The D/A conversion circuit 36 reproduces a predicted signal by D/A converting the amplitude data AM and sign bit signal SG for each sample point supplied from the time division output circuit 32. When viewed as an analog signal waveform, this predicted signal shows a waveform that approximately corresponds to the change in the predicted value obtained during encoding.
Since the signal is supplied to the speaker 40 via the output amplifier 38, the scale tone is generated from the speaker 40. In addition, in the above explanation, the piano note or the scale note are each pronounced independently, but in the case of auto piano mode AP or auto scale note mode AD, the piano sound generation process and the scale note generation process are Since it is executed in a time-sharing manner, from the speaker 40,
Piano notes and scale notes can be generated simultaneously. Timing Signal Generating Circuit FIG. 2 shows a detailed configuration of the timing signal generating circuit 18. As shown in FIG. The frequency dividing circuit 50 has a frequency of 1.46 [μs] as shown in FIG.
_The master clock signal φ _M having _a period of
This occurs as shown in the figure. Both clock signals φ ₁ and φ ₂ have a period of 2.91 [μs]. The frequency divider circuit 52 divides the output signal of the frequency divider circuit 50 to generate a high-speed clock signal φ _H and a low-speed clock signal φ _L for forming a piano envelope, and also generates a reference clock signal TCL ₀ for setting the tempo. It is something to do. High speed clock signal _φH is 0.47
The low-speed clock signal φ _L has a period of [ms].
It has a period of 9.32 [ms], and the reference clock signal
TCL ₀ has a period of 18.64 [ms]. The shift register circuit 54 is reset by an initial clear signal IC generated in synchronization with power-on, and outputs _Q0 to Q0 at the time of reset.
The output signal “1” of the NOR gate 56 according to Q ₇ is
FIG. 3 shows sequential timing signals T ₀ -T ₇ received as data input D through OR gate 58 and shifted in response to clock signals φ ₁ and φ ₂ as outputs Q ₀ -Q ₇ . This is how it occurs. Each of the timing signals T ₀ to T ₇ has a period of 23.3 [μs], and each timing pulse has a pulse width corresponding to one period of the clock signal φ ₁ , and the timing signals T 0 to T 7 each have a period of 23.3 [μs], and each timing pulse has a pulse width corresponding to one period of the clock signal φ 1. used to control time-sharing processing. The OR gate 60 receives timing signals T ₁ , T ₃ ,
_T5 and _T7 are input, timing signal
TC ₀ is generated as shown in FIG. Also, OR
Gate 62 receives timing signals T ₂ , T ₃ , T ₆ and
It takes _T7 as an input and generates a timing signal _TC1 as shown in FIG. Further, the OR gate 64 receives timing signals T ₄ to _{T 7} as input, and generates a timing signal TC ₂ as shown in FIG. The quaternary counter 66 receives an initial clear signal.
After being reset by the IC, the timing signal
It counts _T7 . NOR gate 68 is
Output Q ₁ of counter 66 and output of counter 66
The output of the inverter 70 which inverts _Q2 is input, and the timing signal _φA is generated as shown in FIG. Further, the NOR gate 72 receives the outputs Q ₁ and Q ₂ of the counter 66 as inputs, and
A timing signal φ _B is generated as shown in FIG. Timing signals φ _A and φ _B are both 93.2 [μs]
It has a period of OR gate 74 receives timing signals φ _A and φ _B as input and generates timing signal φ _A +φ _B as shown in FIG. This timing signal φ _A + φ _B
is supplied to an AND gate 78 via an inverter 76, and is ANDed with the timing signal _T2 .
As a result, the AND gate 78 generates a timing signal _T22 as shown in FIG. Details of Performance Data Reading Operation In the performance data generation circuit 22, as shown in FIG.
A performance data memory 80 is provided, and this memory 80 stores performance data for 20 songs in a format as shown in FIG. That is, as shown in FIG. 5a, the start address data indicating the start address of song A (first song) is stored at address 0, and the following address data for songs B, C, D, etc. is stored in the address progression. Performance data is stored.
Furthermore, the performance data for each song includes a main routine section and a subroutine section each consisting of 7-bit data arranged in sequence, as shown in a typical example in Figure 5b for song A. After the tempo data, pitch and note length data for each note are arranged sequentially, and in the middle of the pitch and note length data arrangement, 2-byte data related to the subroutine, that is, subroutine jump data and relative address data are arranged. , pitch and note length data for each note are sequentially arranged in the subroutine section, and
Subroutine return data is placed at the end of the pitch/note length data array. In the main routine section, after the pitch and note length data of the final note, song end data and start address data of the next song (in this case, song B) are sequentially arranged. It should be noted that since the last song (the 20th song) is not called the next song, stop data for stopping reading is placed at a position corresponding to the start address data of the next song. The tempo data is for setting the tempo of the song, and the upper 4 bits are an identification code (1110), and the remaining 3 bits represent the tempo value. Each pitch/note length data represents the pitch and note length of each note, with the upper 4 bits being a pitch code and the remaining 3 bits being a note length code. The most significant bit of the pitch code is an octave code, and the remaining three bits are a note code, and for rests, all bits of the pitch code are set to "0". The subroutine jump data is for instructing a jump to the subroutine section.
The bit is the identification code (1100) and the remaining 3 bits are unused. The subroutine section was provided because if the same section of a song is played repeatedly, storing the performance data corresponding to that section for the number of times will increase the memory capacity, so the performance data of that section is stored in the subroutine section. By storing the data in the subroutine section, jumping to the subroutine section as needed to perform, and then returning to the original position (subroutine return) when the performance is finished, the memory can be played. This is to reduce the capacity. The relative address data is used to enable specification of the start address of the subroutine section, and indicates an address value that is determined relatively according to the address where the relative address data is stored. In other words, the first address of the subroutine part is the A _S address,
Assuming that the storage address of the relative address data is the _AR address, the relative address data indicates an address value of ( _AS - _AR ). The song end data is for indicating the end of the song, and the upper 4 bits are an identification code (1111), and the remaining 3 bits are unused. The start address data of the next song indicates the address where the first data (tempo data) of the performance data of the next song is stored. It is designed to represent an address value. The subroutine return data is for instructing a return from the subroutine section to the main routine section, and the upper 4 bits are an identification code (1101) and the remaining 3 bits are unused. Time division processing circuit 24 regarding performance data reading
As described above, the reference clock count data generation process (A1), the tempo clock count data generation process (A2), and the read address data generation process (A3) are executed in a time-sharing manner. Here, the processing timing and output timing in each process (A1) to (A3) are determined by the above-mentioned timing signal T ₀ to
Table 1 below shows _T7 .

[Table] According to Table 1, it can be seen that the output timing is delayed by two pulses in timing signals such as T ₀ to T ₇ , that is, two periods of clock signal φ ₁ , compared to the processing timing. . In the time division processing _circuit 24, as _{shown in} FIG _. An 8-stage/12-bit shift register circuit 84 is provided, and this shift register circuit 84 takes in an input for each bit with a clock signal _φ2 , and outputs it with a clock signal _φ1 . phase shift register
It consists of 8 SFs connected in series. For example, when a timing signal like _T0 in Figure 3 is input, the number "1" written in the block of shift register SF is delayed by one pulse (one cycle of clock signal _φ1 ). This means that an output signal such as T ₁ is obtained, and this applies by analogy to similar blocks with numbers written inside them in FIG. 6 or FIG. For example, "6"
The block described is a 6-stage/1-bit shift register that provides a delay of 6 pulses. The output signals of the time division processing circuit 24 include the outputs D ₁ to 2 of the second stage of the shift register circuit 84.
_D12 is now taken out, and this corresponds to the fact that in the explanation of Table 1, the output timing is delayed by two pulses from the processing timing. In the performance data reading operation, the full adder 82
The lower 6 bits of the shift register circuit 84 are used as an 8 stage/6 bit time division counter. Assuming that the power is turned on by pressing the _F4 key on the keyboard, in the circuit shown in FIG. 4, the latch circuit 86 latches the high pitch data KPC from the keyboard circuit 20 in response to the initial clear signal IC.
This pitch data KPC indicates the pitch corresponding to the _F4 keyboard, and the chord detection circuit 88
generates _F4 key detection signal F4="1" and selector 9
0 is set to input A selection state. At this time, the no-key pressed signal NK sent from the code detection circuit 88 is "0" because the key has been pressed, and this signal "0" is transmitted via the inverter 92 to the chip enable signal CE.
= "1" and is supplied to the performance data memory 80. Therefore, the data at address 0, that is, the start address data of song A, is read out from the memory 80 and supplied to the latch circuit 94 via the selector 90, where it is supplied in response to the initial clear signal IC from the OR gate 96. It will be latched. Then, when the timing of T ₁ and φ ₂ comes,
Since the AND gate 98 generates an output signal "1", the pitch data corresponding to the F4 key from the latch circuit 94 is latched in the latch circuit 100, and the pitch data corresponding to the _F4 key is latched in the latch circuit 102 as shown in FIG. Address data D ₁ to _{D 6} from the time division counters are latched. All bits of this address data _D1 to _D6 are "0". This is because, in FIG. 4, when the R-S flip-flop 101 is reset by the initial clear signal IC, the sixth
The full adder 82 in the figure is the AND gate 103 in FIG.
This is because the reset is released at the timing of _T7 by the output signal "0" of the time division counter, and the count value of the _T7 channel of the time division counter is zero. The latch data of the latch circuit 100 and the latch data of the latch circuit 102 are stored in the memory 80 as upper address data and lower address data, respectively.
Therefore, the tempo data of song A is read out from memory 80. This tempo data is supplied to the decoder 104, and in response, the decoder 104 generates a tempo data detection signal TEM="1". This detection signal
TEM is supplied to the AND gate 106, and the AND gate 106 outputs a signal “1” at the timing of _T6 .
The latch circuit 108 latches the tempo data from the memory 80 in response to this output signal "1". Tempo data detection signal TEM is OR gate 11
0 as an address increment signal ADU to the AND gate 112 in FIG.
12 generates an output signal "1" at the timing of _T7 . This output signal "1" is a carry input C _i to the full adder 82 via OR gates 114 and 116.
Therefore, the _T7 channel of the time division counter has a count value of 1. Address data D ₁ to _{D 6} indicating the count value 1 is sent out from the shift register circuit 84 at timing T ₁ and latched by the latch circuit 102 shown in FIG. 4 at timing T ₁ and φ ₂ . Therefore, the pitch and note length data of the first note of the song A are read out from the memory 80. Among the read data at this time, pitch data is supplied to the decoder 104 and the latch circuit 118,
The code length data is supplied to a decoder 120. When the decoder 104 receives the pitch data, all of its five output signals become "0", and accordingly,
NOR gate 122 outputs pitch data detection signal PC=
Generates “1”. This detection signal PC is supplied to the AND gate 124, and the AND gate 124 generates an output signal "1" at timing _T6 , and in response to this, the latch circuit 118 latches the pitch data from the memory 80. Therefore, the pitch data of the first note is output from the latch circuit 118 as the pitch data MPC.
Sent as . Furthermore, since the gate circuit 126 becomes conductive at the timing _T6 , which is the same timing as the transmission timing of the pitch data MPC, the output of the decoder 120 that has decoded the note length data of the first note is transmitted from the ROM via the gate circuit 126. It is supplied to the note length code memory 128. This memory 128 encodes the output of the decoder 120 according to the note length type (for example, quarter note length) so that it can be compared with the count output of the time division counter shown in FIG.
The code length code data from 8 is supplied to a comparison circuit 132 via an OR circuit 130. By the way, the tempo data previously latched by the latch circuit 108 is supplied to a tempo code memory 138 consisting of a ROM via a gate circuit 136 which becomes conductive at timings other than _T6 in accordance with the output signal of the inverter 134. This memory 138
The tempo value data consisting of the lower three bits of the tempo data is code-converted so that it can be compared with the count output of the time division counter shown in FIG. The signal is supplied to the comparison circuit 132 via. In FIG. 6, the AND gate 140 receives the reference clock signal for tempo setting at timing _T0 .
The reference clock signal TCL ₀ is supplied to full adder 82 via OR gates 114 and 116 as a carry _{input Ci} . Therefore, the count value of the T ₀ channel of the time-resolved counter increases by 1 every time the reference clock signal TCL ₀ is counted. Then, the reference clock counting data D ₁ based on such counting operation is
~D ₆ is the comparison circuit 1 of Fig. 4 at each timing of T ₂ .
32 and is compared with tempo code data from memory 138. In the comparison circuit 132, when the reference clock count data and the tempo code data match,
A match signal EQ is generated. This coincidence signal EQ is passed through shift registers 142 and 144 as a tempo clock signal TCL to the AND gate 14 in FIG.
6, and the tempo clock signal TCL is sent from the AND gate 146 at timing _T4 . In addition, in FIG. 4, the shift register 114
The tempo clock signal TCL sent from the tempo clock signal TCL is supplied to an AND gate 150 via a shift register 148. At this time, the AND gate 150 is supplied with an output signal "1" from the OR gate 16 in FIG.
Sends the tempo clock signal TCL at timing _T0 . This tempo clock signal TCL is passed through an OR gate 152 as a reset signal RST.
It is supplied to full adder 82 in the figure and causes it to be reset. Therefore, all bits of the _T0 channel of the time division counter become "0", and thereafter, the reference clock signal _TCL0 is counted in the same manner as described above. As a result of the above comparison and counting operation, the result shown in Figure 6 is as follows.
A tempo clock signal TCL having a frequency corresponding to the tempo value indicated by the tempo data of song A is sent from the AND gate 146. This tempo clock signal TCL is input to the full adder 82 via OR gates 114 and 116, so that the _T4 channel of the time division counter increases the count value by 1 every time the tempo clock signal TCL is counted.
It increases gradually. The tempo clock count data D ₁ to D ₆ based on such counting operation is supplied to the comparison circuit 132 in FIG. 4 at every timing T ₆ and is compared with the note length code data of the first note from the memory 128. . When the tempo clock count data and the note length code data match in code in such a comparison operation, a match signal EQ is generated. This match signal
EQ is supplied to the OR gate 110 via the shift register 142 as the mark length end timing signal LET, and from this OR gate 110 is supplied as the address increment signal ADU to the AND gate 112 in FIG. The note length end timing signal LET at this time is
This indicates the end timing of the note length of the first note, and starts from the AND gate 112 at the timing of _T7 .
Full adder 8 via OR gates 114 and 116
2 is input. Therefore, the time-resolved counter
The count value of channel T ₇ increases by 1. Address data D ₁ to _{D 6} corresponding to this increase in count value
is sent out from the shift register circuit 84 at timing _T1 , and latched by the latch circuit 102 of FIG. 4 at timing _T1 and _φ2 . Therefore, the pitch and note length data of the second note of song A are read out from memory 80. Further, the mark length end timing signal LET from the shift register 142 is supplied to the AND gate 153 via the shift registers 144 and 148.
In response, the AND gate 153 generates an output signal "1" at timing _T4 . This output signal "1" is supplied as a reset signal RST to the full adder 82 in FIG. 6 via the OR gate 152.
Reset this. Therefore, all bits of the _T4 channel of the time division counter become “0”,
Thereafter, the tempo clock signal TCL is counted for the note length data of the second note in the same manner as described above. By repeating the same note length measurement and address increment operations as described above, the latch circuit 118 successively sends out pitch data MPC. As the pitch/note length data reading operation progresses as described above, T ₁ and φ ₂ are eventually read from the memory 80.
The subroutine jump data is read out at the timing , and in response to this, the decoder 104 generates the subroutine jump detection signal SUB•J="1". This detection signal SUB.J is latched by the latch circuit 154 at timing _T6 . In addition, the detection signal SUB・J is passed through the OR gate 110 as shown in FIG.
is supplied to AND gate 112, and from this AND gate 112 via OR gates 114 and 116.
It is input to the full adder 82 at timing _T7 .
Therefore, the count value of the channel _T7 of the time division counter increases by 1, and the address data _D1 to _D6 corresponding to this increase in count value are sent out from the shift register circuit 84 at the timing of _T1 . The address data D ₁ to _{D 6} indicate the storage address _AR of relative address data. At this timing of _T1 , the latch circuit 154
The latch signal SUB・J of the latch circuit 156 is latched, while the latch circuit 158 has the AND signal SUB・J of the latch circuit 154 latched.
Based on output signals generated from gate 160 at timings _T1 and _φ2 , address data indicating address _AR is latched. At the same time, address data indicating the address A _R is latched into the latch circuit 102 at the timings _T1 and _φ2 .
In response, relative address data is read from memory 80. This relative address data is (A _S − A _R ), where A _S is the starting address of the subroutine section.
This indicates the address. Next, at timing _T7 , the AND gate 162 activates the latch signal SUB・ of the latch circuit 156.
In response to J, an output signal "1" is generated, and in response, the gate circuit 164 becomes conductive. Therefore, the relative address data read from the memory 80 is supplied as inputs B ₁ to B ₆ to the full adder 82 via the gate circuit 164 and the OR circuit 166, and further via the OR gate group 168 in FIG. Ru. At this time,
Since the inputs A ₁ to _{A 6} of the full adder 82 are supplied with address data indicating the address A _R , the outputs S ₁ to _{S 6} of the full adder 82 are the first address A _S of the subroutine section. The address data shown is obtained,
This address data is sent out from the shift register circuit 84 at timing _T1 , and latched by the latch circuit 102 in FIG. 4 at timings _T1 and _φ2 . As a result, the pitch and note length data of the subroutine section are sequentially read out from the memory 80 in the same manner as in the main routine section described above. After this, when the note length of the last note of the subroutine part ends, T ₁ and φ ₂ are stored from the memory 80.
The subroutine return data is read out at the timing , and in response to this, the decoder 104 generates the subroutine return detection detection signal SUB•R="1". This detection signal SBU・R is AND gate 1
70 and accordingly AND gate 17
0 generates an output signal "1" at the timing of _T7 and makes the gate circuit 172 conductive. Therefore, the address data indicating the address A _R latched in the latch circuit 158 is input to the full adder 82 via the gate circuit 172 and the OR circuit 166, and further via the OR gate group 168 in _FIG. Supplied as ~ _B6 . At this time, the detection signal SUB・R is
Set the output signal of NOR gate 174 to “0”
Since each AND gate in the AND gate group 176 is rendered non-conductive, the inputs A ₁ to A ₁₂ of the full adder 82 are all "0". Furthermore, the detection signal SUB・R is supplied to the AND gate 112 in FIG. ₆ via the OR gate 110 in FIG. Generates signal “1”. This output signal “1” is
Full adder 8 via OR gates 114 and 116
2 as a carry input _Ci , the outputs S ₁ to _{S 6} of the full adder 82 are address data indicating the (A _R +1) address (that is, the address next to the storage address of the relative address data). can get. This address data is sent out from the shift register circuit 84 at timing _T1 , and latched by the latch circuit 102 of FIG. 4 at timing _T1 and _φ2 .
As a result, the pitch/note length data next to the relative address data of the main routine portion is read out from the memory 80, and thereafter, the pitch/note length data reading operation is performed in the same manner as before the subroutine jump. Thereafter, when the note length end timing of the final note of the main routine section is reached, the song end data is read out from the memory 80, and the decoder 104
generates a song end detection signal END="1". This detection signal END is passed through the OR gate 110 to the sixth
Since the signal is supplied to AND gate 112 in the figure, the _T7 channel of the time division counter increases its count value by one. Then, based on the address data corresponding to this increase in the count value, the head address data of the next song B is read out from the memory 80 at the timings _T1 and _φ2 . Further, the detection signal END is supplied to a delay (D) circuit 178. This delay circuit 178
consists of a two-phase shift register that takes in input at timing _T6 and sends out at timing _T1 , and its output signal is supplied to AND gate 180 to generate _F4 key detection signal F4 and timing signal _T6.
It is now possible to perform an AND operation. For this reason,
When the timing of the next T ₆ comes, AND gate 18
0 generates an output signal LT="1". This output signal LT is passed through an OR gate 96 to a latch circuit 94.
In response, the latch circuit 94 latches the start address data of the next song B supplied from the memory 80 via the selector 90. The output signal LT is also supplied to the AND gate 182, and in response, the AND gate 182 generates an output signal "1" at timing _T7 . This output signal "1" causes the full adder 82 of FIG. 6 to be reset through the OR gate 152, so that the _T7 channel of the time division counter has a count value of zero. The address data corresponding to this count value of zero is
It is sent from the shift register circuit 84 at the timing of _T1 , and the signal shown in FIG. 4 is sent out at the timing of _T1 and _φ2 .
It is latched by the latch circuit 102 in response to the output signal "1" of the AND gate 98. Also, at this time
The output signal "1" of the AND gate 98 is supplied to the latch circuit 100, and in response, the latch circuit 10
0 latches the start address data of the next song B from the latch circuit 94. Therefore, the tempo data for the next song B is read from the memory 80, and the same performance data reading operation as for song A described above is performed for song B. Then, the performance data reading operation similar to that described above is performed sequentially for songs C, D, etc., and eventually the stop data at the end of the last song is read from the memory 80, and in response to this, the decoder 104 detects a stop. Generates signal STP="1". This detection signal STP is passed through an OR gate 184 to a delay circuit 186 similar to the delay circuit 178 described above.
is supplied to For this reason, flip-flop 10
1 is set at the timing of _T1 following _T6 , and the AND gate 103 is set according to the output Q=“1”.
Output signal “1” is generated at timing _T7 . This output signal "1" causes the full adder 82 of FIG. 6 to be reset through the OR gate 152, so that the _T7 channel of the time division counter becomes a count value of zero and continues in this state thereafter. Therefore, the memory 80
Data reading from is stopped. What has been described above is the performance data reading operation in the case of all-musical performance, and the performance data reading operation in the case of single-music selective performance is as follows. In this case, on the keyboard, press a key other than the _F4 key that corresponds to the desired song. Then, in the circuit shown in Figure 4,
Pitch data KPC corresponding to the pressed key is latched in the latch circuit 86 in response to the initial clear signal IC. Since this pitch data KPC indicates pitches corresponding to keys other than the _F4 key, the _F4 key detection signal F4 of the chord detection circuit 88 is "0".
Selector 90 is in a state where input B is selected. Therefore, the pitch data KPC from the latch circuit 86
is supplied to a latch circuit 94 via a selector 90 and latched therein in response to an initial clear signal IC from an OR gate 96. Also, since the keyless signal NK from the code detection circuit 88 is "0", the chip enable signal CE of the memory 80 is
becomes “1”. Then, when the timing of T ₁ and φ ₂ comes,
In response to the output signal "1" of the AND gate 98, the latch circuit 100 receives pitch data corresponding to the selected song from the latch circuit 94, and the latch circuit 102 receives all bits "0" from the time division counter shown in FIG. ” address data are respectively latched. For this reason, the tempo data of the performance data of the selected song is first read out from the memory 80, and then the pitch, note length data, etc. for each note are read out in the same manner as in the case of song A described above. As this read operation progresses, song end data will eventually be read out from the memory 80, and in response, the song end detection signal will be output from the decoder 104.
END="1" is generated. This detection signal END
In response to this occurrence, the start address data of the next song is read out from the memory 80 as described above, but since the selector 90 is in the input B selection state, this start address data is not supplied to the latch circuit 94. The latch circuit 94 also receives the _F4 key detection signal F
Since AND gate 180 is non-conductive due to 4="0", no latch operation occurs. The detection signal END is supplied to an AND gate 188, and is ANDed with the output of an inverter 190 which receives the _F4 key detection signal F4 as input. At this time, F ₄
Since the key detection signal F4 is "0", the AND gate 188 generates an output signal "1", and this output signal "1" is supplied to the delay circuit 186 via the OR gate 184. Therefore, in the same manner as in the case of stop data reading described above, the channel _T7 of the time division counter in FIG. 6 is brought into a reset state, and subsequent data reading from memory 80 is stopped. Note that when the power is turned on, if no key is pressed on the keyboard, the no-key-pressed signal NK from the code detection circuit 88 becomes "1", so the chip enable signal CE becomes "0", and the memory Data reading from 80 is prohibited. Details of Piano Sound Generation Operation As described above, the time division processing circuit 24 executes the frequency division output generation process (B1) and the envelope data generation process (B2) in a time division manner regarding piano sound generation. Here, the processing timing and output timing in each process (B1) and (B2) are shown in Table 2 below for the above-mentioned timing signals _T0 to _T7 .

[Table] According to this Table 2, it can be seen that the delay in the output timing with respect to the processing timing is the same as in Table 1. In FIG. 6, the full adder 82 and shift register circuit 84 use the portion from the least significant bit to the 7th bit as a 7-bit counter at timing _T5 , and send out a frequency-divided output _DO . At the timing, the portion from the least significant bit to the 9th bit is used as a 9-bit counter, and 8-bit envelope data _D2 to _D9 is sent out. In the frequency division output generation process, the AND gate 19
2 receives the signal of the least significant bit of the frequency division control data DVC from the frequency division control data memory ₃₀ in FIG. It is designed to be input to the shift register SF via the
Furthermore _, in _the AND gate group 196, when _the outputs S ₁ , S _{2 .} . .
_C6 is inputted, and the signals from the 2nd bit to the 7th bit of the frequency division control data DVC are also inputted, and the output signal of each AND gate in the AND gate group 196 is NOR.
The signal is input to gate 198. The latch circuit 200 responds to the output signal "1" of the AND gate 202 at the timing of _T5 and _φ2 .
It latches the output signal of the NOR gate 198, and when the output signal of the NOR gate 198 is "1", the latched signal "1" is sent out. This signal "1" is passed through the AND gate 204 at the timing of _T5 , and then is passed through the OR gate 1.
16 to a full adder 82 as a carry input C _i . Therefore, whether or not a pulse should be input to the full adder 82 is determined by NOR at each timing of _T5 .
It is controlled according to the output signal "1" or "0" of the gate 198. As a result of the above configuration, the counting operation of channel _T5 of the 7-bit counter is controlled according to the frequency division control data DVC, and the counting operation of channel T5 of the 7-bit counter is controlled according to the frequency division control data DVC.
From the th bit, frequency-divided signals D ₅ , D ₆ and D ₇ corresponding to a desired note name (for example, F) are obtained. These frequency-divided signals D ₅ to D ₇ have frequencies 1/2 lower in D ₆ than D _{5 and 1/2 lower in frequency than D 6 , respectively} .
The signal is supplied to the time division output circuit 32 in FIG. Note that when the frequency-divided output DO is viewed as count data at the timing of _T5 , this count data is transferred from the shift register circuit 84 to the circuit shown in FIG.
Supplied at T ₇ timing. In FIG. 7, divided signals D ₅ and D ₆ are provided to selector 206 as inputs A and B, respectively, and divided signals D ₆ and D ₇ are provided to selector 208 as inputs A and B, respectively. The selection operations of the selectors 206 and 208 are controlled in accordance with the selection signal SA consisting of the output signal of the AND gate 210 when the octave code signal OCT and the timing signal _T7 are input. When the octave code signal OCT is "0" (the octave to which the _F2 to _E3 notes belong), the selection signal SA is "0", so the selector 206 selects the divided signal D6, and the selector ₂₀₈ selects the divided signal D6. The frequency signals _D7 are selectively transmitted. AND gate 212 is
An output signal "1" is generated every time the outputs of the selectors 206 and 208 both become "1", and this output signal "1" is passed through a shift register 214 similar to SF in FIG. 6 at the timing of _T0 . Sent out.
In this case, as an example, the frequency-divided signal for pitch name F is
Assuming that D ₅ to D ₇ are generated, a square wave sound source signal TG having a frequency corresponding to the F ₂ sound is obtained from the shift register 214. Also, when the octave code signal OCT is "1" (when it is the octave to which notes _F3 to _E4 belong and when it is note _F4 ), the selection signal SA becomes "1" at every timing of _T7 , so The selector 206 selectively sends out the frequency-divided signal _D5 , and the selector 208 selectively sends out the frequency-divided signal _D6 . The AND gate 212 generates an output signal "1" every time the outputs of the selectors 206 and 208 both become "1", and this output signal "1" is sent out via the shift register 214 at timing _T0 . . In this case, assuming that frequency-divided signals D ₅ to D ₇ are generated for note name F as in the previous example, the shift register 214 outputs a square wave sound source signal having a frequency corresponding to note _F3 .
TG is obtained. Note that for the _F4 note, the value of the frequency division control data DVC is determined so that the frequency of the frequency division signal _D5 is twice that of the note name F.
F ₄ when octave code signal OCT is “1”
A sound source signal TG having a frequency corresponding to the sound is obtained. In the envelope data generation process, in the circuit shown in Figure 6, according to the initial clear signal IC,
AND gate 216 generates an output signal "1" at timing _T6 . This output signal “1” is OR
T ₆ of the 9-bit counter via gate group 194
Set all bits of the channel to “1”. this is,
This is to set the amplitude level of the piano envelope to zero when the power is turned on, thereby prohibiting piano sound. After this, a sound generation enable signal for generating piano sound is generated.
When PKO is generated, this signal PKO rises and is differentiated by the differentiating circuit 218. According to the differential output of this differential circuit 218, the AND gate 220
Generates output signal “1” at timing _T6 .
This output signal "1" is input to the 9th bit shift register of the first stage of the shift register circuit 84 via the 9th bit OR gate in the OR gate group 194, while the output signal of the NOR gate 174 is set to "0" to make each AND gate in the AND gate group 176 non-conductive, thereby setting all bits of the inputs _A1 to _A9 of the full adder 82 to "0". As a result, when the sound generation enable signal PKO rises, the 9th bit becomes "1" in channel _T6 of the 9-bit counter, and all bits from the least significant bit to the 8th bit become "0"; The 8-bit data "00000001" from the 9th bit to the 9th bit is sent through the shift register circuit 84 to envelope data D ₂ to D 2 at timing T ₀ .
_D9 is supplied to the circuit of FIG. At the next timing _T6 , an output signal "0" is sent from the 8th bit shift register of the 8th stage of the shift register circuit 84, and this output signal "0" is used as the frequency switching signal FC as shown in FIG. The signal is supplied to the selector 222. In FIG. 7, a latch circuit 224 outputs envelope data D ₂ to D 2 at timing T ₀ and φ ₂ in response to an output signal of an AND gate 228 which receives a timing signal T 0 from an OR gate 226 and a clock signal φ _{2 .} It latches D ₉ and the sound source signal TG (output of the shift register 214), and when the aforementioned sound enable signal PKO rises, only the most significant bit (corresponding to D ₉ ) is "1" data as 8-bit envelope data. Send out. Since the signal of each bit of this data is input to the NAND gate 230, the NAND gate 230 generates an output signal "1", and this output signal "1" is latched by the latch circuit 232 at the timing _T2 , and the NAND gate 230 generates an output signal "1".
A gate 234 is provided. Therefore, the ADN gate 234 generates an output signal “1” at the timing of T ₆ and φ _A , and this output signal “1” is supplied to the selector 222 as the enable signal EN. When the selector 222 is enabled in response to the enable signal EN, the selector 222 outputs the frequency switching signal FC.
The high-speed clock signal φ _H as input B is selectively sent out in response to the selection signal _SA ="0" consisting of Carry input C _i
Supplied as. Therefore, the count value of the _T6 channel of the 9-bit counter increases at a relatively high speed in response to the high speed clock signal _φH . As the count value continues to increase in this way, an output signal "1" is eventually sent out from the 8th bit shift register of the 8th stage of the shift register circuit 84, and this output signal "1" becomes the frequency switching signal.
The signal is supplied as FC to the selector 222 in FIG. 7.
Therefore, the selector 222 has a selection signal SA of "1".
Then, the low-speed clock signal φ _L as input A is selectively sent out. Therefore, T ₆ for a 9-bit counter
From now on, the channel of φ _L is the low-speed clock signal φ L
The count value increases at a relatively slow speed according to. Then, when all bits from the 2nd bit to the 7th bit of the 9-bit counter become "1", the
Since all eight input bits of the NAND gate 230 become "1", the NAND gate 230 generates an output signal "0", and accordingly, the output signal after T ₂
At the timing of T ₆ and φ _A , the selector 222 becomes disabled. Therefore, an increase in the count value in the _T6 channel of the 9-bit counter is prevented. The individual count data corresponding to the above-mentioned changes in count value in the 9-bit counter are sent to the latch circuit 224 as envelope data _D2 to _D9 .
The signal is supplied to an inverting circuit 236 via an exclusive OR gate, and each bit is inverted by an exclusive OR gate. This inversion process converts the numerical change in the envelope data from the latch circuit 224 from "00000001" to "11111111" to "11111110".
to "00000000",
This corresponds to changing the piano envelope from an inverted shape to an upright shape. In the inverting circuit 236, the timing signal
Signal ₂ is obtained by inverting TC ₂ with inverter 238.
Inversion processing is performed in response to the input from OR gate 240. That is, from the inversion circuit 236, the timing signal TC ₂ is “0” T ₀ ~
Envelope data that has undergone inversion processing is sent out during the period _T3 . The envelope data sent out sequentially in this way rises from the zero level to a predetermined attack level, then falls to a predetermined value according to a relatively steep decay curve, and then continues to a relatively gentle decay curve. Therefore, it expresses a piano envelope that drops to the zero level. Here, the zero level means that the outputs K ₁ to _{K 7} of the inverting circuit 236 are all “0”.
( _D2 to _D8 are all "1"), and the predetermined attack level is the output _K1 of the inverting circuit 236.
This corresponds to the state in which ~ _K7 are all “1” ( _D2 to _D8 are all “0”), and the predetermined value is the output K1 _~ of the inverting circuit.
Only K ₇ of K ₇ corresponds to the state of "0" (only D ₈ of D ₂ to D ₈ is "1"). Also, a relatively steep decay curve is expressed by the count data of the high speed clock signal _φH , and a relatively gentle decay curve is expressed by the count data of the low speed clock signal _φL . The AND gate 242 inputs the output signal of the NAND gate 230, the sound source signal TG, and the output signal ₂ of the inverter 238, and is used to input the output signal of the NAND gate 230, the sound source signal TG _, and the output signal ₂ of the inverter ₂₃₈ . The sound source signal TG is transmitted during the period. This sound source signal TG is supplied to an AND gate 246 via an OR gate 244. The shifter circuit 248 performs bit shift processing in response to control inputs A, B, and C to enable D/A conversion processing to be described later with a small number of bits.If control input A is "1", the inverting circuit is activated. 23
6 outputs K ₃ to K ₈ are sent out, and control input B is “1”
If so, send out the outputs K ₂ to _{K 7} of the inverting circuit 236,
If the control input C is “1”, the output of the inverting circuit 236
It is designed to send out K ₁ to K ₆ . During the piano sound generation process, the signal D ₉ is always "1" as described above, so the output of the inverting circuit 236 is
_K8 is always "0", and the control input A consisting of this output _K8 is "0". Therefore, the shifter circuit 248 performs a shift process according to the control inputs B and C. In the circuit for forming the control input B,
AND gate 288 connects the output K ₈ of inverting circuit 236 to
The output of the inverter 290 that inverts the output, the output _K7 of the inversion circuit 236, and the timing signal _TC0 are input, and the second most significant bit _K7 is "1".
(the amplitude level is relatively high) and generates an output signal "1" at two timings, T1 _{and T3} , during the period _T0 to _T3 . These output signals “1” are input to the shifter circuit 248 as control input B.
and in response, the shifter circuit 248
During the period _T0 to _T3 , 6-bit data _K2 to _K7 is sent twice as envelope data EV. Furthermore, in the circuit for forming the control input C, the AND gate 292 receives as inputs the output of the inverter 290, the output of the inverter 294 that inverts the output _K7 , and the timing signals _TC0 and _TC1 . , detects that the second most significant bit _K7 is “0” (amplitude level is relatively low).
During the period from T ₀ to T ₃ , an output signal “1” is generated at the timing of T ₃ . This output signal "1" is supplied to the shifter circuit 248 as a control input C, and in response, the shifter circuit 248 converts the 6-bit data _K1 to _K6 as envelope data EV during the period _T0 to _T3 . Send once. The OR gate 296 outputs the output K ₈ of the inverting circuit 236.
, the output of AND gate 288, and AND gate 2
92 output, and when K ₇ = “1” is detected during the period T ₀ to T ₃ , T ₁
The output signal “1” is generated twice at the timing of T 3 and T ₃ , and when K ₇ = “0” is detected, the output signal “1” is generated at the timing of T ₃ . In this way, the output signal "1" generated from OR gate 296 makes AND gate 246 conductive, so that
The sound source signal TG from the OR gate 244 is T ₀ to _{T 3}
During this period, the AND gate 246 sends out twice or once in synchronization with the above-mentioned envelope data sending. Sound source signal TG from AND gate 246 and envelope data EV from shifter circuit 248
is supplied to the D/A conversion circuit 36 in FIG. The D/A conversion circuit 36 includes a first decoder 298 that decodes the upper 2 bits of 6-bit input data (EV or AM), and a second decoder 30 that decodes the remaining 4 bits of the input data.
0, and the analog voltage generation circuit 3 that constitutes a D/A converter together with these decoders 298 and 300.
02, a power supply circuit 304 that supplies a power supply voltage according to the control input (TG or SG) to this analog voltage generation circuit 302, and an analog voltage generation circuit 302.
The pulse width of the output voltage of the clock signals φ ₁ and φ ₂
A pulse width regulation circuit 306 _regulates the voltage output from this pulse width regulation circuit 306 according to
A buffer amplifier 308 is provided for deriving the . Of the 6-bit envelope data EV, the upper 2 bits including the most significant bit (MSB) are input to the decoder 298, and the remaining 4 bits are input to the decoder 300. Decoder 29
The four output lines of No. 8 are connected to the control input terminals of four gate elements GA ₁ to GA ₄ in the analog voltage generation circuit 302, respectively. In the analog voltage generation circuit 302, four gate element groups G ₁ to G ₄ each including 16 gate elements are provided,
The 16 output lines of the decoder 300 are connected to the control inputs of 16 gate elements for each gate element group. The analog voltage generation circuit 302 has first and second
power supply lines PS ₁ and PS ₂ , and the resistance values between these power lines are approximately equal to each other.
64 resistors R1 to R64 are connected in series.
The 16 gate elements of gate element group _G1 are resistors R1
The 16 gate elements of _the gate element group _G2 are connected between one end of each of the resistors R17 to R32 and the gate element GA ₂ . The 16 gate elements of group _G3 are connected to one end of each of resistors R33 to R48 and the gate element.
The 16 gate elements of the gate element group _G4 are connected between one end _of each of the resistors R49 to R64 and the gate element GA ₄ , and the gate elements GA ₁ to _{GA 4} are An analog voltage corresponding to input data is sent to an output point M. In the power supply circuit 304, a resistor R ₀ and resistors R _A and R _B having substantially equal resistance values are connected in series between the voltage source +V and a reference potential point (ground _point ). An intermediate voltage V _C taken from the interconnection point of R _B is supplied to the power supply line PS ₁ . A gate element _GH is connected between the interconnection point of the resistors R ₀ and R _A and the power line PS ₂ , and a gate element _GL is connected between the reference potential point and the power line PS ₂ . The control input terminal of the gate element _GL is supplied with the sound source signal TG or the sign bit signal SG, and the control input terminal of the gate element _GH is supplied with the sound source signal TG or the sign bit signal SG.
is supplied via the inverter IN. Therefore, if the control input (TG or SG) is "1", the gate element G _L is connected to the power supply line PS ₂ .
A voltage V _L lower than the intermediate voltage V _C is supplied via
If the control input is "0", a voltage _VH higher than the intermediate voltage _VC is supplied via the gate element _GH . In this way, the supply voltage to power line PS ₂ is set to V _L or V _H
By switching to the envelope data EV
During D/A conversion, it becomes possible to add an envelope according to the envelope data to the sound source signal TG, and the D/A of amplitude data AM, which will be described later, becomes possible.
During conversion, it is possible to determine the direction of amplitude according to the sign bit signal SG. Pulse width regulating circuit 306 includes gate elements G ₁₁ and G ₁₂ that receive clock signals _{φ 1} and φ ₂ at their control inputs, respectively _. Point M
and the interconnection point N of the resistors R _A and R _B of the power supply circuit 304, and the buffer amplifier 308 is connected from the interconnection point N of the gate elements _G11 and _G12 .
The voltage output V _OUT is taken out through the . There is a possibility that an analog voltage (a voltage that swings from V _C to V _H side or V _L side) is generated at output point M every period corresponding to one pulse of a timing signal such as T ₀ to T ₇ . However, the pulse width regulation circuit 30
6, the analog voltage at output point M is sent out at the timing of φ ₁ , and the intermediate voltage V _C is sent out at the timing of φ ₂ , thereby regulating the width of the output pulse to half that at output point M. It is something. The reason why such a pulse width regulation circuit 306 is provided is that the 8-bit input data _K1 to _K8 are not directly D/A converted, but are converted into 6-bit data (EV/AM) to simplify the configuration and processing. ) and then performs D/A conversion. That is, in FIG. 7, when 6-bit data is extracted via the shifter circuit 248, data K ₁ to
With respect to _K6 , data _K2 to _K7 are shifted by 1 bit, and data _K3 to _K8 are shifted by 2 bits, so the value of data _K2 to _K7 is 1/2. , and the value of data K ₃ to K ₈ becomes 1/4.
Therefore, in the D/A conversion circuit shown in Fig. 8, the data
It is necessary to D/A convert data K ₂ to _{K 7} so that the amplitude level is doubled, and data K ₃ to _{K 8} so that the amplitude level is quadrupled. The data from the circuit in Figure 7 is
The same data is generated twice for K ₂ to _{K 7} and four times for data K ₃ to _{K 8} , and the pulse width regulation circuit 306 in FIG. 8 generates the same data 2 times.
The same analog voltage is sent out as two pulses corresponding to each time, and the same analog voltage is sent out as four pulses corresponding to the same data four times. When such a D/A conversion operation is illustrated for piano sound generation, it is as shown in FIGS. 9a to 9d. FIG. 9a shows the sound source signal TG as a continuous waveform for convenience, and FIG. 9b shows the sound source signal to which a piano envelope has been added as a continuous waveform for convenience. Further, c in the same figure is a macroscopic view of the signal in b, and d in the same figure is a microscopic view of a part of the signal in c, which is actually the output point N of the pulse width regulation circuit 306. This corresponds to the signal waveform obtained from At the rise of the piano envelope, an analog voltage corresponding to the attack level appears at the output point M, but this analog voltage is as shown in Fig. 9a,
As shown in b, if the sound source signal TG is "1", the voltage is shifted toward the V _L side, and if the sound source signal TG is "0", the voltage is shifted toward the V _H side. Looking at this at the output point N, as shown in Figure 9d, the voltage that swings to the V _L side or to the V _H side is T 1 and T ₁ during the period from T ₀ to _{T 3} .
It is sent out as two pulses at timing _T3 . Then, when the amplitude level of the piano envelope falls below the level at which the second most significant bit _K7 mentioned above becomes "0", the number of pulses sent during the period _T0 to _T3 is one at the timing of _T3 . Only. As a result of the above, a sound source signal with a piano envelope added as shown in FIG. 9b to d is obtained as a voltage output V _OUT from the buffer amplifier 308, and this sound source signal is sent to the output amplifier with or without a low-pass filter. The signal is supplied to the speaker 40 via 38, and is produced as a piano sound. In this case, high frequency components based on time division processing and clock signals φ ₁ and φ ₂ are removed by the low-pass filter or speaker 40, and the piano sound produced by the speaker 40 is substantially the same as shown in FIG. 9b. This is a piano sound signal. This piano sound signal has a relatively high amplitude level at the attack level and its vicinity, _T0 ~
Since two pulses are included in the period T ₃ , pulse 1
The energy is doubled and the sound intensity is also doubled compared to the case of individual pieces. Therefore, the amplitude drop caused by the bit shift is recovered. Details of scale sound generation operation Regarding scale sound generation, the time division processing circuit 24 performs address data generation processing (C1), step width data formation processing (C2), and predicted value data generation processing (C3).
As described above, the process is executed in a time-sharing manner. Here, the processing timing and output timing in each process (C1) to (C3) are shown in Table 3 below for the timing signals T ₀ to _{T 7} described above.

[Table] According to Table 3, it can be seen that the delay in output timing with respect to processing timing is the same as in Table 1. The step width data formed in the process C2 is provided to the predicted value data generation process C3 at timing _T2 , and is sent to the time division processing circuit 2.
It is never output from 4. In FIG. 6, full adder 82 and shift register circuit 84 are used as a 12-bit address counter at timing _T3 to send out address data _D1 to _D12 for reading audio data. Further, the full adder 82 is used to perform addition or subtraction processing at timings _T1 and _T2 . In FIG. 4, a differentiating circuit 310 differentiates the sound generation enable signal DKO for generating scale notes at the rising edge and generates a differentiated output. This differential output is R-S
Since the flip-flop 312 is set, the output of the flip-flop 312 becomes "0".
This output is passed through the shift register 314.
Provided to AND gate 316. Since the AND gate 316 is supplied with the timing signals T ₁ , T ₂ , and T ₃ from the OR gate 318, the AND gate 316 generates the output signal “0” at the timing of T ₁ , T ₂ , and T ₃ , respectively. , these output signals "0" are sequentially supplied to the full adder 82 of FIG. 6 via the OR gate 152. Therefore, the full adder 82 is reset and released at timings T ₁ , T ₂ , and T ₃ . The _T3 channel of the address counter starts counting after being reset in this way. That is, the AND gate 320 generates an output signal "1" at timing T ₃ in response to the timing signal sum φ _A +φ _B , and this output signal is sent to the carry input C to the full adder 82 via the OR gates 114 and 116. Since the _T3 channel of the address counter increments its count value each time it receives _{a carry input C i .} Then, the count data based on such counting operation is transferred from the shift register circuit 84 to address data _D1 at timing _T5 .
~ _D12 to the latch circuit 322 of FIG. The latch circuit 322 uses a timing signal
The latch operation is performed in response to the output signal of the AND gate 324 which receives _T5 and the clock signal _φ2 as input, and latches address data at each timing of T5 _{and φ2} . The audio data memory 326 is, for example, a ROM.
As mentioned above, this consists of F ₂ ~
Audio data (serial data) corresponding to the 15th note of _F4 is stored. Audio data memory 3
26, audio data for the 15th scale note is read out in parallel in accordance with the address data from the latch circuit 322, and moreover in bit serial format for each note, and is supplied to the selector 328. The decoder 330 receives pitch data KPC or MPC.
The decoded output is supplied to the selector 328. The selector 328 selects the audio data corresponding to the scale name indicated by the output of the decoder 330 from among the data read from the memory 326. The selected audio data is supplied to the latch circuit 332, and the selected audio data is supplied to the latch circuit 332 at the timing of _T5 . It is latched with. The audio data in bit serial format from the latch circuit 332 is supplied to a triple consecutive detection circuit 334.
Input to delay circuit 336 and exclusive
It is input to one input terminal of OR gate 338.
The delay circuit 336 consists of a two-phase shift register that takes in an input at timing T ₂₂ and sends it out at timing T ₅ , and its output signal is exclusive.
It is adapted to be supplied to the other input terminal of OR gate 338. Therefore, exclusive OR gate 3
38 generates an output signal "0" when both consecutive 2-bit signals are "0" or "1", and otherwise outputs an output signal "1". The output signal of exclusive OR gate 338 is provided to one input of OR gate 340 and is also provided to delay circuit 342 . Delay circuit 3
42 is similar to the delay circuit 336 described above, and its output signal is supplied to the other input terminal of the OR gate 340. For this reason,
The OR gate 340 operates when the output signal of the exclusive OR gate 338 is "0" and the output signal of the delay circuit 342 is "0", that is, all consecutive 3-bit signals are "0" or "1". The output signal "0" is generated when the output signal is 0, and the output signal "1" is output otherwise. The reason why such three consecutive detection circuits 334 are provided is that the step width can be changed and controlled according to the signal state of the audio data (the step width is increased when three bits of "0" or "1" continue). This is to make it happen. AND gate 344 connects timing signals T ₁ and φ _A
+φ _B is input, and its output signal is sent out as the timing signal TM1, and the OR
It is sent out via gate 346 as output signal SO1. Furthermore, the AND gate 348 sends out the output signal from the three consecutive detection circuit 334 at the timing of T ₁ and φ _A +φ _B according to the output signal of the AND gate 344 , and this output signal is sent to the OR gate 35 .
0 as output signal SO2. AND gate 352 connects timing signals T ₂ and φ _A
+φ _B is input, and its output signal is sent out at timing TM2. Furthermore, the AND gate 354 operates the latch circuit 3 at the timing of T ₂ and φ _A +φ _B according to the output signal of the AND gate 352 .
32, and this audio data is sent to the OR gate 34.
6 as output signal SO1, while
It is sent out via OR gate 350 as output signal SO2. Then, the timing signal TM1 and
TM2 and output signals SO1 and SO2 are supplied to the circuit of FIG. The circuit shown in FIG. 6 performs step width data formation processing at timing _T1 . This process is
This is done based on the signals TM1, SO1 and SO2 from FIG. In this case, the signals TM1 and
Both SO1 consist of the output signal T ₁ ·(φ A +φ _B ) of the AND gate 344 in FIG. 10, and the signal SO2
consists of the output signals of the three consecutive detection circuits 334 in FIG. Step width calculation is generally performed as shown in (A) and (B) below. (A) When “0” or “1” continues in serial audio data (amplitude change is large) Δ _t = Δ _t-1 + Δ _nax −Δ _t-1 /n ...(1) (B) Above ( Cases other than A) Δ _t = Δ _t-1 − Δ _t-1 /n (2) In these equations (1) and (2), Δ _t is the step width to be found this time, and Δ _t-1 is The previously determined step width, _Δnax , is the maximum value of the step width, and n is a power constant that determines the rate of change of the step width and is a time constant in units of sampling periods. In this embodiment, if there are three consecutive 0's or 1's, an operation equivalent to the above equation (1) transformed into the following equation (3) is performed; otherwise, , an operation (two's complement addition) corresponding to the above equation (2) transformed into the following equation (4) is performed. Δ _t = Δ _t-1 + (Δ _t-1 )/n...(3) Δ _t = Δ _t-1 + (Δ _t-1 )/n+1...(4) In Figure 6, T ₁ and At the timing of φ _A +φ _B , all six selectors in the selector group 356 are in a state of selecting input B in response to the selection signal b composed of the timing signal TM1. Therefore, the upper 6 bits of the previous step width data from the 8th stage of the shift register circuit 84 (corresponding to S ₇ to S ₁₂ ) are sent to the selector group 356.
is supplied to exclusive OR gate group 358 via
Inversion processing is performed in response to signal SO1="1". The 6-bit data (data that has undergone inversion processing) from the exclusive OR gate group 358 is input to the full adder 82 via the OR gate group 168 B ₁ to _{B 6}
Supplied as. At this time, the previous step width data from the eighth stage of the shift register circuit 84 is supplied as inputs A ₁ to _{A 12} of the full adder 82 . In such a state, if the three consecutive detection circuit 334 in FIG. Carry input C _i
and inputs _B7 to _B12 are all "0". Therefore, the calculation of equation (3) above is executed. Also, assuming that the above three consecutive sequences are not detected,
The signal SO2 is "1", and this signal "1" is input to the full adder 82 as a carry input C _i via OR gates 114 and 116, and also as an input
Input as B ₇ to B ₁₂ . For this reason, (4) above
The expression's operation is performed. Regarding equations (3) and (4) above, the constant n is 6 bits downward from the upper 6 bits.
Since it is bit shifted, it becomes ²⁶ . According to such a calculation, when three consecutive detections occur (when the amplitude rapidly decreases or increases), the step width becomes larger, but the step width becomes “0”.
When "1" and "1" continue alternately (when the amplitude change is gradual), the step width becomes small, and the followability of the predicted signal to the original sound signal is improved. At the timing of T ₂ , in the circuit of Fig. 6,
Predicted value data generation processing is performed. This process consists of the signals TM2, SO1 and SO2 from FIG.
It is carried out based on. In this case, the signal TM2 is the output signal _T2 of the AND gate 352 in FIG.
(φ _A +φ _B ), and the signals SO1 and SO2 both consist of serial audio data from the AND gate 354. The predicted value calculation is performed according to the following formula (5) if the signals SO1 and SO2 (serial audio data) are "0", and is performed according to the following formula (6) if they are "1". . S _t = S _t-1 +Δ _t-1 ...(5) S _t = S _t-1 −Δ _t-1 = S _t-1 + ( _t-1 )+1 ...(6) Here, S _t is the predicted value to be obtained this time, S _t-1 is the predicted value obtained last time, and Δ _t-1 is the step width obtained last time. In FIG. 6, at timings T ₂ and φ _A +φ _B , all six selectors in selector group 356 are in a state of selecting input A in response to selection signal a consisting of timing signal TM2. Now, assuming that the signals SO1 and SO2 are both "0", the upper 6 bits of the previous step width data from the first stage of the shift register circuit 84 (corresponding to _S7 to _S12 ) are sent to the selector. Input B ₁ to full adder 82 via group 356, exclusive OR gate group 358, and OR gate group 168.
Supplied as _B6 . At this time, the full adder 82
As inputs _A1 to _A12 , the shift register circuit 8
The previous predicted value data is supplied from the 8th stage of 4. In addition, in the exclusive OR gate group 358,
Since the signal SO1 is "0", no inversion processing is performed. Further, the carry input C _i and inputs B ₇ to B ₁₂ of the full adder 82 are both “0” because the signal SO2 is “0”. Therefore, the calculation of equation (5) above is executed. Furthermore, if the signals SO1 and SO2 are both "1", the upper 6 bits of the previous step width data from the first stage of the shift register circuit 84 (corresponding to _S7 to _S12 ) are sent to the selector. Input B ₁ to full adder 82 via group 356, exclusive OR gate group 358, and OR gate group 168.
Supplied as _B6 . At this time, since the signal SO2 is "1" in the exclusive OR gate group 358, inversion processing is performed. In addition, the carry input C _i and inputs B ₇ to B ₁₂ of the full adder 82 have a signal SO2="1".
Both become "1" depending on the . Furthermore, the previous predicted value data is supplied from the eighth stage of the shift register circuit 84 as inputs A ₁ to _{A 12} of the full adder 82 . Therefore, the calculation (two's complement addition) of equation (6) above is executed. Note that AND gate A ₀ , OR gates O ₁ and O ₂ ,
Inverter I is provided to set the minimum value of the step width. Upper 5 bits of 6-bit step width data (corresponds to _S8 to _S12 )
are both “0”, the output signal of OR gate _O1 becomes “0”, and this output signal “0” is
AND gate A ₀ is made non-conductive, and the signal is converted to “1” by inverter I, and OR gate O ₂
is supplied to Therefore, at this time, selector group 3
The step width data sent through the step width data 56 is "010000" when the left end is indicated as the least significant bit. Based on the arithmetic processing of the step width and predicted value as described above, the shift register circuit 84 sends out 9-bit predicted value data _D2 to _D10 for each sample point at timing _T4 , as shown in FIG. Supplied to the circuit. In the circuit shown in FIG. 7, predicted value data D ₂ to _{D 10}
is the latch circuit 224 at the timing of _T4 and _φ2 .
is latched to. This latched data is 2's complement code data, and the bit corresponding to _D10 is the sign bit. This sign bit signal SG is supplied to an AND gate 360,
It is ANDed with the timing signal _TC2 . The AND gate 360 becomes conductive during the period from _T4 to _T7 when the timing signal _TC2 takes the "1" level, and sends out the sign bit signal SG. This sign bit signal SG is
It is fed through an OR gate 244 to an AND gate 246 . Further, the sign bit signal SG from the AND gate 360 is sent to the inverting circuit 23 via the OR gate 240.
6 and is used to control the code conversion process. That is, when the sign bit signal SG is "0", the inverting circuit 236 outputs the latch circuit 2.
8-bit data from 24 (corresponds to D ₂ to _{D 9} )
Send as is. On the other hand, the sign bit signal
When SG is "1", the inversion circuit 236 inverts the 8-bit data from the latch circuit 224 and sends it out. As a result, 8-bit data K ₁ to K ₈ are sent out from the inversion circuit 236 and supplied to the shifter circuit 248 . The shifter circuit 248 performs data transmission operations in different ways depending on which of the control inputs A, B, and C is set to "1", as described above regarding piano sound generation, and this shifter circuit 248
The data transmission from the AND gate 246 is performed in synchronization with the transmission of the sign bit signal SG from the AND gate 246. The control input A becomes "1" when the output K ₈ (most significant bit) of the inverting circuit 236 becomes "1". When the control input A becomes "1" in this way, the shifter circuit 248 becomes "1". Output K ₃ of circuit 236 ~
The 6-bit data consisting of _K8 continues to be sent out as amplitude data AM during the period from _T4 to _T7 . Furthermore, since the output K ₈ =“1” makes the AND gate 246 conductive via the OR gate 296, the AND gate 24
6 is the sign bit signal SG from the OR gate 244
continues to be sent during the period from T ₄ to _{T 7} . Control input B consists of the output signal of AND gate 288, which output signal _K8 is "0".
and the output _K7 is “1”, the timing signal
In response to TC ₀ , it becomes “1” at timings T ₅ and T ₇ . Therefore, based on the control input B="1", the shifter circuit 248 sends 6-bit data _K2 to _K7 at two timings, _T5 and _T7 , during the period _T4 to _T7 . Sent as amplitude data AM. Further, since the output signal "1" of the AND gate 288 makes the AND gate 246 conductive via the OR gate 296, the sign bit signal SG from the OR gate 244 is transmitted from the AND gate 246 to the signal "1" during the period _T4 to _T7 . It is sent at two timings: ₅ and T ₇ . Control input C consists of the output signal of AND gate 292, which output signal is connected to outputs K ₇ and K ₈
When both are “0”, the timing signals TC ₀ and TC ₁
It becomes “1” at the timing of T ₇ according to . Therefore, from the shifter circuit 248, the control input C=
Based on “1”, 6-bit data of K ₁ to _{K 6} is
Amplitude data at timing T ₇ during period T ₄ to T ₇
Sent as AM. Also, AND gate 29
The output signal of 2 causes AND gate 246 to conduct through OR gate 296, so that AND gate 24
From 6 onwards, the sign bit signal SG from the OR gate 244 is sent out at timing _T7 during the period from _T4 to _T7 . The 6-bit amplitude data AM and sign bit signal SG for each sample point sent in any of the above-mentioned modes are supplied to the circuit shown in FIG. In the circuit shown in FIG. 8, the upper two bits of the amplitude data AM are sent to the first decoder 298.
Then, the remaining 4-bit signal is sent to the second decoder 300.
The sign bit signal SG is supplied directly to the gate element _GL and as a control input to the gate element _GH via the inverter IV. Therefore, an analog voltage corresponding to the input amplitude data AM is generated at the output point M of the analog voltage generation circuit 302. The analog voltage generated in this way is connected to the sign bit signal SG as illustrated in FIG.
If is “0”, the intermediate voltage V _C swings to the positive side like V _H1 and V _H2 , and the sign bit signal SG becomes “1”.
Then, the intermediate voltage V _C swings to the negative side like V _L1 and V _L2 . In addition, in FIG. 11, W _A is the voltage V _H1 , V _H2 , . . . that is sequentially sent out from the output point M.
The predicted signal consisting of V _L1 , V _L2 . . . is shown as an analog signal waveform. The analog voltage at the output point M is converted into one, two, or four pulses depending on the output timing by the pulse width regulation circuit 306. In this case, the pulse conversion operation is performed by using the clock signals _φ1 and _φ2 to convert the gate elements _G11 and
T ₄ to T ₇ in Figure 9d, which alternately switches to G ₁₂ .
If analog voltage is generated from output point M at timing _T7 during period, one pulse is generated at _T5 and
When generated at the 2nd timing of T ₇ , 2 pulses are generated, and when generated at the 4th timing of T ₄ , T ₅ , T ₆ , and T ₇ , 4 pulses are generated. . That is, in FIG. 11, the analog voltage below level L ₁ (corresponding to data K ₁ to K ₆ in FIG. 7) becomes 1 at timing T ₇ .
analog voltage above level _L1 and below level _L2 (data in Figure 7).
The analog voltage above level L ₂ (corresponding to _data K ₃ to _{K 8 in} Figure 7) is sent out as two pulses at two timings, T ₅ and T ₇ . is sent out as four pulses at four timings: T ₄ , T ₅ , T ₆ and T ₇ . As a result of the above, from the pulse width regulation circuit 306,
For example, a prediction signal corresponding to the scale name "do", which is composed of a pulse train that swings positive and negative with respect to the intermediate voltage V _C , is obtained. This predicted signal is supplied to the speaker 40 via the buffer amplifier 308, the output amplifier 38 in FIG. 1, etc. in the same manner as described above regarding piano sound generation, and is produced as a scale note. in this case,
In the prediction signal, the sound intensity will be doubled where the period T ₄ to T ₇ includes two pulses, and the sound intensity will be quadrupled where the prediction signal includes 4 pulses during the period T ₄ to _{T 7} . , the amplitude drop caused by the bit shift is recovered. In addition, in FIG. 6, the output of the full adder 82
When S ₁₂ becomes “1” at the timing of T ₃ , AND
Gate 362 generates an output signal "1". This output signal “1” is used as the read completion signal SRE.
It is supplied to the circuit shown and causes flip-flop 312 to be reset via shift register 364. Therefore, the output of the flip-flop 312 becomes "1", and this output is transferred to the shift register 31.
4 to AND gate 316. Then, the AND gate 316 sequentially generates an output signal "1" according to the timing signals T ₁ , T ₂ , T ₃ from the OR gate 318, and these signals "1"
It is supplied to full adder 82 via OR gate 152 as reset signal RST. As a result, the full adder 82 is reset in sequence at timings T ₁ , T ₂ , and T ₃ after transmitting the address data indicating the final read address for the audio data memory 326 in FIG. Therefore, the scale note generation operation for the first scale note is completed. After this, the scale tone generating operation as described above is performed every time the sound generation enabling signal DKO for generating scale notes is generated. [Effects of the Invention] As described above, according to the present invention, when digital waveform data is D/A converted, the number of bits of the digital waveform data is limited and the data input period is controlled according to the amplitude level. Therefore, it is possible to use a D/A converter with a small number of bits and a simple structure, and it is possible to recover the amplitude drop caused by the limitation of the number of bits. Furthermore, as shown in the example, when envelope data or sound waveform data is D/A converted in a device that generates sounds such as musical instrument sounds and human voice sounds, the performance is almost as good as that of the conventional case where the number of bits is not limited. You can get good sound quality.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an electronic musical instrument according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a timing signal generation circuit, and FIG. 3 is a time chart showing various timing signals. Figure 4 is
Circuit diagram of performance data generation circuit, Figure 5 a and b
is a format diagram of performance data, FIG. 6 is a circuit diagram of a time division processing circuit, FIG. 7 is a circuit diagram of a time division output circuit, FIG. 8 is a circuit diagram of a D/A conversion circuit, and FIG. 9 is a circuit diagram of a time division output circuit. Figures a to d show D/D related to piano sound generation.
Signal waveform diagram for explaining A conversion operation, No. 10
FIG. 11 is a circuit diagram of the audio data generation circuit, and FIG. 11 is a signal waveform diagram for explaining the D/A conversion operation regarding scale tone generation. 32...Time division output circuit, 36...D/A conversion circuit, 224...Latch circuit, 248...Shifter circuit, 288, 292...AND gate.

Claims (1)

[Scope of Claims] 1 (a) input means for sequentially inputting digital waveform data representing a desired waveform in bit parallel format; (b) detecting the amplitude level of the waveform based on the digital waveform data; a level detection means for generating an output signal when the amplitude level reaches a predetermined level; (c) each time the digital waveform data is input, the input data is converted into a number n of bits that is smaller than the number of bits m at the time of input and is transmitted; The bit number limiting means transmits the input data from the least significant bit to the nth bit for a predetermined period when the output signal is not generated, and transmits the input data from the least significant bit when the output signal is generated. (m-n) bits are truncated from the bits, and the remaining n bits are transmitted for a period twice ^(mn) times the predetermined period; and (d) an n-bit digital waveform sequentially transmitted from the bit number limiting means. A D/A converter equipped with a D/A converter that exchanges data D/A and sends out an analog output signal. 2. In the D/A converter according to claim 1, the digital waveform data inputted from the input means represents the envelope of the musical tone, and the D/A converter is configured to convert the envelope of the musical tone. A D/A receiving a sound source signal having a frequency corresponding to a pitch as a control input, and transmitting a musical tone signal in the form of adding the envelope to the sound source signal as the analog output signal. conversion device. 3. In the D/A converter according to claim 1, the digital waveform data inputted from the input means represents an amplitude value of a sound waveform, and the D/A converter A sign bit signal representing the sign of the amplitude value of the sound waveform is received as a control input, and a sound signal in which a sign is given to the amplitude value of the sound waveform according to the sign bit signal is sent out as the analog output signal. A D/A conversion device characterized by: