JPS60253285A - Manufacture of semiconductor surface light-emitting element - Google Patents

Manufacture of semiconductor surface light-emitting element

Info

Publication number
JPS60253285A
JPS60253285A JP59109253A JP10925384A JPS60253285A JP S60253285 A JPS60253285 A JP S60253285A JP 59109253 A JP59109253 A JP 59109253A JP 10925384 A JP10925384 A JP 10925384A JP S60253285 A JPS60253285 A JP S60253285A
Authority
JP
Japan
Prior art keywords
layer
substrate
gaas
current confinement
epitaxial growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59109253A
Other languages
Japanese (ja)
Inventor
Tomoyuki Yamada
山田 朋幸
Kazuya Sano
一也 佐野
Akira Watanabe
彰 渡辺
Yoshio Kawai
義雄 川井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP59109253A priority Critical patent/JPS60253285A/en
Publication of JPS60253285A publication Critical patent/JPS60253285A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To manufacture a semiconductor surface light-emitting element having a high output and long life easily without using diffusion and a boring process by forming high reflection multilayer films on the substrate side of a light-emitting element and shaping an internal current constriction layer onto the multilayer films on liquid-phase epitaxial growth. CONSTITUTION:First and second reflecting layers 2a, 2b are laminated alternately onto the substrate surface 1a of a P-GaAs substrate 1 to form high reflection multilayer films 2, and a P type GaAs layer 3 is grown on the multilayer films 2. One part of the P-GaAs layer 3 is etched to shape a columnar projecting section 3b. An N-AlzGa1-zAs layer is grown onto an exposed surface 2c and the projecting section 3b as a current constriction layer 4 while the surface 4a thereof is flattened. The layer 4 is melted back up to approximately the same position as the interface between the multilayer films 2 and the constriction layer 4 to shape a hole 5. A P-AlyGa1-yAs layer is grown onto the substrate with the current constriction layer 4 with the hole as a first clad layer 6. An active layer 7 is formed as an AlxGa1-xAs layer, and a second clad layer 8 consisting of an N-AlyGa1-yAs layer and a contact layer 9 composed of an N-GaAs layer are grown onto the layer 7 in succession, thus obtaining double hetero-structure.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明は光通信又は情報処理用の半導体面発光素子の
製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor surface emitting device for optical communication or information processing.

(従来の技術) 従来AQGaAs半導体面発光素子としてバラス構造の
ものが知られている(例えば、C,A、Burrus 
etal rApplied Physic Lett
er J (1870) WOl、1?、P97)。第
3図はこの面発光素子の一例を示す断面図であって、こ
の素子の製造方法は、n型GaAs基板21上に、液相
エピタキシャル成長により、711QヲGa 7−yA
s層からなるn型筒−クラッド層22゜AQ xGa 
t−yAs層からなるp型活性層23、AQyGaz−
yAs層からなるP型筒二りラッド層24、GaAs層
からなるn型電流狭窄層25を順次に形成した後、電流
注入領域の形成のために電流狭窄層25の表面からこの
層25を経てn型クラッド層24に達する円形状のp+
拡散領域26を形成し、さらに、光りを取り出すため、
このp+拡散領域26の直下に位置する基板21の部分
をn型クラッド層22に達するまで円形状の光取り出し
穴27を掘り、然る後、p側電極28及びn側電極28
を形成していた。
(Prior Art) Conventionally, AQGaAs semiconductor surface emitting devices having a burr structure are known (for example, C, A, Burrus).
etal rApplied Physics Lett
er J (1870) WOl, 1? , P97). FIG. 3 is a cross-sectional view showing an example of this surface emitting device, and the manufacturing method for this device is to use liquid phase epitaxial growth of 711Q to Ga7-yA on an n-type GaAs substrate 21.
N-type tube consisting of s layer - cladding layer 22゜AQ xGa
P-type active layer 23 consisting of t-yAs layer, AQyGaz-
After sequentially forming a P-type cylindrical rad layer 24 made of a yAs layer and an n-type current confinement layer 25 made of a GaAs layer, a layer is formed from the surface of the current confinement layer 25 through this layer 25 in order to form a current injection region. Circular p+ reaching the n-type cladding layer 24
In order to form the diffusion region 26 and further take out the light,
A circular light extraction hole 27 is dug in the part of the substrate 21 located directly under this p+ diffusion region 26 until it reaches the n-type cladding layer 22, and then the p-side electrode 28 and the n-side electrode 28 are
was forming.

(発明が解決しようとする問題点) しかしながら、この従来の製造方法では、図に示すよう
に、液相エピタキシャル成長後であって電極形成前に、
電流集中を行わせるための拡散工程や、光取り出し穴2
7の形成工程が必要であり、これら工程は素子の特性の
劣化の一因となっていた。
(Problems to be Solved by the Invention) However, in this conventional manufacturing method, as shown in the figure, after liquid phase epitaxial growth and before electrode formation,
Diffusion process for current concentration and light extraction hole 2
7 formation steps are required, and these steps contribute to the deterioration of the characteristics of the device.

さらに、この光取り出し穴27とp″″拡散領域26と
の位置合わせが困難であることや、拡散の深さが素子の
特性を決定するため、この深さを精密に制御することが
必要である等の理由から製造工程が複雑かつ困難であっ
た。
Furthermore, it is difficult to align the light extraction hole 27 and the p'' diffusion region 26, and the depth of diffusion determines the characteristics of the element, so it is necessary to precisely control this depth. The manufacturing process was complicated and difficult for several reasons.

さらに、活性層23の近くにハンダ材のような融材を用
いてマウントしているので、これが素子の信頼性を低下
すると共に、素子を短寿命化する一因となっていた。
Furthermore, since the active layer 23 is mounted using a fusing material such as solder, this reduces the reliability of the device and contributes to shortening the life of the device.

さらに、この従来構造では活性層から基板とは反対側に
向う光は電流狭窄層25で吸収されてしまうため、この
光を有効的に利用することが全く出来なかった。
Furthermore, in this conventional structure, the light traveling from the active layer toward the side opposite to the substrate is absorbed by the current confinement layer 25, so that this light cannot be used effectively at all.

この発明の目的は、従来の半導体面発光素子の製造工程
で行われていた拡散工程や穴掘り工程を用いずに、高信
頼性、高出力及び長寿命の半導体面発光素子を簡単かつ
容易に製造出来るようにした半導体面発光素子の製造方
法を提供することにある。
The purpose of this invention is to simply and easily produce semiconductor surface emitting devices with high reliability, high output, and long life without using the diffusion process and drilling process that are carried out in the conventional manufacturing process of semiconductor surface emitting devices. An object of the present invention is to provide a method for manufacturing a semiconductor surface emitting device.

(問題点を解決するための手段) この目的の達成を図るため、この発明の要点は、半導体
面発光素子を基板とは反対側の成長結晶面側から光を取
り出す構造とし、この構造の当該素子の基板側に高反射
多層膜を形成し、さらにこの高反射多層膜上に、拡散に
よって電流狭窄領域を形成する代わりに、液相エピタキ
シャル成長時に内部電流狭窄層を作り込むようにした点
にある。
(Means for Solving the Problems) In order to achieve this object, the main point of the present invention is to provide a semiconductor surface emitting device with a structure in which light is extracted from the growth crystal surface side opposite to the substrate, and Instead of forming a high-reflection multilayer film on the substrate side of the element and then forming a current confinement region by diffusion on this high-reflection multilayer film, an internal current confinement layer is created during liquid phase epitaxial growth. .

従って、この発明の半導体面発光素子の製造方法によれ
ば、基板上にダブルへテロ構造を構成する第一クラッド
層、活性層及び第二クラッド層と、電流狭窄層とを形成
して半導体面発光素子を製造するに当り、 GaAsか
らなる基板上に高反射多層膜を形成し、この高反射多層
膜上にGaAs層を成長させ、次に、このGaAs層を
エツチングして円柱状の凸部を形成し、次に、−回の液
相エピタキシャル成長工程において、順次に連続して、
前述の高反射多層膜上に、この凸部を埋込むように、電
流狭窄層としてのAl) zGa t−yAs層を液相
エピタキシャル成長させ、液相エピタキシャル成長時の
メルトバック速度の組成依存性を利用して、前述の電流
狭窄層に円形の穴を形成し、この穴付き電流狭窄層を有
する基板上に前述の第一クラッド層としてのM yGa
l−yAs層、活性層としてのNJxGat−tAs層
及び第二クラッド層としてのAQyGaz−yAs層(
組成比はx<y 、x<zの関係にある)を液相エピタ
キシャル成長させることを特徴とする。
Therefore, according to the method for manufacturing a semiconductor surface emitting device of the present invention, a first cladding layer, an active layer, a second cladding layer constituting a double heterostructure, and a current confinement layer are formed on a semiconductor surface. In manufacturing a light emitting device, a highly reflective multilayer film is formed on a substrate made of GaAs, a GaAs layer is grown on this highly reflective multilayer film, and then this GaAs layer is etched to form cylindrical convex portions. is formed, and then, in -times of liquid phase epitaxial growth steps, sequentially,
An Al) zGa tyAs layer as a current confinement layer is grown by liquid phase epitaxial growth on the above-mentioned high-reflection multilayer film so as to embed the convex portion, and the composition dependence of the meltback rate during liquid phase epitaxial growth is utilized. Then, a circular hole is formed in the current confinement layer, and the MyGa layer as the first cladding layer is formed on the substrate having the current confinement layer with the hole.
l-yAs layer, NJxGat-tAs layer as the active layer, and AQyGaz-yAs layer as the second cladding layer (
The composition ratio is in the relationship of x<y, x<z) and is characterized by liquid phase epitaxial growth.

(作用) このような方法によれば、高反射多層膜上べのGaAs
層の円形状の凸部の形成後に、−回の液相エピタキシャ
ル成長工程で、電極形成の直前までの素子の各層を順次
に連続して形成することが出来るので、拡散工程や、光
取り出し穴形成工程を必要とせず、従って、簡単かつ容
易に半導体面発光素子を製造することが出来ると共に、
製造された素子の特性が熱的及び機械的な損傷を受ける
ことがないので特性の劣化を来す恐れがない。
(Function) According to such a method, GaAs on the high reflection multilayer film
After the formation of the circular convex portion of the layer, each layer of the device up to just before electrode formation can be successively formed in the second liquid phase epitaxial growth process, which eliminates the diffusion process and the formation of light extraction holes. A semiconductor surface emitting device can be manufactured simply and easily without any process, and
Since the characteristics of the manufactured device are not thermally or mechanically damaged, there is no risk of deterioration of the characteristics.

さらに、得られた素子の構造は基板とは反対側の結晶成
長面側から光取り出しを行い、基板側をマウン]・する
構造となるので、活性層が融材の影響を受けず、高信頼
性と長寿命化を図ることが出来る。
Furthermore, the structure of the obtained device is such that light is extracted from the crystal growth surface side opposite to the substrate, and the substrate side is mounted, so the active layer is not affected by the flux and is highly reliable. It is possible to improve performance and longevity.

さらに、活性層に対し基板側に高反射多層膜を設けるの
で、従来有効に利用していなかった光をこの多層膜で反
射させて有効的に利用出来るので、高出力を得ることが
出来る。
Furthermore, since a highly reflective multilayer film is provided on the substrate side with respect to the active layer, light, which has not been used effectively in the past, can be reflected by this multilayer film and used effectively, so that high output can be obtained.

(実施例) 以下、第1図(A)〜(H)及び第2図を参照して、こ
の発明による半導体面発光素子の製造方法の一実施例を
説明する。
(Example) Hereinafter, an example of the method for manufacturing a semiconductor surface emitting device according to the present invention will be described with reference to FIGS. 1(A) to (H) and FIG. 2.

先ず、第1図(A)につき説明する。p −GaAsか
らなる基板lの基板面la上に第一反射層2aと第二反
射層2bの交互の積層から成る高反射多層膜2を形成す
る。この第一反射膜2afep −AQ uGa t−
uAs層とし、第二反射膜2bをp −AQ vGa 
t−vA1z層(u>vで、後述する活性層の組成比X
に対してX<U。
First, FIG. 1(A) will be explained. A high-reflection multilayer film 2 consisting of alternating layers of first reflective layers 2a and second reflective layers 2b is formed on a substrate surface la of a substrate l made of p-GaAs. This first reflective film 2afep -AQ uGa t-
uAs layer, and the second reflective film 2b is p-AQ vGa
t-vA1z layer (u>v, composition ratio of the active layer described later
For X<U.

Vである)として、例えば、有機金属熱分解法(Koc
vn法)を用いて形成する。これら6膜2a及び2bの
膜厚は発光する光の光路長が1/4波長となるようにそ
れぞれ設定する。尚、これら反射膜2a及び2bノ組成
比をu=0.7及びv = 0.2とすると、高反射多
層膜2全体が60層で、反射率は85%となる(茨木晃
、石用信、伊賀健−: 11382秋季第43回応用物
理学会学術講演会予稿集、130)。この高反射多層膜
2上に、基板と同一の材料の、例えばp形の、GaAs
層3を成長させる。このp−GaAs層3は後述するメ
ルトバックの際に完全に除去されるものである。このよ
うにして、第1図(A)に示すような構造を得る。
For example, organometallic pyrolysis method (Koc
vn method). The thicknesses of these six films 2a and 2b are set so that the optical path length of the emitted light is 1/4 wavelength. If the composition ratios of these reflective films 2a and 2b are u = 0.7 and v = 0.2, the entire high reflective multilayer film 2 has 60 layers, and the reflectance is 85% (Akira Ibaraki, stone material Shin, Ken Iga: 11382 Proceedings of the 43rd Autumn Academic Conference of the Japan Society of Applied Physics, 130). On this high-reflection multilayer film 2, a p-type GaAs film made of the same material as the substrate is coated.
Grow layer 3. This p-GaAs layer 3 is completely removed during meltback described later. In this way, a structure as shown in FIG. 1(A) is obtained.

次に、第1図(B)に示すように、p−GaAs層3の
一部分をその表面3aからフォトリソグラフィー技術を
用いてエツチングを行い、円柱状の凸部3bを形成する
。このエツチングで露出した高反射多層膜2の露出面を
20とする。
Next, as shown in FIG. 1B, a portion of the p-GaAs layer 3 is etched from its surface 3a using photolithography to form a cylindrical convex portion 3b. The exposed surface of the high-reflection multilayer film 2 exposed by this etching is designated as 20.

続いて、この凸部3bが形成された部材をエピタキシャ
ル成長炉に入れる。この場合、スライド方式のエピタキ
シャル成長炉を用いる。次に、第1図(C)に示すよう
に、この成長炉中で、露出面2c及び凸部3b上に、こ
の凸部3bを完全に埋め込んで表面4aが平担となるよ
うにn −AQ zGa t−zAs層を電流狭窄層4
として液相エピタキシャル成長させる。
Subsequently, the member on which the convex portion 3b is formed is placed in an epitaxial growth furnace. In this case, a sliding type epitaxial growth furnace is used. Next, as shown in FIG. 1(C), in this growth furnace, the exposed surface 2c and the convex portion 3b are completely buried so that the surface 4a becomes flat. AQ zGa tzAs layer as current confinement layer 4
It is grown by liquid phase epitaxial growth.

次に、成長炉中でスライドさせて、メルトバック用のG
aAs溶液に移す。そこで、未飽和メルトを用いてメル
トバックを行うと、第1図(D)に示すように、凸部3
bの表面3aが現われる所までメルトバックが進行する
Next, slide it in the growth furnace and prepare the G for meltback.
Transfer to aAs solution. Therefore, when meltback is performed using unsaturated melt, as shown in FIG. 1(D), the protrusions 3
The meltback progresses until the surface 3a of b appears.

メルトバック速度はGaAsよりもAQGaAsの方が
格段に遅いので、GaAsの凸部3bのメルトバックが
速く進む。この凸部3bの選択メルトバックを進め、第
1図(E)に示すような状態を経て、第1図(F)で示
すように高反射多層膜2及び電流狭窄層4の界面(基板
lの露出面1cの位置に対応する)と同−又はほぼ同一
の所までメルトバックした時、このメルトバックを停止
し、穴5を形成する。このメルトバックの際、電流狭窄
層4の、円形の穴5の側壁4bは、この層4の表面側か
ら基板1の方向に見て表面側で多く及び基板側で少なく
メルトバックされるため、表面側での径が大きくなる傾
斜を有している。このメルトバックにより円形の穴5を
有する内部電流狭窄層4が形成される。
Since the meltback speed of AQGaAs is much slower than that of GaAs, the meltback of the convex portion 3b of GaAs proceeds quickly. As this selective meltback of the convex portion 3b progresses, the state shown in FIG. When it melts back to the same or almost the same position as (corresponding to the position of the exposed surface 1c), this meltback is stopped and the hole 5 is formed. During this meltback, the side wall 4b of the circular hole 5 in the current confinement layer 4 melts back more on the surface side and less on the substrate side when viewed from the surface side of this layer 4 toward the substrate 1. It has a slope where the diameter becomes larger on the surface side. This meltback forms internal current confinement layer 4 having circular holes 5.

このメルトバックの終了後、第1図(G)に示すような
ダブルへテロ構造の各層を液相エピタキシャル成長させ
る。このため、穴付き電流狭窄層4を有する基板(以下
、総称してウェハという)をスライドさせて次の液相エ
ピタキシャル成長溶液に運び、そこでp −AQ vG
a7−yAs層を成長させて第一クラッド層6を成長さ
せる。この場合、メルト過飽和度及びこのエピタキシャ
ル成長の成長時間を制御することによって、この穴5の
部分の第一クラッド層6が凹型形状を留めるようにする
After completion of this meltback, each layer of a double heterostructure as shown in FIG. 1(G) is grown by liquid phase epitaxial growth. For this purpose, the substrate (hereinafter collectively referred to as a wafer) having the holed current confinement layer 4 is slid and transported to the next liquid phase epitaxial growth solution, where p -AQ vG
The first cladding layer 6 is grown by growing the a7-yAs layer. In this case, by controlling the melt supersaturation degree and the growth time of this epitaxial growth, the first cladding layer 6 in the hole 5 portion maintains a concave shape.

次に、このウェハを同様にスライドさせてp −AQ 
xGa t−xAs層(この場合、x<y 、 x<z
 、 x<U 、X<V)を成長させて活性層7を形成
し、この場合にも、メルト過飽和度と成長時間とを制御
することによって、穴5の部分の活性層7の厚みが厚く
なってレンズ形状となるようにする。同様にスライドと
成長を繰り返して行って、この活性層7上にn AQy
Gaノー!As層からなる第二クラッド層8及びn−G
aAs層からなるコンタクト層9を順次に液相エピタキ
シャル成長させることによって、第1図(G)に示すよ
うなダブルへテロ構造のウェハを得る。
Next, slide this wafer in the same way to obtain p −AQ
xGa t-xAs layer (in this case, x<y, x<z
, x<U , so that it becomes a lens shape. By repeating sliding and growing in the same way, n AQy is formed on this active layer 7.
Ga no! Second cladding layer 8 made of As layer and n-G
A wafer having a double heterostructure as shown in FIG. 1(G) is obtained by sequentially growing contact layers 9 made of aAs layers by liquid phase epitaxial growth.

その後、第1図(H)に示すように、フォトリソグラフ
ィー技術を用いて、コンタクト層9の表面9aからエツ
チングを行って、円柱状に除去した光取り出し窓(又は
穴ともいう)10を形成する。
Thereafter, as shown in FIG. 1H, etching is performed from the surface 9a of the contact layer 9 using a photolithography technique to form a columnar light extraction window (or hole) 10. .

−に述したこの発明の製造方法によれば、基板上に高反
射多層膜2とGaAs層3を形成し、このGaAsの凸
部3bを形成した後この部材を一旦エビタキシャル成長
炉に入れた後は、何等出し入れなくして、すなわち、−
回の液相エピタキシャル成長工程で、基板上に内部電流
狭窄層とダブルへテロ構造形成の各層とが成長した、電
極形成直前の構造のウェハが得られる。
According to the manufacturing method of the present invention described in -, after forming the high reflection multilayer film 2 and the GaAs layer 3 on the substrate and forming the convex portions 3b of GaAs, this member was once placed in an epitaxial growth furnace. After that, without putting anything in or out, that is, -
In the second liquid phase epitaxial growth process, a wafer having a structure immediately before electrode formation is obtained, in which an internal current confinement layer and each layer forming a double heterostructure are grown on the substrate.

第2図は、このよにして形成されたウェハにn側電極1
1及びp側電極12とを蒸着し、面発光素子を完成した
状態を断面図で示す。
FIG. 2 shows the n-side electrode 1 on the wafer formed in this way.
1 and the p-side electrode 12 are vapor-deposited to form a surface emitting device, which is shown in a cross-sectional view.

このような構造の面発光素子では、オーミック電極とし
てのp側電極12から注入された電流は基板lから多層
膜2を経て穴5の中央部を通って第一クラツド層6→活
性層7→第二クラッド層8→コンタクト層9を経てオー
ミック電極としてのn側電極11に流れる。しかしなが
ら、電流狭窄層4はn型でありp型の第一クラッド層6
との間は逆バイアスとなっているため、基板1からこの
n型電流狭窄層4を経て第一クラッド層6には注入電流
は流れず、従って、このn型電流狭窄層が有効的に機能
し、専ら穴5の中央部分の第一クラッド層6及び活性層
7が電流経路となり、その部分だけに電流の集中が起る
In a surface emitting device having such a structure, a current injected from the p-side electrode 12 as an ohmic electrode passes from the substrate l through the multilayer film 2 and through the center of the hole 5, and then flows from the first cladding layer 6 to the active layer 7 to It flows from the second cladding layer 8 to the contact layer 9 to the n-side electrode 11 as an ohmic electrode. However, the current confinement layer 4 is n-type and the first cladding layer 6 is p-type.
Since there is a reverse bias between the substrate 1 and the n-type current confinement layer 4, no injection current flows from the substrate 1 to the first cladding layer 6 through this n-type current confinement layer 4, and therefore, this n-type current confinement layer functions effectively. However, the first cladding layer 6 and active layer 7 in the central portion of the hole 5 serve as current paths, and current concentration occurs only in that portion.

従って、この面発光素子の場合には、この電流狭窄層4
の穴5の真上の活性層7の領域で再結合発光して得られ
た光は、層組成比がx<yであるため、基板1とは反対
側の、活性層7→第二クラッド層8の経路でコンタクト
層9の光取り出し窓lOより取り出すことが出来る。
Therefore, in the case of this surface emitting device, this current confinement layer 4
Since the layer composition ratio is x<y, the light obtained by recombining and emitting light in the region of the active layer 7 directly above the hole 5 is transmitted from the active layer 7 to the second cladding on the side opposite to the substrate 1. The light can be extracted from the light extraction window 10 of the contact layer 9 through the path of the layer 8.

また、高反射多層M2は光吸収が少なく理想的な高反射
ミラーとなっているため、活性層7から基板側に向けて
発光した光の大部分を反射させることが出来るので、発
光した大部分の光りを光取り出し穴10から有効的に出
力させることが出来る。
In addition, since the high-reflection multilayer M2 has low light absorption and is an ideal high-reflection mirror, it can reflect most of the light emitted from the active layer 7 toward the substrate, so that most of the emitted light This light can be effectively output from the light extraction hole 10.

また、電流狭窄層4の穴5の側壁4bが傾斜しているた
め、活性層7→第一クラツド層6→電流狭窄層4の方向
に進む光りの一部分がこの側壁4bの傾剥面で反射して
(X < Zのため)出力光として取り出すことが出来
るので、高出力が得られる。
Furthermore, since the side wall 4b of the hole 5 in the current confinement layer 4 is inclined, a portion of the light traveling in the direction of the active layer 7 → first cladding layer 6 → current confinement layer 4 is reflected by the inclined surface of the side wall 4b. (because X < Z), it can be extracted as output light, resulting in high output.

さらに、内部電流狭窄層4の電流集中作用及びこの層4
のNの組成比が活性層7の層の組成比よりも大きい(X
<Z)ことにより、光の吸収による光スイツチング動作
を生ずる恐れがなく、高電流動作によって高出力を容易
に取り出すことが出来る。
Furthermore, the current concentrating effect of the internal current confinement layer 4 and this layer 4
The composition ratio of N in the active layer 7 is larger than the composition ratio of the active layer 7 (X
<Z), there is no possibility of optical switching operation due to absorption of light, and high output can be easily obtained through high current operation.

また、活性層7がレンズ状となっているため、集光能力
が高く、これがため1発光径が小さくなり、光ファイバ
との結合に有利である。
In addition, since the active layer 7 is lens-shaped, it has a high light collecting ability, and therefore the single emission diameter becomes small, which is advantageous for coupling with an optical fiber.

この発明は上述した実施例にのみ限定されるものではな
い。例えば、基板を1士しめ各層の導電型を反対導電型
とすることも出来る。すなわち、p型基板とn型電流狭
窄層の組合わせを、n型基板とp型電流狭窄層の組み合
わせとしても良い。
The invention is not limited to the embodiments described above. For example, the conductivity types of each layer can be made to be opposite conductivity types by using only one substrate. That is, the combination of a p-type substrate and an n-type current confinement layer may be replaced by a combination of an n-type substrate and a p-type current confinement layer.

上述したエツチング及び液相エピタキシャル成長の条件
は設計に応じて適切に設定することが出来る。
The conditions for etching and liquid phase epitaxial growth described above can be appropriately set according to the design.

また、各部分の寸法、形状及び配置関係等も適切に設定
出来る。
Further, the dimensions, shapes, arrangement relationships, etc. of each part can be appropriately set.

(発明の効果) 上述した説明からも明らかなように、この発明の半導体
面発光素子の製造方法によれば、高反射多層膜上べのG
aAs層の円柱状の凸部の形成後に、液相エピタキシャ
ル成長時のメルトバック速度の組成比依存性を利用して
、−回の順次の連続した液相エピタキシャル成長で内部
電流狭窄層を作り付けてしまうので、従来のような拡散
工程を必要とせず、さらに、光取り出しを基板とは反対
側の表面から行う構造となっているので、基板に対する
穴開は工程を必要とせず、従って、この発明の素子は、
製造が簡単かつ容易であるという利点がる。
(Effects of the Invention) As is clear from the above explanation, according to the method for manufacturing a semiconductor surface emitting device of the present invention, the G of the high reflective multilayer film is reduced.
After the cylindrical convex portion of the aAs layer is formed, an internal current confinement layer is built up by successive liquid phase epitaxial growth times by utilizing the dependence of the meltback rate on the composition ratio during liquid phase epitaxial growth. , the device of the present invention does not require a diffusion process like the conventional one, and has a structure in which light is extracted from the surface opposite to the substrate, so there is no need for a process to make holes in the substrate. teeth,
It has the advantage of being simple and easy to manufacture.

さらに、活性層に対し基板側に高反射多層膜を設けるの
で、従来有効に利用していなかった光をこの多層膜で反
射させて有効的に利用出来るので、従来よりも高出力を
得ることが出来る。
Furthermore, since a highly reflective multilayer film is provided on the substrate side of the active layer, light that was previously not used effectively can be reflected by this multilayer film and used effectively, making it possible to obtain higher output than before. I can do it.

さらに、ハンダ材等の融剤が基板側にくることにより高
信頼性となり、長寿命となるという利点を有する。
Furthermore, since the fluxing agent such as the solder material is placed on the substrate side, it has the advantage of high reliability and long life.

さらに、この方法では内部電流狭窄層が形成されるので
、電流集中が効率良く行われる素子構造となり、従って
、高電流動作が可能となる。
Furthermore, since an internal current confinement layer is formed in this method, the element structure is such that current concentration can be performed efficiently, and therefore high current operation is possible.

さらにこの発明の方法によれば、活性層をレンズ状に成
長させることが出来るので、面発光素子と光ファイバと
の結合性を高めることが出来る。
Further, according to the method of the present invention, since the active layer can be grown in a lens shape, the coupling between the surface emitting device and the optical fiber can be improved.

この発明による半導体面発光素子は光情報処理及び長寿
命が要求される光通信の分野に適用して好適である。
The semiconductor surface emitting device according to the present invention is suitable for application to the fields of optical information processing and optical communication where long life is required.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)〜(H)はこの発明の半導体面発光素子の
製造方法の一実施例を説明するため製造工程図。 第2図はこの発明の方法により製造された半導体面発光
素子の構造を示す路線的断面図第3図は従来の半導体面
発光素子の製造方法を説明するための略図的断面図であ
る。 1・・・基板(又はGaAs基板) la・・・基板面、 2・・・高反射多層膜2a−”第
一反射膜(又はAQ uGa r−uAs層)2 b−
・・第二反射膜(又はAQvGal−yAs層)2C・
・・(高反射多層膜の)露出面 3 ・・−GaAs層、 3a=・(GaAs層の)表
面3b・・・(GaAsの円柱状の)凸部4・・・電流
狭窄層(又はAQ zGa t−zAs層)4a・・・
(電流狭窄層の)表面 4b・・・(穴の)側壁 5・・・(電流狭窄層の)穴 6・・・第一クラッド層(又はAQyGaノーyAs層
)7・・・活性層(又はAQ xGa )−yAs層)
8・・・第二クラッド層(又はAQ yGa 7− y
As層)9・・・コンタクト層(又はGaAs層)8a
・・・(コンタクト層の)表面 10・・・光取り出し窓、 11.12・・・電極L・
・・光。 特許出願人 沖電気工業株式会社 へ1 へ1 %j 。 ど\ へ く ロ 一ノ \ノ Q口 −夷さた芝力論 手続補正書 昭和60年8月19日 特許庁長官 宇賀 道部 殿 1事件の表示 昭和59年特許願1013253号2発
明の名称 半導体面発光素子の製造方法 3補正をする者 事件との関係 特許出願人 住所(〒−105) 東京都港区虎ノ門1丁目7番12号 名称(028)沖電気工業株式会社 代表者 橋本 南海男 4代理人〒170 tt (988)55E13住所 
東京都豊島区東池袋1丁目20番地5池袋ホワイトハウ
スビル805号 明細書の発明の詳細な説明の欄、図面の簡単な(1)、
明細書、第2頁第18行rPhysic Letter
 JをrPhysics Letters jと訂正す
る。 (2)、同、第9頁第14行「基板1の露出面1cJを
r高反射多層膜2の露出面2cJと訂正する。 (3)、同、第13頁第10行rx<zのため」を「y
≠2とする1と訂正し、同第11行「高出力が得られる
。」を1出力を増大させることができる。」と訂正する
。 (4)、同、第15頁第2行〜第3行「利点がる。」を
1利点がある。Jと訂正する。 (5)、同、第16頁第3行「説明するため製造」火r
説明するための製造1と訂正し、同第6行「路線的断面
図」をr略図的断面図、1と訂正する。 (8)3図面第2図を添付した訂正図の通り訂正する。
FIGS. 1A to 1H are manufacturing process diagrams for explaining an embodiment of the method for manufacturing a semiconductor surface emitting device of the present invention. FIG. 2 is a schematic cross-sectional view showing the structure of a semiconductor surface-emitting device manufactured by the method of the present invention. FIG. 3 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor surface-emitting device. 1...Substrate (or GaAs substrate) la...Substrate surface, 2...Highly reflective multilayer film 2a-"first reflective film (or AQ uGa r-uAs layer) 2 b-
・Second reflective film (or AQvGal-yAs layer) 2C・
...Exposed surface 3 (of the high-reflection multilayer film)...-GaAs layer, 3a=...Surface 3b (of the GaAs layer)...Convex portion 4 (cylindrical of GaAs)...Current confinement layer (or AQ zGa t-zAs layer) 4a...
Surface 4b (of the current confinement layer)... Side wall 5 (of the hole)... Hole 6 (of the current confinement layer)... First cladding layer (or AQyGa or As layer) 7... Active layer (or AQ xGa )-yAs layer)
8... Second cladding layer (or AQ yGa 7- y
As layer) 9... contact layer (or GaAs layer) 8a
... (contact layer) surface 10 ... light extraction window, 11.12 ... electrode L.
··light. To patent applicant Oki Electric Industry Co., Ltd. 1%j. Do\Heku Roichino\NoQguchi-Isata Shiba Power Theory Procedural Amendment August 19, 1985 Director General of the Patent Office Tono Uga Michibe 1 Indication of Case 1989 Patent Application No. 1013253 2 Name of Invention Relationship with the Case of Person Who Amends Manufacturing Method for Semiconductor Surface Emitting Devices 3 Patent Applicant Address (〒-105) 1-7-12 Toranomon, Minato-ku, Tokyo Name (028) Oki Electric Industry Co., Ltd. Representative Nankai Hashimoto 4 Agent Address: 170 tt (988) 55E13
1-20-5 Ikebukuro White House Building, Toshima-ku, Tokyo Detailed explanation column of the invention in the specification, brief (1) of the drawing,
Specification, page 2, line 18 rPhysic Letter
Correct J to rPhysics Letters j. (2), same, page 9, line 14, ``Correct the exposed surface 1cJ of the substrate 1 to be the exposed surface 2cJ of the high-reflection multilayer film 2.'' (3), same, page 13, line 10, rx<z ``y''
By correcting ≠2 to 1, the 11th line "High output can be obtained" can be increased by 1. ” he corrected. (4), page 15, lines 2 and 3, ``There is an advantage.'' There is one advantage. Correct it with J. (5), same, page 16, line 3 “Manufacturing to explain” Tue r
It has been corrected to ``Manufacture 1 for explanation'', and the line 6, ``Route sectional view'' has been corrected to ``R Schematic sectional view'', 1. (8) Correct as shown in the correction diagram attached with Figure 2 of 3 drawings.

Claims (1)

【特許請求の範囲】 ■、基板上にダブルへテロ構造を構成する第一クラッド
層、活性層及び第二クラッド層と、電流狭窄層とを形成
して半導体面発光素子を製造するに当り、 GaAs基板上に高反射多層膜を形成し、該高反射多層
膜上にGa As層を成長させ。 次に、該GaAs層をエツチングして円柱状の凸部を形
成し、 次に、−回の液相エピタキシャル成長工程において、順
次に連続して、 前記高反射多層膜上に、該凸部を埋込むように、電流狭
窄層としてのAQ zGa /−2AS層を液相エピタ
キシャル成長させ、 液相エピタキシャル成長時のメルトバック速度の組成依
存性を利用して、前記電流狭窄層に円形の穴を形成し、 該穴付き電流狭窄層を有する基板上に前記第一クラッド
層としてのAQyGaz−yAs層、前記活性層として
のAOxGa/−yAs層及び前記第二クラッド層とし
テノAQ yGaz−yAs層(組成比はx<y 、x
<zの関係にある)を液相エピタキシャル成長させるこ
とを特徴とする半導体面発光素子の製造方法。 2、前記高反射多層膜をAQ uGa /−uAs膜及
びAQ vGa /−vAs膜(組成比はv<u 、 
x<u 、 x<vの関係にある)を交互に成長させて
形成し、これら6膜の膜厚は発光する光の光路長が1/
4波長となるように設定したことを特徴とする特許請求
の範囲第1項記載の半導体面発光素子の製造方法。
[Claims] (2) In manufacturing a semiconductor surface emitting device by forming a first cladding layer, an active layer, a second cladding layer, and a current confinement layer constituting a double heterostructure on a substrate, A high reflection multilayer film is formed on a GaAs substrate, and a GaAs layer is grown on the high reflection multilayer film. Next, the GaAs layer is etched to form a cylindrical convex portion, and then, in the second liquid phase epitaxial growth step, the convex portion is successively buried on the high reflection multilayer film. An AQ zGa /-2AS layer as a current confinement layer is grown by liquid phase epitaxial growth so as to fill the current confinement layer, and a circular hole is formed in the current confinement layer by utilizing the composition dependence of the meltback rate during liquid phase epitaxial growth. On the substrate having the holed current confinement layer, an AQyGaz-yAs layer as the first cladding layer, an AOxGa/-yAs layer as the active layer, and a TenoAQ yGaz-yAs layer as the second cladding layer (the composition ratio is x<y, x
A method for manufacturing a semiconductor surface emitting device, characterized by performing liquid phase epitaxial growth. 2. The high reflection multilayer film is an AQ uGa/-uAs film and an AQ vGa/-vAs film (composition ratio is v<u,
x<u, x<v), and the film thickness of these six films is such that the optical path length of the emitted light is 1/
2. The method of manufacturing a semiconductor surface emitting device according to claim 1, wherein the wavelength is set to four.
JP59109253A 1984-05-29 1984-05-29 Manufacture of semiconductor surface light-emitting element Pending JPS60253285A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59109253A JPS60253285A (en) 1984-05-29 1984-05-29 Manufacture of semiconductor surface light-emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59109253A JPS60253285A (en) 1984-05-29 1984-05-29 Manufacture of semiconductor surface light-emitting element

Publications (1)

Publication Number Publication Date
JPS60253285A true JPS60253285A (en) 1985-12-13

Family

ID=14505488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59109253A Pending JPS60253285A (en) 1984-05-29 1984-05-29 Manufacture of semiconductor surface light-emitting element

Country Status (1)

Country Link
JP (1) JPS60253285A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830186A (en) * 1981-08-18 1983-02-22 Toshiba Corp Manufacture of optical semiconductor element
JPS58222581A (en) * 1982-06-19 1983-12-24 Mitsubishi Electric Corp Manufacture of semiconductor light-emitting element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5830186A (en) * 1981-08-18 1983-02-22 Toshiba Corp Manufacture of optical semiconductor element
JPS58222581A (en) * 1982-06-19 1983-12-24 Mitsubishi Electric Corp Manufacture of semiconductor light-emitting element

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