JPS58222581A - Manufacture of semiconductor light-emitting element - Google Patents
Manufacture of semiconductor light-emitting elementInfo
- Publication number
- JPS58222581A JPS58222581A JP57106420A JP10642082A JPS58222581A JP S58222581 A JPS58222581 A JP S58222581A JP 57106420 A JP57106420 A JP 57106420A JP 10642082 A JP10642082 A JP 10642082A JP S58222581 A JPS58222581 A JP S58222581A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- protrusion
- current blocking
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000007791 liquid phase Substances 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 30
- 238000004090 dissolution Methods 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 9
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005253 cladding Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000012047 saturated solution Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体発光素子の製造方法に関し、特に半導
体発光素子内部を流れる電流を特定の領域に狭窄化する
のに有効な製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor light emitting device, and more particularly to a manufacturing method effective for confining a current flowing inside the semiconductor light emitting device to a specific region.
一般に半導体発光素子において、半導体発光素子内部を
流れる電流をある特定の領域に狭窄化することは、その
発光特性を維持向上する上で必須の条件となっている。In general, in a semiconductor light emitting device, confining the current flowing inside the semiconductor light emitting device to a specific region is an essential condition for maintaining and improving its light emitting characteristics.
例えば、レーザ・ダイオードでは電流をストライプ状領
域に狭窄化することによってはじめてしきい値電流の低
減化、横基本モード発振の実現が可能となるものであり
、また発光ダイオードにおいても、例えば円形領域に電
流を狭窄化することによって高輝度化が実現可能となる
。For example, in laser diodes, it is only possible to reduce the threshold current and achieve transverse fundamental mode oscillation by confining the current into a striped region, and in light emitting diodes, for example, by narrowing the current into a circular region. High brightness can be achieved by narrowing the current.
従来、このような電流狭窄化のための構造は種々提案さ
れているが、その一つとして動作時には逆バイアスされ
る接合を有する構造は、逆バイアスされる接合領域で容
易に電流を阻止することができるため、電流を特定の領
域に確実に狭窄化するこ七ができ、半導体発光素子では
広く採用されている。そのような半導体発光素子の一例
の主要部の断面図を第1図に示す。第1図において、+
11はN形半導体基板、(2)はP形を流阻止層、(3
)はN形りラッド層、(4)はP形活性i、+5+はP
形りラッド層であり、N形りラッド層(3)、P形活性
層(4)およびP形りラッド層(5)の3層はいわゆる
ダブルへテロ構造を形成している。この半導体発光素子
において、順方向にバイアスした動作時には、P形N流
明止/!!f21.?n形クラッド層(3)とで形成す
るPN接合は逆バイアスされるから、電流はP形電流阻
止層(2)で囲まれたN形りラッド層(31の領域工に
狭窄化することができ、発光部の幅は領域工の幅Wにお
おむね近い値にしほり込まれるので、レーザダイオード
ではしきい値電流の低減化、横基本モード発振などが実
現で色、また、発光ダイオードでは高輝度化が実現でき
る。ただし、このとき、P形電流阻止層(2)がP形活
性層(4)で発生した光を吸収してキャリアを発生し阻
止状態を崩壊させることのないように、P形電流阻止層
(2)の禁制帯幅をP形活性層(4)のそれよpも大き
くするなどの工夫を必要とする。Conventionally, various structures for current confinement have been proposed, but one of them is a structure that has a junction that is reverse biased during operation because it is difficult to easily block current in the reverse biased junction region. This makes it possible to reliably constrict the current to a specific region, and it is widely used in semiconductor light emitting devices. A cross-sectional view of the main parts of an example of such a semiconductor light emitting device is shown in FIG. In Figure 1, +
11 is an N-type semiconductor substrate, (2) is a P-type flow blocking layer, (3
) is N-type rad layer, (4) is P-type active i, +5+ is P
The three layers of the N-shaped rad layer (3), the P-type active layer (4), and the P-shaped rad layer (5) form a so-called double heterostructure. In this semiconductor light emitting device, during forward biased operation, P type N flow /! ! f21. ? Since the PN junction formed with the n-type cladding layer (3) is reverse biased, the current can be narrowed to the area of the N-type cladding layer (31) surrounded by the P-type current blocking layer (2). Since the width of the light emitting part is carved to a value roughly close to the width W of the area, laser diodes can achieve reduced threshold current, oscillation in the transverse fundamental mode, etc. However, at this time, in order to prevent the P-type current blocking layer (2) from absorbing the light generated in the P-type active layer (4), generating carriers and collapsing the blocking state, the P-type current blocking layer (2) must be It is necessary to take measures such as making the forbidden band width of the P-type current blocking layer (2) larger than that of the P-type active layer (4).
第2図(a)〜(c)に第1図に示す半導体発光素子の
従来の製造方法の主要工程における状態の断面図を示す
。まず、第2図(、)に示すように、N形半導体基板(
1)上にP形市、流阻止N(2)を成長させる。次に第
2図(b)に示すように写真製版法によりP形電流阻止
層(2)に電流の通路となるべき領域の窓あけを行い、
つづいて第2図(C)に示すように、N形りラッド層(
3)、P形活性層(4)、P形りラッドm (51を成
長させて素子構造を完成する。このように従来の製造方
法では、第2図(b)のようにp形電流阻止#(2)の
窓あけ工程か必要なために、結晶成長を2回に分けて実
施する必要があり、素子製造上、工程の煩雑さや工期の
増大を招いており、ひいては製造コストの増大となる不
都合な面があった。さらにGaAs系の半導体発光素子
では、P形電流阻止(2)は禁制帯を広くするためにA
lGaAeで形成されるが、このAI!GaAeは酸化
性が強いために、ダブルへテロ構造をつくる2度目の結
晶成長前には結晶基板の充分慎重な処理・取扱いが必要
であり、それでもなおアルミニウム酸化物の残存・発生
はしばしば起こり、2度目の結晶成長でこのアルミニウ
ム酸化物のために結晶成長しない部分を生じたり、素子
構造を完成してもアルミニウム酸化物を取り込んだ結晶
部分は欠陥を生じており非発光部となって、素子寿命を
短くするなど製造歩留り土工都合な面があった。FIGS. 2(a) to 2(c) show cross-sectional views of main steps in the conventional manufacturing method of the semiconductor light emitting device shown in FIG. 1. First, as shown in Figure 2 (,), an N-type semiconductor substrate (
1) Grow P-type city, flow prevention N(2) on top. Next, as shown in FIG. 2(b), a window is formed in the P-type current blocking layer (2) in the area that should become a current path by photolithography.
Next, as shown in FIG. 2(C), an N-shaped rad layer (
3), a P-type active layer (4), and a P-type rad m (51) are grown to complete the device structure.In the conventional manufacturing method, as shown in FIG. Because the window opening process in #(2) is required, the crystal growth must be performed in two steps, which increases the complexity of the process and the length of time required to manufacture the device, which in turn increases the manufacturing cost. Furthermore, in GaAs-based semiconductor light emitting devices, the P-type current blocking (2) is used to widen the forbidden band.
Although it is formed of lGaAe, this AI! Because GaAe has strong oxidizing properties, it is necessary to treat and handle the crystal substrate very carefully before the second crystal growth to form a double heterostructure, but even then, aluminum oxide often remains or is generated. During the second crystal growth, some parts of the crystal do not grow due to this aluminum oxide, and even after the device structure is completed, the crystal parts that incorporate the aluminum oxide have defects and become non-emissive parts, causing the device to fail. There were some disadvantages to manufacturing yields, such as shortening the lifespan.
この発明は、以上の点にかんがみてなされたもので、半
導体発光素子の製造方法に関して、製造工程の簡略化を
実現し、製造コストの低減を達成することを目的とする
ものであり、ひいては、製造工程の簡略化により結晶性
を向上させて製造歩留りの向上を図ることを目的とrる
ものである。The present invention has been made in view of the above points, and aims to simplify the manufacturing process and reduce manufacturing costs in a method of manufacturing a semiconductor light emitting device. The purpose is to improve crystallinity and improve manufacturing yield by simplifying the manufacturing process.
この発明は、以上の目的を達成するためにあらかじめN
形半導体基板に電流の通路となるべき突出部を設けてお
き1度の液相エピタキシャル成長によってP形電流阻止
Jk、N形りラッド層、P形活性層およびP形りラッド
層を成長させて素子構造を完成するのであるが、そのた
めにP形電流阻止層を半導体基板の突出部の頂部では層
厚を薄く、突出部以外の部分では層厚を厚く成長させ、
次のN形りラッド層の成長では突出部の頂部上のP形電
流阻止層の厚さに相当する分だけP形電流阻止層の表面
を溶解させ、突出部の頂部でN形半導体基板とN形りラ
ッド層とを接続させて電流の通路を完成させるものであ
る。In order to achieve the above object, this invention
A protrusion to serve as a current path is provided on a semiconductor substrate, and a P-type current blocking layer, an N-type rad layer, a P-type active layer, and a P-type rad layer are grown by one-time liquid phase epitaxial growth to form a device. To complete the structure, a P-type current blocking layer is grown to be thinner on the top of the protrusion of the semiconductor substrate and thicker in areas other than the protrusion.
In the next growth of the N-shaped rad layer, the surface of the P-type current blocking layer is dissolved by an amount corresponding to the thickness of the P-type current blocking layer on the top of the protrusion, and the N-type semiconductor substrate is formed at the top of the protrusion. The current path is completed by connecting the N-shaped rad layer.
第3図(a) T (b)にこの発明による半導体発光
素子の製造方法の一実施例の主要工程における状態の断
面図を示す。ます、第3図(a)に示すように、N形半
導体基板1+)に写真製版法により電流の通路となるべ
き突出部■を形成する。次に、第3図(b)に示すよう
に、液相エピタキシャル成長法によりP形電流阻止層(
2へN形りラッド層(3)、P形活性層(4)およびP
形りラッド層(6)を連続的に成長させる。FIGS. 3(a) and 3(b) show cross-sectional views of main steps in an embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention. First, as shown in FIG. 3(a), a protrusion (2) to serve as a current path is formed on the N-type semiconductor substrate (1+) by photolithography. Next, as shown in FIG. 3(b), a P-type current blocking layer (
2 to N-type rad layer (3), P-type active layer (4) and P
A shaped rad layer (6) is grown continuously.
このとき、P形電流明止N(2)を半導体基板(1)の
突出部■の頂部では層厚を薄く、突出部■以外の部分■
でけ層厚苔・厚く成長させる。この場合、例えばGaA
s系の半導体発光素子ではP形雷、流阻止層(2)はP
形活性膚(4)よυ禁制帯幅を広くとるためにAj+G
aAsで形成するが、一定の温度勾配で降温する成長法
では冷却速度を1°C/分以下に非常に小さくとること
により、凹凸のある表面にAlGaAs層を上記のよう
な層厚分布で成長させることが可能であることは広く知
られている。こうして成長したP形電流阻止層(2)の
上に未飽和のN形りラッド成長用溶液をかぶせて突出部
の頂部に成長したP形電流阻止N(2)の厚さの分だけ
P形電流阻止層(2)の表面部(6)を溶解してやれば
よい。溶解する量はN形りラッド層(3)成長用の溶液
中のヒ素量により未飽和度を調整して決定する。また、
溶解する方法については、ちょうど飽和したN形りラッ
ド層(3)成長用溶液をP形電流阻止層(2)にかぶせ
てやり、その後、昇温しでN形りラッド層(3)の成長
用溶液を未飽和にして、P形市、流阻止層(21の表面
部を溶解する方法などでも勿論側らさしつかえない。こ
の場合は溶解する量は昇温する温度の大きさにより調整
すればよく、N形りラッドJitl (31以降の層は
溶解した後再び降温することにより成長することができ
る。At this time, the P-type current stop N (2) is made thinner on the top of the protruding part (■) of the semiconductor substrate (1), and the layer thickness is made thinner on the top of the protruding part (■) of the semiconductor substrate (1),
Thick layer of moss - Make it grow thick. In this case, for example, GaA
In the s-based semiconductor light emitting device, the P-type lightning, and the flow blocking layer (2) is P-type lightning.
Aj+G to widen the υ forbidden band width as in shape active skin (4)
However, in the growth method where the temperature is lowered with a constant temperature gradient, the cooling rate is kept very low, less than 1°C/min, so that an AlGaAs layer can be grown on the uneven surface with the layer thickness distribution shown above. It is widely known that it is possible to The P-type current blocking layer (2) grown in this way is covered with an unsaturated N-type rad growth solution, and the P-type current-blocking layer (2) is coated with an amount corresponding to the thickness of the P-type current blocking layer (2) grown on the top of the protrusion. The surface portion (6) of the current blocking layer (2) may be dissolved. The amount to be dissolved is determined by adjusting the degree of unsaturation depending on the amount of arsenic in the solution for growing the N-shaped rad layer (3). Also,
As for the dissolving method, just cover the P-type current blocking layer (2) with a saturated solution for growing the N-type LAD layer (3), and then raise the temperature to grow the N-type LAD layer (3). Of course, it is also possible to use the method of making the solution unsaturated and dissolving the surface of the P-type layer or flow prevention layer (21).In this case, the amount dissolved can be adjusted depending on the temperature increase Often, the layers after N-shaped rad Jitl (31) can be grown by lowering the temperature again after melting.
以上述べたように1.この発明では従来2回の結晶成長
を必要としていたものを1回のみてす甘せることができ
るので、製造工程の簡略化による工期の短縮、製造コス
トの低減が可能である。さらに、1回のみの結晶成長で
は2回成長の場合のように、一度成長させた後に結晶成
長基板を一旦、成長炉外へ取り出して外気に触れさぜる
必すがないので、何に、AlGaAsでは外気による酸
化の心配がなくなるため、結晶性の向上が期待できるも
のでおり、製造歩留りを向上させることができる。As mentioned above, 1. According to the present invention, the crystal growth that conventionally required two times can be reduced to just one, so that it is possible to shorten the manufacturing period and reduce the manufacturing cost by simplifying the manufacturing process. Furthermore, in the case of one-time crystal growth, unlike in the case of two-time growth, there is no need to take the crystal growth substrate out of the growth furnace and expose it to the outside air after the first growth. With AlGaAs, there is no need to worry about oxidation due to outside air, so improvement in crystallinity can be expected, and manufacturing yield can be improved.
なお、上述の実施例ではAlGaAs系の半導体発光素
子につい°C説明したが他の半導体桐料、例えば・「ン
ジウム・リン(Ink)系などのものを用いた場合にも
同様に有効であることは言う寸でもない。In addition, although the above-mentioned embodiment describes an AlGaAs-based semiconductor light-emitting device, it is equally effective when using other semiconductor materials, such as indium phosphide (Ink)-based materials. It's not even close to saying that.
第1図は逆バイアス接合による電流阻止服を持った半導
体発光素子の一例を示す断面図、第2図(8)〜(0)
は第1図の半導体発光素子の従来の製造方法の主要工程
における状態を示した断面図、第3図<a)、 (1)
)はこの発明による半導体発光素子の製造方法の一実施
例の主要工程における状態を示した断面図である。
図において、fl+は11形半導体基板、(2)はP形
電流阻止/ai(第1の半導体層) 、(31はN形り
ラッド層(第2の半導体N ) 、f41はP形活性廖
、(5)はP形りラッド屑、(6)はP形電流阻止層(
2)の溶は込まし部分、Jは電流の通路となるべき領域
、nはN形半導体基板(1)の突出部、111は半導体
基&(1)の突出部以外の部分、Wは突出部工の電流の
通路となるべき領域の幅である。
なお、図中同一符号は同一または相当部分を示す。
代理人 葛 野 信 −(外1名)第1図
第2図
第3図
手続補正書(自発)
特許庁長官殿
]、0件の表示 特願昭57−106420号2
、発明の名称 半導体発光素子の製造方法3、補正
をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号
名 称(601) 三菱電機株式会社代表者片山仁
八部
4、代理人
住 所 東京都千代田区丸の内二丁目2番3号
5、 補正の対象
8A#I書の特許請求の範囲の欄および発明の詳細な説
明の欄
6、 補正の内容
(1)明細書の特許請求の範囲を除行別紙のとおりに訂
正する。
(2)明細書の第4頁第16行および第6頁第18行の
「GaAs系」を「AAGaAs系」に訂正する。
(3)同、第4頁第17行の「P形電流阻止(2)」を
「P形電流阻止層(2)」に訂正する。
7、 添付書類の目録
(1)訂正後の特許請求の範囲を示す書面 1通以上
特許l1Ti水の範囲
(1)半導体基板上に設けられ上記半導体基板とは反対
の伝導形を有する第1の半導体層と上記第1の半導体層
の上の所定位置に設けられ上記半導体基板と同一の伝導
形を有する第2の半導体層とで形成されたPH接合が動
作時には逆バイアスされて電流を阻止する構造の半導体
発光素子を製造する方法において、上記半導体基板の一
方の主面に電流を狭窄化するための突出部をあらかじめ
形成しておき、液相エピタキシャル成長法により、上記
突出部を有する上記半導体基板の上記主面上に上記突出
部の頂部では、層厚が薄く、上記突出部以外では層厚が
厚くなるように上記第1の半導体層を形成し、上記第1
の半導体層の上に、上記突出部の頂部の上記第1の半導
体層r/iS解して消失させるように上記第2の半導体
層を形成することを特徴とする半導体発光素子の製造方
法。Fig. 1 is a cross-sectional view showing an example of a semiconductor light emitting device having a current blocking suit using a reverse bias junction, Fig. 2 (8) to (0)
is a cross-sectional view showing the main steps of the conventional manufacturing method for the semiconductor light emitting device shown in FIG. 1, and FIG. 3<a), (1)
) is a sectional view showing the main steps of an embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention. In the figure, fl+ is an 11-type semiconductor substrate, (2) is a P-type current blocking/ai (first semiconductor layer), (31 is an N-type rad layer (second semiconductor layer), and f41 is a P-type active layer). , (5) is P-type rad scrap, (6) is P-type current blocking layer (
2), the melt penetration part, J is the area that should become a current path, n is the protrusion of the N-type semiconductor substrate (1), 111 is the part other than the protrusion of the semiconductor base & (1), W is the protrusion This is the width of the area that should become the current path for the part. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person) Figure 1 Figure 2 Figure 3 Procedural amendment (voluntary) Commissioner of the Japan Patent Office], 0 items displayed Patent Application No. 106420/1982
, Title of the invention Method for manufacturing semiconductor light-emitting devices 3, Relationship to the amended case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Jinhachi Katayama, Representative of Mitsubishi Electric Corporation Part 4, Address of agent: 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo, Subject of amendment 8A#I, Claims column and Detailed explanation of the invention column 6, Contents of amendment (1) The scope of claims in the specification shall be corrected as per the attached appendix. (2) "GaAs-based" on page 4, line 16 and page 6, line 18 of the specification is corrected to "AAGaAs-based." (3) Same, on page 4, line 17, "P-type current blocking layer (2)" is corrected to "P-type current blocking layer (2)". 7. List of attached documents (1) Documents showing the scope of the claims after correction One or more copies Patent l1 Scope of Ti water (1) A first semiconductor substrate provided on a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate A PH junction formed between a semiconductor layer and a second semiconductor layer provided at a predetermined position on the first semiconductor layer and having the same conductivity type as the semiconductor substrate is reverse biased during operation to block current flow. In a method for manufacturing a semiconductor light emitting device having a structure, a protrusion for confining a current is formed in advance on one main surface of the semiconductor substrate, and the semiconductor substrate having the protrusion is grown by a liquid phase epitaxial growth method. The first semiconductor layer is formed on the main surface of the semiconductor layer such that the first semiconductor layer is thin at the top of the protrusion and thick at areas other than the protrusion;
A method for manufacturing a semiconductor light emitting device, characterized in that the second semiconductor layer is formed on the semiconductor layer in such a way that the first semiconductor layer r/iS on the top of the protruding portion dissolves and disappears.
Claims (1)
の伝導形を有する第1の半導体層と上記第1の半導体層
の上の所定位置に設けられ上記半導体基板と同一の伝導
形を有する第2の半導体層とで形成PN接合が動作時に
は逆バイアスされて電流を阻止する構造の半導体発光素
子を製造する方法において、上記半導体基板の一方の主
面に電流を狭窄化するための突出部をあらかじめ形成し
ておき、液相エピタキシャル成長法により、上記突出部
を有する上記半導体基板の上記主面上に上記突出部の頂
部では、層厚が薄く、上記突出部以外では層厚が厚くな
るように上記第1の半導体層を形成し、上記第1の半導
体層の上に、上記突出部の頂部の上記第1の半導体層は
溶解して消失させるように上記第2の半導体層を形成す
ることを特徴とする半導体発光素子の製造方法。(1) A first semiconductor layer provided on a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate; and a first semiconductor layer provided at a predetermined position on the first semiconductor layer and having the same conductivity type as the semiconductor substrate. In a method for manufacturing a semiconductor light emitting device having a structure in which a PN junction formed with a second semiconductor layer is reverse biased during operation to block current, a protrusion for confining current on one main surface of the semiconductor substrate is provided. is formed in advance on the main surface of the semiconductor substrate having the protrusion by liquid phase epitaxial growth so that the layer is thin at the top of the protrusion and thick at areas other than the protrusion. The first semiconductor layer is formed on the first semiconductor layer, and the second semiconductor layer is formed on the first semiconductor layer such that the first semiconductor layer on the top of the protrusion is dissolved and disappeared. A method for manufacturing a semiconductor light emitting device, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57106420A JPS58222581A (en) | 1982-06-19 | 1982-06-19 | Manufacture of semiconductor light-emitting element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57106420A JPS58222581A (en) | 1982-06-19 | 1982-06-19 | Manufacture of semiconductor light-emitting element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58222581A true JPS58222581A (en) | 1983-12-24 |
Family
ID=14433169
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57106420A Pending JPS58222581A (en) | 1982-06-19 | 1982-06-19 | Manufacture of semiconductor light-emitting element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58222581A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60253285A (en) * | 1984-05-29 | 1985-12-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor surface light-emitting element |
-
1982
- 1982-06-19 JP JP57106420A patent/JPS58222581A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60253285A (en) * | 1984-05-29 | 1985-12-13 | Oki Electric Ind Co Ltd | Manufacture of semiconductor surface light-emitting element |
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