JPS60253258A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent electrostatic breakdown without affecting normal circuit operation by connecting a collector and an emitter in a transistor element as a protective element in parallel between a collector and an emitter in a transistor element. CONSTITUTION:An N-P-N type transistor element 2 used as a transistor such as an input one for a differential amplification citcuit is formed. A collector and an emitter in the element 2 are each connected to external lead terminals 4 through pads 3. An N-P-N type transistor element 5 as a protective element is shaped in an island region electrically isolated from an island region in which the element 2 is formed. An emitter region in the element 5 is connected to an emitter region in the element 2 while a collector region in the element 5 is connected to a collector region in the element 2. When surge voltage is applied to the external terminals, the transistor element 2 and the transistor element 5 as the protective element each share surge voltage, and the transistor elements 2, 5 mutually absorb surge voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device that prevents electrostatic damage in integrated circuits.

(b) Prior art At least one NPN transistor element (2) is provided in a semiconductor substrate (1), and the collector and emitter of the transistor element (2) are connected to external lead terminals (4) via pads (3), respectively. There is a semiconductor integrated circuit device connected to. External lead terminals (4) of this type of semiconductor integrated circuit device
), a large bias is applied in the reverse direction to the PN junction, and if that voltage is higher than the withstand voltage of the PN junction, the element will be destroyed. In particular, when surge voltage (g) is applied to the collector and (c) to the emitter, a large bias is applied in the opposite direction to the PN junction between the emitter and base, which has a small PN junction area among the elements, making it easy to break down. . Therefore, as a method for preventing electrostatic damage in this type of semiconductor integrated circuit device, as shown in FIG. 5, a resistor (7) is connected in series between the pad (3) and the collector and emitter. There is a method of smoothing the surge voltage waveform using the time constant of stray capacitance and resistance to prevent sudden surge voltage from entering the transistor element. However, in this method, if the resistance value of the resistor (7) to be connected is several tens to hundreds of ohms, it cannot be said to be a perfect countermeasure, and the resistance value must be several kilohms or more.

However, if a resistor (7) with a resistance of several kilohms or more is provided at a position on the circuit, not only will the pattern area increase, but also the resistor (7) will cause attenuation in the case of a normal input signal. This is undesirable because it causes problems in the circuit, such as shifting the operating point of the circuit or changing circuit constants. Furthermore, if the resistor (7) is composed of a P-type region formed in an N-type semiconductor region, it will not be destroyed when a surge voltage is applied in the forward direction to the PN junction between the N-type semiconductor region and the P-type region. However, when a surge voltage of one magnitude higher is applied in the opposite direction, the resistor itself will be destroyed if the voltage is higher than the withstand voltage of the PN junction. Therefore, an element with a pseudo transistor structure that operates in the forward direction is connected to the semiconductor substrate in parallel with the input terminal of the protected circuit, and even if a surge voltage is applied in either the forward or reverse direction, the element will not be destroyed and will function as a transistor. There is an electrostatic breakdown prevention element configured to absorb surge voltage when activated (see Japanese Patent Publication No. 53-21838 for details). However, even in the normal case, this element is configured so that the input signal is sent to the input side of the circuit through the N-type doped layer, so a voltage drop occurs due to the internal resistance of the doped layer, and as mentioned above. I have a similar problem.

Another method is to increase the size of the transistor element (2) connected to the external lead terminal (4) to increase the PN junction area. That is, P.N.
This method increases the breakdown voltage of the junction to prevent damage caused by surge voltage. However, if there are multiple transistor elements that have a rising ratio of this transistor element and ■□, the size of all of those transistor elements must be similarly increased, and the pattern area becomes larger. This is disadvantageous in terms of design.

(c) Purpose of the Invention The present invention has been made to solve the above-mentioned difficulties, and it is an object of the present invention to prevent electrostatic damage without affecting normal circuit operation.

B) Structure of the Invention The present invention provides a semiconductor integrated circuit device comprising at least one NPN type transistor element in a semiconductor substrate, the collector and emitter of the transistor element being connected to external terminals, respectively, in which the transistor element is formed. An island region electrically isolated from the island region is used as a collector region, a P type base region is formed in this island region, and an N type emitter region is formed in this space region to form an NPN type as a protection element. By forming a transistor element and connecting a collector region to a collector region and an emitter region to an emitter region of each transistor element, the transistor element serving as the protection element is connected between the collector and emitter of the transistor element. This is a semiconductor integrated circuit device in which a collector and an emitter are connected in parallel.

(e) Example An example of the present invention will be described below with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing the configuration of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a plan view showing main parts of the present invention,
FIG. 3 is a sectional view taken along the line ■--■ in FIG. 2.

As shown in FIG. 1, the semiconductor integrated circuit device according to the present invention includes an NPN transistor element (2) used as an input transistor of a differential amplifier circuit, for example, in a semiconductor substrate (1).
) is provided. The collector and emitter of this transistor element (2) are each connected to an external lead terminal (4) via a pad (3). Further, an NPN transistor element (5) as a protection element is provided in an island region electrically separated from the island region in which the transistor element (2) is formed.

Then, while connecting the emitter region of the transistor element (5) to the emitter region of the transistor element (2),
The collector region of the transistor element (6) is connected to the collector region of the transistor element (2). By connecting the transistor elements (2) and (5) in this manner, the collector and emitter of the transistor element (5) as a protection element are connected in parallel between the collector and emitter of the transistor element (2).

Note that the base of the transistor element (5) is made floating so that no base bias is applied.

Next, embodiments of the present invention will be described in detail with reference to FIGS. 2 and 3. N on a P-type silicon semiconductor substrate
A − type epitaxial layer (b) is formed, and this epitaxial layer α◇ is separated into islands by a P type isolation region (6) to form island regions Q3 (14).

In addition, an N-type buried layer 06 (to) is provided on the bottom surface of each island region Q3 (b), and the island region (to) is NPN.
In the collector region (43a) of the type transistor element (2), the island region 0 becomes the collector region (14a) of the NPN transistor element (5) as a protection element. and,
P-type base regions (17) are formed on the surfaces of the island regions (to) α→ by base diffusion. Furthermore, N 2 emitter regions 0→QO are formed in the base region (to) αη by emitter diffusion, respectively. At this time, an N type collector contact region -Qη is formed on the surfaces of the collector regions (13a) (14a). In addition, a protective film made of silicon oxide etc. is applied to the surface of the epitaxial layer α.
is formed. A contact hole communicating with each region is formed in this protective film (c), and an electrode ring made of aluminum or the like is provided to make ohmic contact with each region through the contact hole. Incidentally, in FIG. 2, the shaded portion indicates the contact portion.

In this way, an NPN transistor element (
2) An NPN transistor element (5) as a protection element is formed in the island region (b). The collector electrode ring and the transistor element (5) are in ohmic contact with the collector contact region of the transistor element (2).
A collector electrode (c) in ohmic contact is connected to the collector contact region 62η.

Further, an emitter electrode (c) in ohmic contact with the emitter region (g) of the transistor element (2) and an emitter electrode ring in ohmic contact with the emitter region Q of the transistor element (5) are connected. Incidentally, the base electrode powder is in ohmic contact with the base region (2) of the transistor element (2) to take out the electrode. Further, no electrode is taken out from the base region Qη of the transistor element (5), and the base is made into a 70-Ting.

The emitter electrode) and the collector electrode ring are connected to the pads (3) (3), respectively, and the pads (3) (3) are connected to the pads (3) (3), respectively.
) are connected to external lead terminals (4) (4)K using bonding wires (6) (6), and the collector and emitter of the transistor element (2) are connected to the external terminals, respectively.

That is, as shown in FIG. 1, the collector and emitter of a transistor element (5) serving as a single storage element are connected in parallel between the collector and emitter of the transistor element (2).

Now, in the present invention, normally, an input signal is passed from an external lead terminal (4) to a pad (3) to a transistor element (
2). In other words, since the base of the transistor element (5) is floating, the transistor element (5) as a protection element has a floating base.
) does not have an input signal flowing to it. Therefore, it does not affect the circuit operation in any way.

By the way, when a surge voltage is applied to an external terminal, the transistor element (2) and the transistor element (5) as a protection element share the surge voltage, and the transistor elements (2) and (5) mutually prevent the surge. Absorbs voltage. Therefore, unlike the conventional protection device that absorbs surge voltages alone, transistor elements (2) and (5) mutually absorb surge voltages, which substantially increases the junction area of the PN junction, and This increases the withstand voltage and prevents damage to the device.

The transistor element (2) and the transistor element (1) as a protection element should be elements with the same PN junction area and the same level of electrostatic breakdown resistance, and it is preferable that the size of the transistor element (2) and the transistor element (1) as a protection element be larger. . This means that if the electrostatic breakdown capacity of one element is smaller than the other, that element will be destroyed, but if both are of the same level,
Theoretically, since the bonding area doubles against electrostatic damage, the breakdown resistance also doubles.

Next, a semiconductor integrated circuit device (A) according to the present invention and an NPN
A type transistor (2) and an NPN type transistor (O) as a protection element were prepared, and a surge voltage was applied to the external terminal of each using the apparatus shown in FIG. 4 (1), and the breakdown voltage of each was measured.

Incidentally, the device according to the present invention is an NPN type transistor element (
2) The PN junction area between the base and emitter of the part is 300
μm2, NPN transistor element as a protection element (
5) The PN junction area between the base and emitter of the part is 300
It is μm2. Also, the base of the NPN transistor■
The PN junction area between the emitters is 300 μm2, and the PN junction area between the base and emitter of the NPN transistor (Q) is 300 μm.

The measurement was carried out by charging the capacitor () from the power supply, and by switching the capacitor () to the semiconductor device to measure the surge voltage, and by varying the applied power supply voltage to measure the voltage at which it would break down. The results are shown in Table 1.

Table 1 In addition, the power supply voltage was varied up to 800μ during measurement, so
In the above table, a value of 800 Å or more indicates that the element was not damaged even when a surge voltage of 800 Å was applied.

As is clear from Table 1, according to the present invention, a transistor element (2) and a transistor element (5) as a protection element
It can be seen that by mutually absorbing surge voltage, the breakdown voltage is improved compared to the conventional device, and electrostatic breakdown can be prevented. Further, in the present invention, since the transistor element (2) used as an input transistor etc. and the transistor element (5) as a protection element are electrically separated, the bias condition of the transistor element (2) etc. The transistor element (5) has no influence. Therefore, it is possible to precisely control Vmm, etc. of the transistor element (2), and especially when there are multiple transistor elements whose rise ratios are the same as that of the transistor element (2), the control is particularly difficult. It has the advantage of being easy to use.

(f) As described in detail, the semiconductor integrated circuit device according to the present invention can provide sufficient protection against forward and reverse surge voltages without affecting normal circuit operation.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the structure of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a plan view showing essential parts of the present invention, and FIG. 3 is a cross-sectional view taken along the line ■--■ in FIG. FIG. 4 is a circuit diagram of an apparatus for measuring electrostatic breakdown voltage, and FIG. 5 is a plan view showing the configuration of a conventional semiconductor integrated circuit device. (1)...Semiconductor substrate, (2)...Transistor element, (3)...Pad, (4)...Lead terminal,
(5)...transistor element as a protection element,
(G)...Semiconductor substrate, (B)...Epitaxial layer, (6)...Isolation region, (to) α→...Island region, (13a) (14a)...Collector region, Qf9
Q71...Base area, (To) ◇Emitter area, 翰(B)...Collector contact area. Applicant: Sanyo Electric Co., Ltd. and 1 other representative: Patent attorney: Shizuo Sano

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device including at least one NPN transistor element in a semiconductor substrate, and in which the collector and emitter of the transistor element are connected to external terminals, the island region in which the transistor element is formed is electrically The island area separated into the collector area is the collector area.
A P-type base region is formed in this island region, and an N-type emitter region is formed in this base region to form an NPN-type transistor element as a protection element. area,
By connecting the emitter regions to the emitter regions, between the collector and emitter of the transistor element,
A semiconductor characterized in that the collector and emitter of the transistor element serving as the protection element are connected in parallel so that when a surge voltage is applied between the external terminals, both the transistor elements mutually absorb the surge voltage. Integrated circuit device.