JPS60249568A - Polishing of semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce cracking or chipping of semiconductor wafer considerably in such polishing method where a semiconductor wafer is inserted into a carrier then pressed by upper and lower surface plates and rotated, by placing buffer material between the wafer and the carrier. CONSTITUTION:Buffer material 13 such as soft polyvinyl-chrolide, wood (cork), felt, rubber, Teflon, mica, etc. is employed while profiling the shape of semiconductor wafer W. When polishing a circular wafer, for example, a planar ring of soft polyvinyl-chloride smaller than the bore diameter of an outercircumferential carrier C having the innercircumference larger than the diameter of the wafer W and the thickness thinner than the finish thickness of the wafer W and approximately same with the thickness of the carrier C is employed as the buffer material 13 and inserted into the bore section of carrier C then the wafer W is inserted into said planar ring. When polishing, the planar ring is repelled by the carrier C to perform spiral motion but only the inside of planar ring and the outercircumference of wafer W will collide resulting in reduction of impact to be applied onto the wafer.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to improvements in a method for polishing both sides of semiconductor wafers.

(Prior Art) In recent years, with the advancement of microfabrication technology such as ultra-LSI, the demand for surface quality accuracy for semiconductor wafers has been increasing. This requirement does not simply depend on the length of a silicon wafer, but also requires mirror-finished wafers with peripheral processing for good flatness of substrates for compound semiconductors, such as GaA and I/C.

In order to meet these demands, crystalline material inogots are manufactured by: (1) one rising process to cut the semiconductor wafer into pieces; (2) beveling process to chamfer the semiconductor wafer and its periphery into a predetermined shape; and (3) lapping (rough) to make the thickness even. Polishing) (
4) Etching to improve surface precision and remove process-distorted layers (5) Polishing to make the semiconductor wafer surface mirror-like (
It is manufactured through various processing steps (finish polishing).

At this time, the polishing methods applied to rough polishing and final polishing include (1) machining with an adhesive such as semiconductor wax or wax;
Attaching to the teng plate is a single-sided polishing method in which it is pressed against a rotating surface plate and polished.

(2) The semiconductor wafer is inserted into a carrier interposed between the upper surface plate and the lower surface plate without using any adhesive such as wax,
Two methods have been applied: a double-sided polishing method in which polishing is performed by pressing between two surface plates and rotating them.

However, as the diameter of semiconductor chips increases, 710 mm is increasingly required, and the single-sided polishing method (1) uses all adhesives such as wax, so it is expensive due to uneven thickness. Various problems such as the inability to process flatness, (2) adhesion and peeling of semiconductor wafers are troublesome and difficult to automate, and (3) cleaning of semiconductor wafers after polishing is difficult. Because of this, the adoption of double-sided polishing methods with high dimensional accuracy is increasing.

(Problems to be Solved by the Invention) The double-sided polishing method is usually carried out using a double-sided polishing machine as shown in FIGS. 1 and 2.

Polishing sheet 2 on each of the upper surface plate 1 and lower surface plate 5 that can be rotated
・Attach the fitting gear 12 on the same side so that it fits into the sun gear 5 and internal gear 6.
t-'If a plurality of carriers C (3 in the example of Fig. 2)
The semiconductor wafer to be polished is inserted into the perforated part of the carrier C (in the example of FIG. 2, four semiconductor wafers per carrier), and the upper surface plate 1 is gradually lowered. Squeeze the entire semiconductor wafer.

At this time, the semiconductor wafer thickness is greater than the carrier thickness, and a chemical polishing liquid (abrasive grains W in the case of rough polishing) is applied between the upper and lower surface plates while gold is flowing.
When the sun gear 5 and the internal gear 6 are fully rotated by the shafts 8 and 10, the carrier C fitted thereon completes its rotation and revolution, and the semiconductor wafer W is pushed by the carrier C and moves spirally between the surface plates. rotates around axis 7. Axis lower surface plate 3? , and the polishing surfaces of the surface plate and the semiconductor wafer W are rubbed against each other and polished.

As described above, the double-sided polishing method can polish without using adhesives such as wax, so it has the advantage of having good flatness and being able to polish many wafers at once.
It has the disadvantage that there are many I n % defects. This tendency is particularly noticeable in brittle materials such as compound semiconductors such as GaAO and ■nP, which are softer than 81 and rich in interosseous properties.

The cause of this is that the semiconductor wafer w'2 is placed in the perforated part of the carrier C.
In order to insert and attach, there are some gears between them, and during polishing, the semiconductor wafer W is subjected to (1) frictional force due to the rotation of the upper and lower surface plates that are pinched, (2) hole drilling of the carrier C that rotates and revolves. It moves in a limited plane due to the impact force caused by repeated collisions between the hollow part and the surrounding area of the semiconductor. The carrier C receives the driving force from the sun gear 5 and the ink null gear 6 and regulates the movement of the semiconductor sea urchin.It is thinner than the semiconductor wear, so it is made of a material that has excellent strength and is difficult to deform.It is usually made of blue steel (steel). /res) or glass epoxy, etc. are used.

Therefore, chipping occurs around the wafer due to the collision between the semiconductor chip W and the carrier C, and furthermore, the microscopic fragments generated thereby cause scratches and cracks on the wafer.

Decrease in polishing yield due to cracking and chipping of highly precisely processed semiconductor wafers increases the cost of semiconductor wafers and poses a major problem in production.

The present invention has been devised to solve the above-mentioned problems, and its entire purpose is to provide an improved double-sided polishing method with less chipping.

(Means for Solving the Problems) The above object is to provide a method for polishing a semiconductor wafer by inserting it into a carrier and rotating the semiconductor wafer while being held under pressure by an upper surface plate and a lower surface plate. This is achieved by a method for polishing semiconductor wafers, which is characterized in that polishing is performed with a buffer interposed between carriers. In other words, the cause of cracks and chips is the repeated impact between the hollow area and the holed area of the carrier during polishing, so a cushioning material with appropriate elasticity is inserted into the gap between them.
kfa is intended to be summed. As this buffer material, materials such as soft vinyl chloride, wood (cork), felt, rubber, Teflon, mica, etc. are used, all of which are configured in an arbitrary shape depending on the shape of the semiconductor wafer.

For example, if a circular semiconductor sea urchin is to be completely polished, Figure 6 (
As in a) and (1)), the outer periphery is smaller than the carrier hole diameter and the inner periphery is thicker (preferably 1 to 2 times larger) than the semiconductor wafer diameter, and the thickness is the same as that of the semiconductor wafer to be polished. A flat ring made of soft vinyl chloride, which is thinner than the finished thickness and approximately equal to the carrier thickness, is used as a cushioning material and inserted into the carrier hole, and a semiconductor evaporator is inserted into the flat ring.

When it is polished, it moves in a spiral motion against the seat in the flat ring, but the semiconductor urchin inside it also comes into contact with the flat ring, and is repeatedly polished by collisions with the metal.

At this time, what collides is the inside of the flat ring and the outer periphery of the semiconductor wafer, and due to the dimensional freedom of the flat ring and the elasticity of the material, the impact force applied to the semiconductor wafer is small, causing splitting and chipping. becomes less likely to occur.

As explained above, the iL counterfeit is a flat ring, but in this case, the structure of the cushioning material is (1) integral with the carrier, and the semiconductor sea urchin is in free contact (Fig. 3) (2) ) One that has an integral structure with the carrier and is in contact with the P half-integral wafer in the same shape (Fig. 5) (3) One that is in free contact with the carrier and also in free contact with the semiconductor wafer (Fig. 6) ( 4) One that is in free contact with the carrier and has the same shape and contact with the wafer (Figure 7) (5) In (2) and (4) above, contact at the corner of the semiconductor wafer should be avoided. Various embodiments are possible, such as one in which only the flat part is in contact (Fig. 8), but the point is that the semiconductor sea urchin, which is easily damaged,
・In order to avoid the impact of the hard carrier, polishing is performed with a cushioning medium in between, resulting in a high yield of semiconductor wafers with high precision.

(Example of the present invention) Next, examples of the present invention will be described.

Table 1 ij The occurrence of cracks and chips was investigated when circular and D-shaped GaAs single crystal wafers of 50 myφ were subjected to double-sided lapping, etching, and double-sided boring.

First, test number 1.2 in Table 1 will be described.

Figure 3 shows GaAe with a diameter of approximately 50Wnφ and a thickness of 420μm.
It is a top view of the carrier used when circular sea urchin/tsuworubbing.

Carrier C uses glass epoxy with a thickness of 500 μm,
Inside it, there are 11 holes for inserting semiconductor wear, hole diameter 60 φ
, 4 holes are drilled symmetrically, and a flat ring 134 of soft vinyl chloride is formed along the inner circumference of the perforated part, width 3fm, thickness 300μ,
Attach it to carrier C using m'@adhesive so that it becomes an integral structure.

The thickness of this cushioning material is the same as the carrier thickness, but it is desirable that the thickness be greater than or equal to that of a semiconductor wafer. Eight of these carriers were set on a double-sided lapping machine, and 52 pieces of the GaAe single crystal sea urchin were inserted into each hole.

FIG. 4(a) shows that in this state, abrasive liquid is supplied, the upper surface plate is lowered, and the surface of the semiconductor wafer is 120 mm thick. It is a sectional view at 9 o'clock when pressurized so that a pressure of 7 cm2 is applied. In the figure, the thickness of the Wt semiconductor wafer was approximately 420 μm, and at was the carrier thickness = the thickness of the buffer material (soft vinyl chloride) − 300 μm. The abrasive grains 14 enter the upper and lower surfaces of the semiconductor wafer and the carrier, as well as the gap 15 between the side surface of the semiconductor wafer and the cushion ring. In the above condition, the upper surface plate - 50° clockwise
rpm, lower surface plate = 4 orpm counterclockwise, carrier revolution 5 rotations clockwise, semi-exclusive gear wrapping to thickness f39opm and occurrence of cracks and chips was observed. After that, complete etching was performed to remove machining distortion 30 ~35μ
Using a carrier having the same structure except for the T-shape, a polishing sheet 2.4 was pasted on the upper surface plate 1 and the lower surface plate 5, respectively, and mechanical and chemical polishing was carried out using a double-sided polisher. As a result, it was confirmed that the polishing amount was reduced by half compared to Test No. 5 conducted under the same polishing conditions using the conventional method.

For a 10,000-round semiconductor wafer, as shown in Figure 7 (eL), the same thing can be done using a cushioning material that has a circular outer part, a wafer-shaped inner part, and a slight gap between it and the semiconductor wafer. Tested on abrasive strips.

The results are shown in Table 1 Test No. 6.4.

According to this figure, it can be seen that the number of cracks and chips is greatly reduced compared to the conventional method of Test No. B.

FIG. 4 (1)) is a sectional view during wrapping in this case, and the cushioning material can also move freely from the carrier.

Table 1 Semiconductor wafer polishing conditions and results (effects of the invention) As described in the above examples, the present invention makes it possible to significantly reduce cracks and chips in semiconductor wafers.

In the examples, circular and D-type GaAS were used for comparison, but the semiconductor wafer shape was rectangular.

In semiconductor wafers with corner edges such as D-shaped pedestal formation, chipping occurs concentrated at the corner edges, so using a cushioning material as shown in FIG. 8 can be expected to have an even greater effect. Furthermore, it can be used for brittle materials such as semiconductor wafers other than GaAe wafers, and is expected to be effective.

[Brief explanation of the drawings] Figure 1 is a cross-sectional view of the double-sided polishing machine. Figure 2 is a top view of the lower surface plate of the double-sided polishing machine. Figure 3 and subsequent figures relate to the present invention. Top view Figure 4 (a
) is a sectional view where the buffer is integrated with the carrier; (b) is a sectional view where the buffer is separated from the carrier. Figure 5 is a sectional view where the buffer is integrated with the carrier and whose internal shape matches the wafer shape. Top view Figure 6 is a top view of an example in which the buffer is separate from the carrier and has a circular interior so that it can move freely with the wafer ((a) is for a circular wafer; (b) is for an orientation flat) In the case of a circular wafer〃(C) is the case of a trapezoidal wafer〃(d) is the case of a D-shaped wafer Figure 7 is a top view when the buffer is separate from the carrier and the inside matches the wafer shape〃 (a) is for a circular wafer; (b) is for a circular wafer with an orientation flat; (C) is for a trapezoidal wafer; (d) is for a D-shaped wafer. ) is a top view of an improved example. In the diagram 1. Upper surface plate 2. Polishing sheet 5. Lower surface plate 4. Polishing sheet 5 To sun gear Internal gear Z Center shaft 11 to 9.1C1, hollow shaft 11, carrier hole 12. Carrier fitting gear 1S buffer 14.
Grinding grain 15, Gap between wafer and cushioning material 16 Gap between carrier and cushioning material C Carrier W Wafer agent 1) Akira agent Ryo Hagiwara - Figure 2 Figure 3 Figure 4 ((1) Figure 6

Claims (4)

[Claims] (1) In a method of polishing by inserting a semiconductor wafer into a gold carrier and rotating the semiconductor wafer with pressure applied to the entire upper surface plate and lower surface plate, a buffer is placed between the semiconductor wafer and the carrier. A polishing force method for semiconductor wafers characterized by intervening polishing. (2) The method according to claim 1, wherein the buffer has an integral structure with the carrier. (3) The method according to claim 1, wherein the semiconductor wafer insertion portion of the buffer conforms to the shape of the semiconductor wafer. (4) The carrier has a circular hole, and a buffer material having a circular outer periphery and a circular inner periphery or matching the shape of a semiconductor wafer is inserted into the circular hole independently of the carrier for polishing. The method described in paragraph 1.