JPS60248085A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To obtain an optimum reference voltage without noise component by providing a voltage comparator using an output of a switch circuit as a reference voltage and binary-coding an input signal and extracting it. CONSTITUTION:When a framing code FC in an output of a comparator 2 is detected, a framing code (e) is extracted, a capacitor C3 is charged by an output (f) of a D FF14 and an input voltage of a comparator 12 rises. When this voltage exceeds the reference voltage of a reference voltage source 15, an output of the comparator 12 goes to H level, then a switch 11 is thrown to the position of a terminal A, and an output of an LPF10 is fed to the comparator 2. When a character data is incoming in succession to a clock run in signal CK and a framing code FC, a binary-coding signal using an output of the LPF10 as a reference is extracted from the comparator 2. In this case, the LPF10 absorbs the noise component and more optimum reference voltage is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a reference voltage generation circuit, which is used in, for example, a television receiver that receives teletext broadcasting, and is used to generate a reference voltage that is not affected by disturbances such as noise. The purpose is to provide a circuit for extracting data.

BACKGROUND OF THE INVENTION In recent years, as shown in FIG. 2(B), a technique has been developed in which character data D is inserted into the vertical retrace period of a video signal to perform teletext multiplex broadcasting. In the video signal of such teletext broadcasting, there is a 7-raming code FC (FC) before the character data D.
When this framing code FC is detected, a framing code detection pulse e ((E) in the same figure) is obtained to synchronize the data D byte.

In this case, generally, the video signal is compared with a reference voltage by a voltage comparator, IJ and rOJ of the signal are determined, and character data D is extracted as a binary signal.

FIG. 3 shows a circuit diagram of an example of a conventional reference voltage generation circuit used to obtain the above-mentioned binary signal.

In the same figure, the video signal input to the terminal 1 is supplied to the voltage comparator 2, where it is compared with the reference voltage from the reference voltage power supply 3, and the signal becomes "1".

"0" is determined, and the character data D is extracted as a binary signal 9. This device has a simple circuit and can obtain an optimum reference voltage by adjusting the reference voltage power supply 3.

FIG. 4 shows a circuit diagram of another example of the conventional reference voltage generation circuit. In the same figure, the video signal input to terminal 1 is supplied to low-pass filter 4, where clock run-in signal G
K (FIG. 2(C)) is attenuated and supplied to the switch 5. On the other hand, the sampling signal d that entered terminal 6 ((D) in the same figure)
, a signal that is at H level only during the clock run-in signal CK period) is supplied to the switch 5 as a switching control signal to turn on the switch 5.

When the switch 5 is turned on, the capacitor C1 is charged with the voltage during the clock run-in signal CK period, and is applied to the voltage comparator 2 as a comparison voltage.

A comparator 2 compares the voltage of the video signal G with a reference voltage and extracts a binary signal g.

In this case, since the reference voltage level is varied in accordance with the conditions of the incoming video signal, the optimum reference voltage can always be obtained without adjusting the reference voltage as in the case shown in FIG.

The problem that the invention aims to solve, as shown in Figure 3, requires adjusting the reference voltage every time the conditions of the video signal change, making the operation cumbersome.

Furthermore, in the case shown in Figure 4, if the charging time constant of the capacitor C1 is made large, the battery cannot be charged to the desired potential only during the clock run-in signal GK period, and if the charging time constant of the capacitor C1 is made small, the capacitor cannot be charged to the desired potential. There is a problem in that it is difficult to select the charging/discharging time constant of the capacitor C1, such as not being able to maintain the voltage at the same level for one horizontal scanning period.

Also, in the case shown in Figure 4, the timing of the sampling signal d is the second.
If the timing deviates from the normal timing as shown by the broken line in FIG.

Furthermore, in the case shown in FIG. 4, the switch 5 is turned on by the sampling signal d regardless of whether or not the character data 0 is superimposed during the horizontal scanning period. There is a problem in that the voltage during the scanning period is not always charged, and it is not possible to obtain the optimum reference voltage due to the influence of the video signal portion b', noise, etc.

Means for Solving the Problems and Their Effects The present invention provides a first low-pass filter to which an input signal superimposed with a clock run-in signal, a framing code, etc. is applied and which attenuates the clock run-in signal; a first switch circuit that is turned on during the presence of the signal and charges the output of the first low-pass filter to a first capacitor connected to the output terminal thereof; and an input to the output terminal of the first switch circuit. a connected buffer amplifier having a high input impedance and a low output impedance; a second switch circuit that is turned on and off by a first control signal and charges a second capacitor with the output of the buffer amplifier during the on period; The input of the buffer amplifier is connected to the output terminal of the buffer amplifier, the other input is connected to the output terminal of the second switch circuit, and the output of the buffer amplifier and the output of the second switch circuit are selected and input by a second control signal. a third switch circuit, one input of which is supplied with the input signal, the other input of which is supplied with the output of the third switch circuit; A voltage comparator that converts the output into a value and extracts it, a shift register that sequentially captures the output of the voltage comparator and parallelizes the output of the voltage comparator and extracts it, and a framing code detection that detects the presence or absence of the above-mentioned framing code in the output of the shift register. the first control signal which is set by the output of the circuit and the framing code detection circuit, is reset by a horizontal synchronizing signal or a signal equivalent thereto, and turns on the switch circuit 'jB2 from setting to reset. a state holding circuit that outputs
The second control is supplied with the output of the state holding circuit, selects the output of the buffer amplifier when the framing code is not detected, and selects the output of the second switch circuit when the framing code is detected. The above-mentioned problem is solved by a configuration including a switch control circuit that supplies a signal to the third switch circuit, and one embodiment thereof will be described below with reference to the drawings.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention. In the figure, the same components as in FIGS. In the figure, the voltage charged in the capacitor C1 is applied to a buffer amplifier 7 having a high input impedance and a low output impedance, where it is taken out as it is and supplied to an analog switch 8. The analog switch 8 is a framing code detector 9 which will be described later.
The configuration is such that it remains on for a period from when the 'C framing code FC is detected until the horizontal synchronizing signal a (Fig. 2 (A)) is detected, so that the output of the buffer amplifier 7 ( That is, the charging voltage of capacitor c1) is charged to capacitor C2.

The output of the switch 8 is supplied to a low-pass filter 10, where the voltage charged in the capacitor C2 is supplied to the switch 11 together with the output of the amplifier 7 after passing through several field fractions W4. The switch 11 is a voltage comparator 12 which will be described later.
The period from when the 7-raming code FC is detected until the horizontal synchronizing signal a is detected by the output of the terminal A (the period during which the character data D is being sent) is connected to the terminal A, and the other period is connected to the terminal port. The output of the switch 11 is supplied to the voltage comparator 2.

14 is a D-type flip-flop which receives the framing code detection pulse e which is the output of the framing code detector 9.
(Fig. 2 (E)) is used as the clock input, and the horizontal synchronization signal a
((A) in the same figure) operates as a clear input.
As shown in FIG. 2 (F>), the six outputs f are set to the L level when the framing code detection pulse e is supplied, and set to the H level when the horizontal synchronizing signal a is supplied. The signal [ is supplied to the switch 8. The switch 8 is turned on only during that L level period.

On the other hand, the signal f is supplied to the base of the transistor Tr,
As a result, the transistor Tr is turned on during the L level period of the signal r and turned off during the H level period.

The transistor Tr has a resistance R+ when the signal f is at L level.
, R2, and a constant current determined by the voltage and the resistance value of the resistor R3. Capacitor C3 is connected to transistor T[
A current-voltage conversion capacitor that is charged when the
Resistor R4 becomes capacitor C when transistor Tr is turned off.
It is a resistor that discharges the electric charge that has been charged in the 3. The discharge time constant of the capacitor C3 and the resistor R4 ranges from several fields to several tens of fields, and is selected depending on the transmission state, reception state, etc.

The charging current through the resistors R+, R2, R3, and capacitor C3 is set so that it exceeds the identification level of the voltage comparator 12 when the framing code FC is detected several to several tens of times in succession.

Resistor Rs and capacitor C4 are low-pass filters for reducing sudden changes in voltage occurring across capacitor C3.

Immediately after the power switch is turned on or the channel is changed, the capacitor C3 is in a discharge state, and the output of the comparator 12 is at L level. This causes switch 1
1 is connected to the terminal port, and the output of the buffer amplifier 7 is supplied to the comparator 2. When the clock run-in signal GK and the framing code FC are input to the terminal 1, the comparator 2 outputs a binary signal using the output of the amplifier 7 as a reference voltage.

When the framing code FC in the output of the comparator 2 is detected, the framing code FC is taken out, the capacitor C3 is charged by the output f of the D-type flip-flop 14, and the input voltage of the comparator 12 is increased. When this voltage exceeds the reference voltage of the reference voltage power supply 15, the output of the comparator 12 becomes H level, thereby connecting the switch 11 to terminal A and supplying the output of the low-pass filter 10 to the comparator 2. When character data D comes in following clock run-in signal CK and framing code FC, comparator 2 outputs low-pass filter 1.
A binarized signal with the output of 0 as a reference voltage is extracted.

In this case, since the capacitor CI is charged with the voltage of the clock run-in signal GK period regardless of whether or not the character data 90 is superimposed in the horizontal scanning period, the video signal portion is charged especially during the period when the character data D is not used. b' is affected. However, since the capacitor C2 is always charged with the voltage during the horizontal scanning period on which the character data D is superimposed, it is not affected by the video signal portion b'. As a result, an optimal reference voltage can be obtained compared to that of the conventional circuit, and characters can be read more accurately.

Further, noise components can be absorbed by the low-pass filter 10,
The lowest reference voltage can be obtained.

Note that when a channel switching operation is performed after the synchronized state, the electric charge stored in the capacitor C3 is discharged through the resistor R4, resulting in an asynchronous state, and the mode automatically returns to the optimum reference voltage generation mode.

In addition, the sensitivity of synchronous state detection and asynchronous state detection is
It can be freely set by appropriately selecting the respective constants of resistors R+, R2, R3, R4, and capacitor C3.

Furthermore, by operating an indicator using the output of the comparator 12, the reception status of character data can be displayed to the receiver. It is also possible to adopt a configuration in which the sampling clock on the receiving side is controlled to match that on the sending side when continuity is guaranteed.

Effects As described above, the reference voltage generation circuit according to the present invention has a first voltage generator to which an input signal on which a clock run-in signal, a framing code, etc. are superimposed is applied, and which attenuates the clock run-in signal.
a first switch circuit that is turned on during the presence of the clock run-in signal to charge the output of the first low-pass filter to a first capacitor connected to its output; Turned on by a buffer amplifier with high input impedance and low output impedance connected to the output end of the first switch circuit and the first control signal.

During the off period, the output of the buffer amplifier is switched to the second
a second switch circuit that charges the capacitor of the buffer amplifier; one input is connected to the output terminal of the buffer amplifier; the other input is connected to the output terminal of the second switch circuit; a third switch circuit which selects the output and the output of the second switch circuit; one input is supplied with the input signal; the other input is supplied with the output of the third switch circuit; A voltage comparator that binarizes and takes out the input signal using the output of the switch circuit as a reference voltage, a shift register that sequentially takes in the output of the voltage comparator and parallelizes the output of the voltage comparator and takes out the output, and an output of the shift register. a framing code detection circuit that detects the presence or absence of the above-mentioned framing code; and a framing code detection circuit that is set by the output of the framing code detection circuit and reset by a horizontal synchronization signal or a signal equivalent thereto; a state holding circuit that outputs the first control signal to turn on the circuit; and a state holding circuit that is supplied with the output of the state holding circuit, selects the output of the buffer amplifier when the framing code is not detected, and selects the output of the buffer amplifier when the framing code is detected. When the second control signal selects the output of the second switch circuit, the third control signal
Since the reference voltage of the voltage comparator automatically changes according to the signal conditions, there is no need to adjust the reference voltage as in conventional circuits. Since the first and second capacitors are used, the same voltage level can be maintained for a sufficient horizontal scanning period, and the charging/discharging time constant of the capacitors can be easily selected compared to conventional circuits. The optimal reference voltage can be obtained even if the timing of the sampling signal indicating the timing deviates from the normal timing, and since the reference voltage is obtained only during the horizontal scanning period in which the framing code is detected, it is not possible to display images like the conventional circuit. It has the advantage of being able to obtain an optimal reference voltage that is not affected by the external signal part or noise.

[Brief explanation of the drawing]

FIGS. 1 and 2 are circuit diagrams of one embodiment of the circuit of the present invention and signal waveform diagrams for explaining its operation, and FIGS. 3 and 4 are circuit diagrams of each side of the conventional circuit. 1... Video signal input terminal, 2, 12... Voltage comparator, 4, 10... Low pass filter, 5, 8.11...
...Analog switch, 6...Sampling signal input terminal, 7
...Buffer amplifier, 9...Framing code detector, 13...Shift register, 14...D-type flip 70 tube, 15...Reference voltage power supply, 01-C4.
...Capacitor, Tr...Transistor, R1-R5
···resistance.

Claims (1)

[Claims] (1) A first low-pass filter to which an input signal superimposed with a clock run-in signal, a framing code, etc. is applied and which attenuates the clock run-in signal; a first switch circuit that charges the output of the first low-pass filter to a first capacitor connected to its output; and a high input impedance and low a buffer amplifier with an output impedance, a second switch circuit that is turned on and off by a first control signal and charges a second capacitor with the output of the buffer amplifier during the on period; a third switch connected to the output terminal, the other input of which is connected to the output terminal of the second switch circuit, and which selects and inputs the output of the buffer amplifier and the output of the second switch circuit according to a second control signal; a switch circuit, one input of which is supplied with the input signal, the other input of which is supplied with the output of the third switch circuit, and the input signal is binary-valued with the output of the third switch circuit as a reference voltage. a voltage comparator that sequentially takes in the outputs of the voltage comparators and parallelizes the outputs of the voltage comparators and takes them out; and a framing device that detects the presence or absence of the above-mentioned framing code in the output of the shift register. The first switch circuit is set by the output of the code detection circuit and the framing code detection circuit, and is reset by the horizontal synchronization signal or a signal equivalent thereto, and turns on the switch circuit in box 2 from the setting to the reset.
a state holding circuit that outputs a control signal; and a state holding circuit that is supplied with the output of the state holding circuit, selects the output of the buffer amplifier when the framing code is not detected, and selects the output of the buffer amplifier when the framing code is detected; A reference voltage generation circuit comprising: a switch control circuit that supplies the second control signal for selecting an output of the circuit to the third switch circuit. - The second switch circuit has a second low-pass filter to which the terminal voltage of the second capacitor is applied and whose cutoff frequency is set to several fields to several tens of fields of the video signal. The reference voltage generation circuit according to claim 1, characterized in that: ■ The switch control circuit includes a constant current switch that is turned on and off by the output of the state holding circuit, a third capacitor that is charged by the constant current switch and performs current-voltage conversion, and a circuit connected in parallel with the third capacitor. A discharge resistor connected to the capacitor, a third low-pass filter connected to a terminal of the third capacitor, and a voltage level determination circuit that determines the output level of the third low-pass filter. A reference voltage generation circuit according to claim 1 or 2.