JPS60247971A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit the generation of hot carriers without lowering channel currents by forming a high electric-field section in a region having impurity concentration lower than other drain sections and inducing channel currents into a high impurity concentration region positioned around said region. CONSTITUTION:A gate 8 is formed, and As ions are implanted to shape high- concentration N type source-drain regions. A side wall 9 consisting of CVD SiO2 is formed, and B<+> ions are implanted in order to lower the concentration of one parts of the high-concentration N type regions. A contact hole 10 is shaped, As ions are implanted in high concentration, and a substrate surface section in a drain is changed into an N<+> region. There are N<-> regions 11 escaping from the implantation of As ions so as to be surrounded by the N<+> region at that time. Desired structure is obtained through annealing and an Al wiring process.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a transistor (Tr) used in an MIS type integrated circuit.
) regarding the improved structure of

[Prior art and its problems]

As the density of integrated circuits increases, so-called hot
Deterioration of device reliability due to the Carrier problem has become a major problem.

FIG. 1 shows a cross-sectional view of an N-channel type transistor having a conventional structure. A channel current 2 consisting of electrons emitted from the source 1 is absorbed into the drain 4 while being controlled by the gate 3 . However, as elements become finer due to increased circuit density, a region 5 (marked with ■) with a high electric field is generated in the drain region, and when the channel current passes through the high electric field region, a so-called impact ionization phenomenon occurs. As a result, a hot carrier consisting of a large amount of electron-hole pairs is generated. These electron and hole pairs are trapped in the gate insulating film 6, or flow through the substrate and locally fluctuate the potential of the substrate, deteriorating the characteristics of the device in various ways. This was a major obstacle to increasing the density of circuits.

A conventionally proposed improvement method for this problem is the LDD (Lighty Doped D) shown in Figure 2.
(rain) structure, the part 7 of the drain facing the channel is made into a low-concentration N-type diffusion layer, and the electric field in the region 5, where a high electric field was generated in the conventional structure, is lowered to improve the impact ionization rate. The aim is to reduce the If you use this LDD structure, you will definitely get a Hot Carri
The occurrence of er is reduced, but the reduction is typically by an order of magnitude. If the impurity concentration in the region 7 were further lowered in an attempt to further improve the effect, a large potential drop would occur due to the high resistance component of the low concentration impurity region 7, resulting in the disadvantage that a sufficient channel current could not be obtained.

[Purpose of the invention]

An object of the present invention is to provide a Tr tank structure that eliminates the drawbacks of conventional improvement proposals represented by the LDD structure and suppresses the occurrence of hot carriers without reducing the channel current.

[Summary of the invention]

The gist of the present invention is to realize a structure that prevents channel current from passing through the high electric field area inside the drain. That is, in the LDD structure, although it is possible to weaken the electric field inside the drain, , the channel current still passes through the high electric field part in the drain, so the H
o t Carrier has occurred. Furthermore, as described above, in this structure, the high resistance component deteriorates the performance of the element. Therefore, if the channel current avoids the high electric field portion, the occurrence of hot carriers should be drastically reduced. In the present invention, as a method of diverting the path of the channel current from the high electric field region, as shown in FIG. A method is used to induce the impurity into a high impurity concentration region, that is, a low resistance region.

〔Effect of the invention〕

The effect of the present invention is that the Hot E
This not only suppresses the generation of electrons, but also has the advantage that since the current passes through a low resistance region, there is almost no voltage drop inside the drain that would degrade device performance. In addition, surrounding the high electric field area inside the drain with a low concentration diffusion layer not only changes the channel current path, but also has the effect of relaxing the electric field itself in the high electric field area, which has the advantage of further reducing impact ionization. There is also. Next, the present invention will be explained in detail with reference to Examples.

[Embodiments of the invention]

In FIG. 4, after gate 8 is formed using a well-known technique, As is ion-implanted to form a heavily doped N-type region of the source φF rain. Next, a side wall 9 made of CVD 810° is formed using the well-known active ion etching (RIB) technique. time, 4th
The impurity concentration of the 1+ region in the figure is lXl0"c+a-'
, the n-region was I
High-concentration ions of s are implanted to make the drain substrate surface part a Y region.

At this time, the n- region 11 that was spared from the As ion implantation exists so as to be surrounded by the n+ region. At this time, an n- region is also left in the portion in contact with the element isolation region 12, but this region has nothing to do with the deterioration of the element characteristics. next,
After proper annealing and the well-known A/wiring process, the fourth
The desired structure as shown in Fig. d is obtained.

[Other embodiments of the invention]

Although the embodiment has been described above using an N-channel type Tr, it goes without saying that a P-channel type Tr has similar effects. In this case, the ion implantation of a) in FIG. 4 is B'', and the ion implantation of b) is r or As''.

The ion implantation in C) is B+.

On the other hand, in the above example, the high resistance region and the low resistance region are realized by the low concentration region and the high concentration region of impurities, but the present invention is not limited to this, and the high resistance region may be an insulator in an extreme example, and the high resistance region The resistance region may be a metal that functions as a drain, such as a silicide such as PT or W.

Further, in the above example, the high resistance region is surrounded by a low resistance overlay and an insulating film, but even if the structure is completely surrounded by the high resistance region 14 as shown in figure $5, exactly the same effect can be expected.

Furthermore, in the structure shown in Figure 4, sidewall leaving technology using RIB and ion implantation through contact holes were used;
It is sufficient that the impurity distribution is as shown in FIG. 4, and other methods are also acceptable.

By using the present invention, Hot Electron
It is possible to realize a Tr tank structure that minimizes the noise and does not reduce device performance, and further promotes higher density in future integrated circuits.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional MIS type transistor, Figure 2 is an LDD
3 is a sectional view of a Tr according to the present invention, FIG. 4 is a sectional view of an embodiment, and FIG. 5 is a sectional view of another embodiment. In the figure, 1...source, 2...channel current. 3...Gate, 4...Drain. 5...High electric field part, 6...Gate insulating film. 7...Low concentration diffusion region, 8...Gate. 9...CVD5 ioz side wall left by RIB. 10...Contact hole. 11...N- region, ]2... Element isolation region. 13... N- region, 14... High resistance region. 15...Low resistance region. Agent Patent Attorney Nori Keisuke Chika (and 1 other person) Figure 1 Figure 4 Request

Claims (1)

[Claims] The drain consists of a first region with high resistance and a second region with low resistance, and the first region is located in a high electric field inside the drain and is completely surrounded by the second region, or A MIS type semiconductor device characterized in that the MIS type semiconductor device is surrounded by a region and an insulating film.