JPS60247699A - Acoustic signal frequency conversion control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION When changing the frequency of an acoustic signal in real time, there is a fundamental problem that must be solved.

Since the memory capacity of the digital memory circuit is limited, and in order to faithfully reproduce the flow of the strength and weakness of the input signal, both the read side and the write side start scanning from the start address after scanning from the start address to the end address.

Frequency conversion in real time is obtained by changing the address change speeds on the write side and read side. The larger the conversion ratio, the greater the chance that the read address will overtake or be overtaken by the write address. If the frequency is converted in this state without any control, a considerable abnormal sound will occur in the reproduced sound.

The core of the problem lies in the fact that when the playback frequency is increased for a single acoustic signal, blank time periods occur periodically in the real-time sound signal, and conversely, when the playback frequency is lowered, the real-time sound signal Overlapping time periods occur periodically. A typical method to solve this problem is to replay and submerge the acoustic signals in the vicinity of blank time periods, and to skip over and delete the overlapping parts of overlapping time periods. has been widely adopted because it is relatively low cost and satisfies practicality.

However, in pursuit of good sound quality, the problem remains that if you listen to the sound repeatedly, you will notice abnormal sounds during the above-mentioned replay or skip times.

Circuits that change the frequency of acoustic signals are used in pitch-variable devices, etc., but the central problem lies in reducing this abnormal sound as much as possible.

Typical examples include a method in which the replay or jump joint is selected as the zero-crossing point of the acoustic signal, and a method in which the joint is not switched instantaneously but is switched gradually, which is called fade switching.

Although the reproduced sound quality is considerably improved by adding these measures, abnormal sounds remain depending on the specific musical instrument signal or the specific frequency signal.

It is theoretically extremely difficult to ideally perform this type of conversion in real time, and considering cost limitations, it is nearly impossible to achieve with currently available devices.

This project focuses on the fact that it has two independent systems of readout circuits, and by constantly detecting the phase difference between the two systems of playback signals and controlling the phase of one, it is possible to obtain good replay and skip seams. This method relates to an acoustic signal frequency conversion control method, and although it does not reach the ideal expected value for the problem, it can obtain sound quality that is even better than the current method.

A detailed explanation will be given below using the drawings.

FIG. 1 is a block diagram when the present invention is applied to a pitch variable device, which is an example of application.

100 is an input terminal for an audio signal; 101 is an analog-to-digital conversion circuit for digitally encoding the audio signal; 10
2 is an audio signal encoded by the output of 101. 11
0 is a digital memory, 111 is a digital memory control circuit, and 112 is a memory control signal line for address read/write of the digital memory, which is the output thereof.

113 is a memory write address generation circuit, 114 is an output signal selection determining circuit, and 115 is an output of 113, which will be referred to as a write address in the following explanation. 116
is the first read address, and 117 is the second read address. 120 is a basic clock generation circuit that generates basic signals for controlling peripheral circuits of the digital memory.

121 and 12 are basic signals for generating read addresses;
2 is the basic signal for writing address generation, 123 is the control signal for digital memory read/write timing and address switching, etc. 124 and 125
126 outputs a signal for synchronizing the digital memory output and the analog converter, and 126 outputs a signal for synchronizing the digital memory and the digital converter.

128 is a frequency conversion ratio setting circuit that determines the frequency ratio of the audio reproduction signal output to the audio signal input, and 129 is a control signal to the reference clock generation circuit. Generally, an acoustic signal frequency conversion circuit has a function consisting of the above blocks. 130 is a read signal line for the digital memory.

131 is a first analog-to-digital conversion circuit that converts a digital code into an analog signal. 132 is a first read address generation circuit, and its output will be referred to as a first read address in the following explanation. 133 is the output of the first digital-to-analog conversion circuit, and corresponds to the data at the first read address in the digital memory.

This signal will be referred to as a first reproduction signal in the following explanation.

134 is a second circuit that converts the digital code into an analog signal.
This is an analog-to-digital conversion circuit.

Reference numeral 135 denotes a second read address generation circuit, and its output will be referred to as a second read address in the following explanation.

136 is the output of the second digital-to-analog conversion circuit, and corresponds to the data at the second read address in the digital memory. This signal will be referred to as a second reproduction signal in the following explanation. 137 is a reproduction signal selection circuit that instantly or gradually switches between the first reproduction signal and the second reproduction signal;
4 is controlled by the output 118 of the output signal selection determining circuit.

140 is a phase difference detection circuit that detects the phase difference between the first reproduction signal and the second reproduction signal. 141 is a signal corresponding to the phase difference, and will be referred to as a phase difference feedback signal in the following explanation. 143 is an address difference control circuit between the first read address generation circuit and the second read address generation circuit, and is controlled by a phase difference feedback signal.

Then, it acts on the read address generation circuit on the side that is not selected by the output signal selection determining circuit 114, that is, the side that is not selected by the reproduction signal selection circuit, and reduces the phase difference between the first reproduction signal and the second reproduction signal. It works like that.

FIG. 2 is a diagram for explaining an example of the operation of a portion related to the present invention in the applied example of FIG. 1.

Generally, for an input of an arbitrary frequency of an arbitrary waveform with periodicity, the first reproduction signal is selected as the output in the current operating state, whether the frequency conversion is to increase or decrease the frequency. There are combinations of cases in which the first reproduced signal leads or lags the second reproduced signal.

In Figure 2, when the input waveform is relatively monotonous and the frequency is lowered by one, the first reproduced signal is currently selected as the output, and at time mt tφ the phase is delayed with respect to the second reproduced signal. A case will be described in which, if the first reproduction signal is not switched to the second reproduction signal by time tχ, the waveform becomes discontinuous at time tχ and an abnormal sound is generated. This state is one example among many combinations of cases, but since the operation in each case can be easily inferred from the following explanation, it is no different from the explanation of -membrane properties.

The horizontal axis in FIG. 2 is time. 200 is the write address, 201 is the first read address, 202 is the case when the feedback control by phase detection is working normally, and 203 is the second read address when the feedback control by phase detection is not working, respectively. Shows time transition.

204 is a point at which the first read address is overtaken, at which the write address and the first read address become the same value at time tχ. At time tφ, the difference between the first and second read addresses is one-half of the memory size, but this is done to make the diagram easier to understand and is generally an arbitrary value.

210 is the input acoustic waveform of FIG. 1 100;

211 is the first reproduction signal of 133 in FIG.

This waveform is similar to the input signal up to time tχ, but at this point the signal at the most recent time on the memory is momentarily transferred to the new signal that has just been written, so the first reproduction signal continues to be selected. Generally speaking, this point 212 of the reproduced signal is the second reproduced signal.

This waveform is discontinuous at time tφ as at 204 points. However, since the first reproduction signal is selected at time tφ, no abnormal sound is produced as the final output.

213 to 222 indicate states in which the phase difference between the first reproduced signal and the second reproduced signal decreases with time.

Reference numeral 231 indicates an example of the phase difference feedback signal 141 in FIG. In this case, it acts on the address difference control circuit to correct the phase delay amount equivalent to 213-222. 2
Reference numerals 41 to 244 are diagrams for explaining the operation of the reproduced signal selection circuit 137 in FIG. From the time when the phase difference between the first reproduction signal and the second reproduction signal disappears to tx, the first reproduction signal
The switching from the reproduced signal to the second reproduced signal is completed. 2
42 shows that the first side gradually decreases, and conversely, 243 shows that the second side gradually increases. Whether this change occurs instantaneously or gradually is not the essence of this proposal.

Since the second reproduction signal is completely selected at time tx, the discontinuous state at the overtaking point on the first side of 204 does not affect the final output. Therefore, a continuous signal 251.252.253 similar to the input appears at the audio reproduction signal output terminal 139 in FIG.

The above explanation describes a method in which the phase detection operation between the middle cylinder 1 reproduction signal and the 2nd reproduction signal is performed at the analog level.However, if it is performed at the analog level, the same result can be obtained even if it is performed at the digital code level using an equivalent method. It can be easily inferred that . It can be easily inferred that similar results can be obtained even if the reproduced signal selection circuit is operated at a digital level.

As described above, a first readout generation circuit and a first digital-to-analog conversion circuit corresponding thereto, a second readout address generation circuit independent of these, and a second digital-to-analog conversion circuit corresponding thereto are provided. The phase difference between the output on the first side and the output on the second side is detected, and the address is generated to eliminate the phase difference between the output on the first side and the second side by acting on the read address generation circuit on the side not selected as the final output. By performing differential control, the expected operation is automatically performed and good replay and interleaved seams can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of application of the present invention. FIG. 2 is an explanatory diagram of the operation of the present invention. June 1930 198 20, Ming name 壜傳4j石” Ogisuri U drunken detective 3,
Relationship with the case of the person making the amendment Patent applicant address (residence) Postal code 663 4, Agent 5, Date of amendment order 1920, Month, Day 6, Subject of amendment Attack, Sun Self-Print 7, Contents of Amendment Appendix 90

Claims (1)

[Claims] A first circuit for reading out the encoded acoustic signal written in the digital storage circuit and returning it to the original acoustic signal.
an analog-to-digital conversion circuit, a first read address generation circuit that generates the read address, and a second read address generation circuit that has the same function as the first digital-to-analog conversion circuit;
A digital-to-analog conversion circuit, a second readout address generation circuit that generates the readout address, a first reproduction signal that is the output of the first digital-to-analog conversion circuit, and a second reproduction signal that is the output of the second digital-to-analog conversion circuit.
an analog signal selection circuit having a function of instantly or gradually switching between the first and second reproduction signals, and a phase difference detection circuit that detects a phase difference between the first reproduction signal and the second reproduction signal;
an address difference control circuit having a function of causing the output of the phase difference detection circuit to act on a non-selected read address of the analog signal selection circuit to reduce the phase difference between the first reproduction signal and the second reproduction signal; Of the inputs of the above-mentioned analog signal selection circuit, the reproduced signal on the non-selected side is
An acoustic signal frequency conversion control method characterized in that an acoustic reproduction signal is obtained by matching the phase of the selected signal during mode selection.