JPS60246678A - Semiconductor nonvolatile memory - Google Patents

Abstract

PURPOSE:To enable programming at low voltage and low currents, and to obtain a nonvolatile semiconductor memory, which has the large efficiency of writing and is fitted to the increase of the degree of integration, by forming P type region in order to make injection-charge acceleration region steep only in the injection-charge acceleration region. CONSTITUTION:A selective gate electrode 15 and a floating gate electrode 14 are shaped in a channel region between a source region 12 and a drain region 13 in the surface of a P type semiconductor substrate 11 through gate insulating films 16, 17, and a control gate electrode 19 controls the potential of the floating gate electrode 14 through an insulating film 20. A high-concentration P type region 18 is formed only to the surface of the semiconductor substrate between the selective gate electrode 15 and the floating gate electrode 14, and an injection-charge acceleration region is shaped extremely steeply because the region 18 and both the electrode 15 and the electrode 14 hardly overlap. Drain voltage is applied effectively into the injection-charge acceleration region, thus enabling programming at low voltage and low currents.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a low programming voltage floating gate type semiconductor nonvolatile memory that can be highly integrated.

A conventional low program voltage floating gate type semiconductor nonvolatile memory that we have invented will be explained with reference to FIG.

An N-type source region 2I and a drain region 3 are provided in the surface portion of the P-type semiconductor substrate 1, and a first channel region L1 and a second channel region L1 are provided in the channel region between the source region 2 and the drain region 8. A channel region L2 is provided. mud 1
The surface potential of the channel region L1 is controlled by the potential of the selection gate electrode 5 provided through the gate insulating film 7. Further, the surface potential of the second channel region L2 is controlled by the potential of the floating gate electrode 4 provided through the gate insulating film 6. Further, the potential of the floating gate electrode 4 is controlled by the potential of the control gate electrode 9 which is capacitively coupled most strongly by the insulating N ILI Vc.

Therefore, when a high positive voltage is applied to the drain region 8 and the control gate electrode 9 with respect to the substrate 1, the surface potential of the second channel L2 becomes equal to the potential of the drain region 8. Therefore, when a voltage is applied to the selection gate electrode 5 such that the first channel region Kll flow flows, the source voltage and the drain voltage are applied to the region indicated by the arrow A where the first channel region L1 and the second channel region L2 intersect. A large surface box difference of one place, which is equal to the difference between Some of the electrons flowing out from source region 2 are
This large surface potential difference causes hot electrons to enter the floating gate electrode 4. That is, writing is possible. These hot electrons are accelerated by an electric field having a component perpendicular to the lateral electric field between the source and drain regions, and in order to efficiently inject them into the transmission gate electrode 4, such an injection method is used. C(Perpetvl
icularly Acceltyating Chtx
nnsl) It is called injection. 1. Semiconductor non-volatile memory using this injection method is called 'PAC'.
M OS (Perpendicularly Acc
elerating Channel 1njecti
Metal Dxtal○xide 5tnnico
ndvctor).

To read the memory of PACMO8, floating gate electrode 4
This phenomenon occurs because the channel conductance between the source and drain regions changes depending on the amount of charge in the region.

In the case of the conventional PACMO 9 as shown in FIG. 1, a highly concentrated P-type impurity region 8 is formed to make the surface potential difference in the electron acceleration region steep in the acceleration direction. Since this P-type impurity region 8Vi is formed from the region where the first and second channel regions intersect to a part of the first channel region M, the resistance of the @l channel L1 increases, which occurs during drilling. The surface potential difference becomes small. Therefore, writing efficiency was not significantly improved.

The present invention has been made to overcome the conventional drawbacks, and provides a nonvolatile semiconductor memory with high write efficiency and suitable for high integration.

The present invention will be explained briefly using FIGS. 2 and 8. Figure 2 shows
It is a cross section M of the semiconductor nonvolatile memory of the present invention. A 19-type source region I2 and a drain region 13 are formed on the surface of a P-type semiconductor substrate 11, and a selection gate electrode 15. A floating gate electrode 14 is formed, and a control gate electrode I9 is further formed on the floating gate electrode 14 through an insulating film hole. Control gate electrode 19
is the most strongly coupled with the floating gate electrode 14,
The potential of the floating gate electrode 14 is controlled. In addition, as shown in FIG. It is formed only on the surface of the semiconductor substrate between the floating gate electrode 14 and the floating gate electrode 14 . That is, a high concentration P-type region is formed only in the vicinity of the injected charge acceleration region.

In the non-volatile semiconductor memory of the present invention as shown in FIG. A charge acceleration region is formed very steeply. Since the channel resistance under the selection gate electrode and the floating gate electrode 13 is extremely small, no drain voltage is effectively applied to the injected charge acceleration region.

Therefore, a programmable nonvolatile semiconductor memory with low voltage and low current consumption can be realized.

Highly doped P-type region in FIG. 2; 38 is the selection gate electrode]5
and floating gate) are formed in a self-aligned manner with respect to the pole 14.

Further, the selection gate insulating film I5 and the floating gate electrode 14 were formed in the same process. At the poles, their distance Fi
It is 0.5 μm or less.

High concentration P type region of the nonvolatile semiconductor memory of the present invention as shown in FIG. A single pole floating gate electrode can be formed by the steps shown in FIGS. 3(a) to 3(g). Gate I on the P type substrate 21! ! 2i* film n, and a polycrystalline silicon film which will serve as a select gate electrode and a floating gate [pole] are further formed. An insulating film is formed on the polycrystalline silicon, and a resist 25 is applied thereon. When etching the absolute tJ film according to pattern 7 of resist δ, it is shown in Fig. 3 (6
)become that way. Next, when an aluminum silicon film 26 is formed on the wafer, a cross-sectional view as shown in the third section 1(c) is obtained. The knee 24 is side-etched during etching, so it looks like No. 8F (c). Next, when the resist 5 is removed, it becomes as shown in FIG. When the polycrystalline silicon group 23 is etched, it becomes as shown in FIG. 8(g). That is, it corresponds to the side etching 1' of the edge formed in the step of FIG. 3(b). Therefore, the width of the polycrystalline silicon shank is several 100 mm.
Can be processed within 0 angstroms. Finally, as shown in FIG. 3(A), if ions are implanted through the polycrystalline silicon H23, a highly doped P-type head region is formed in a self-aligned manner with respect to the polycrystalline silicon that becomes the selection gate electrode and the floating gate electrode. 27
can be formed.

As explained above, according to the nonvolatile semiconductor memory of the present invention, by forming a P-type head region to make the injection charge acceleration region steep only in the injection charge acceleration region, programming can be performed with low voltage and low current. Therefore, a highly integrated nonvolatile semiconductor memory can be realized.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional PA (MO8 type semiconductor non-insertion memory), and Figure 2 is a cross-sectional view of a PACM of the present invention.
FIG. 2 is a cross-sectional view of an O8 type semiconductor nonvolatile memory. Figure 3 (
α) to (A) are cross-sectional views showing the manufacturing process of the semiconductor nonvolatile memory of the present invention in Section 2. 1, 11, 21...P-type substrate 2.12--φ--Source region 3.13-Fist...Drain region 4.14...Floating gate 'ifi pole 5.15--
Medium... selection gate? ij @L9.19... Control gate electrode device Upper applicant: Seiko Electronic Industries Co., Ltd. Agent Patent attorney: Mogami Fig. 1

Claims (1)

[Claims] Source/drain regions of a second conductivity type different from the first conductivity type provided at intervals on a surface portion of a semiconductor substrate of a first conductivity type; and a gate insulating film on a surface portion of the semiconductor substrate between the source/drain regions. A semiconductor non-volatile device is formed of a selection gate provided via a floating gate electrode and a floating gate electrode, and a charge acceleration region is formed near a surface portion of the semiconductor substrate between the selection gate electrode and the floating gate electrode. 1. A semiconductor nonvolatile memory characterized in that a second conductivity type impurity region gold film trench is formed on a surface portion of the semiconductor substrate between the selection gate electrode and the floating gate electrode.