JPS6024660A - Input/output interrupting processing system of multiprocessor system - Google Patents

Abstract

PURPOSE:To reduce the number of connecting lines for connecting a controller and a processor, by providing a PSWC register for holding a copy of a program status word of each processor, in the controller. CONSTITUTION:An interrupting destination determining logical circuit 71 inputs the contents of PSWC registers 72-75, and an interrupting destination processor is determined from these contents. When an interrupting destination is determined, the circuit 71 outputs an interrupting destination processor number through an interrupting destination processor informing line 6, by which a designated processor executes an interrupting processing. Rewriting of the PWSC registers 72-75 is executed as mentioned below, when a program status word PSW which each processor 1-4 has been changed. That is to say, it is executed by inputting the contents of PSW registers 11-14 of each processor 1-4 to the inside of a controller 7 through a system data bus 5, and transferring it to the PSWC registers 72-75. In this way, the number of connecting lines between the controller 7 and the processors 1-4 can be reduced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention determines a processor to perform interrupt processing from among a plurality of processors in which an interrupt occurs, and interrupts a specific processor. The present invention relates to an input/output Wll-inclusive processing method for a multiprocessor system that performs processing (1').

[Technical background of the invention]

In a multiprocessor/system consisting of a plurality of processors, the processors that perform interrupt processing on a case-by-case basis from the channel; conventionally, the following methods have been used to intermix the processors: was there. The tenth method is to have one specific predetermined processor perform all interrupt processing. In the 20th method, interrupt requests from channels are handled by all professionals,
7 Lee is 11i gill i'L1 The processor that receives the data first performs M-inclusive processing. , the third method is
When a processor makes an I/O request to a channel,
The channel records the processor that made the human output request, and the interrupt request is made to this processor.
This processor performs interrupt processing.

However, each of the above methods has the following drawbacks. In method 1 and 2, if the processor corresponding to interrupt processing goes down, the system goes down. Furthermore, if the processor in charge of interrupt processing is unable to accept interrupts, the interrupt processing will be delayed. Furthermore, the interrupt processing ability of the processor in charge of interrupt processing can easily become a performance bottleneck.

In the second method, the procedure for accepting an interrupt is complicated and time-consuming. Furthermore, the processor that accepts the interrupt request is not always the most suitable processor for processing the interrupt in the system.

In the third method, if the processor that should accept interrupts is in a state where it cannot accept interrupts, interrupt processing will be delayed. Additionally, countermeasures are required in case the processor that issued the input/output request goes down before accepting the interrupt.

In order to overcome these drawbacks of each method, the following four-part method has been proposed. Figure 1 shows an example of a multiprocessor system applying method 4.
It is the cause. The four Norocessors 1 to 4 are connected to the system bus 5.
/lc is connected. Each processor 1 to 4 has a psw
(Program status word) PSW registers 11 to 14 are provided. Also, processor 1~
4 is i! IIJ interrupt destination processor notification to notify the interrupt destination processor number l1lli! 6 is connected.

The system controller 7 has an interrupt destination determination logic circuit 71.
This interrupt destination determination logic circuit 71 includes registers 11 to 14 in processors 1 to 4 to P8 to
The contents of the PSW of each processor are input by tracing the dedicated lines 101 to 104 through which the contents of the V are transferred. Also, the system controller 7's filling destination determination logic circuit 71
A Vj inclusion request signal is input from channel 8 by cutting signal 19.

Next, the operation of the above-mentioned known example will be explained. In this known example, the system controller 7 that handles the multiprocessor system determines the destination of 61, τi+ii logic rpa1!
i71, and when an interrupt request is received from channel 8, the interrupt destination determining logic circuit 71 determines the interrupt destination processor.

As a material for determining the interrupt destination, each processor 1 to 4
p s 'w (register 11
- 14 contents)) to the interrupt decision logic circuit 71.
, and uses this as information for determining the interrupt destination. The contents of the PSW of each processor 1 to 4 received by the interrupt destination determination logic circuit 71 of the system controller 7 include the interrupt level, the strawberry prohibition/permission bit, the bit indicating whether or not each processor is in a standby state, etc. It consists of a pit. When the interrupt destination processor is determined based on these materials, the system controller outputs the interrupt destination processor static code to the 91 interrupt destination processor notification line 6, which causes the specified processor to perform interrupt processing. .

According to this method, the drawbacks of the above-mentioned methods 1 to 3 are almost solved. In other words, even if one of the processors goes down,
Add V3jj to other processors, r! 1! If you do this, you will get it, so the system will not go down.

Since the destination of the interrupt is determined according to the state of each processor, the processor that handles the interrupt becomes the processor that is most suitable (or close to Q) for handling the interrupt in the system. The procedure for accepting an interrupt is simple and does not require much time. If any of the processors ~qij
Even if an interrupt cannot be accepted, other processors will accept the interrupt, so interrupt processing will not be delayed.

[Background Art] However, in the method of Part 4, the contents of the PSW of each processor 1 to 4 are stored in the system controller 7.
For blue, flj1101 to 104 for delivery to λ
The disadvantage is that it has to be downloaded. This dedicated line 1
For example, if the number of bits to be transferred to the system controller 7 of each of the processors 1 to 4 is 4 bits, the actual ta of 01 to 104 is 4 bits x 4 units - 16 bits.1. 'j: This is because it cannot be seen. Furthermore, if the system f 4'f is successful, the number of dedicated lines will increase further, resulting in increased costs, increased work and man-hours, and reduced reliability. It has the disadvantage of inviting people.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above drawbacks, an object of the present invention is to provide a human output interrupt processing method in a multiprocessor system that reduces the number of connections f"1 connecting a system controller having an interrupt destination determination logic circuit and a processor. be.

[Summary of the invention]

In the present invention, an interrupt processing decision logic circuit is provided in the system controller that manages α number of processors 'ff: When an interrupt request is received from a channel, this d+; J interrupt processing decision logic circuit determines the state of each processor. The contents of the program status word (i' 8 W ) shown are taken in, and the status of each processor is determined by J, , ;t:
In a multiprocessor system in which the most common interrupt processing processor is determined, the system controller includes a copy of the 171 report that is necessary for specifying the recipient of the PSW; 14.”, beat P
An SWC register is provided, and the interrupt processing decision logic circuit determines which processor is to perform the interrupt processing J1 by the contents of this pswc register. JJ: Transfer the rewrite data in warehouse A to the P and SWC registers in the system controller through the system data bus, and change the entire contents of this register: By adopting the j'7 configuration, the above It achieves all objectives.

[Embodiments of the invention]

The following is a detailed example of the input/output interrupt processing method in the multiprocessor system of the present invention.
S is given the same reference numeral and will be explained with reference to FIG. ni7.

4'r 21A Input/output 211-inclusive processing method in the multiprocessor system of the book B'ft: J-use 1
This is an example of a multiprocessor system.

Algebraic processors 1 to 4 connect to system bus 5
has been done. Each processor 1 to 4 has PSWk?
PAW registers 11 to 14 are provided.

Further, the temporary processor number is input to each of the processors 1 to 4 through the interrupt destination processor notification gland 6. System controller 7 has channel 8
An interrupt destination determining logic circuit 71 is provided which determines which processor among processors 1 to 4 is to be caused to not process the interrupt when an interrupt request is received from the processor. The system controller 1 also has a PS which is a copy of the information necessary for determining the interrupt destination among the contents of the PAWs of the processors 1 to 4.
PSWC registers 72 to 75 are provided to hold wcl, and the contents of these registers 72 to 75 are stored in the signal line 100.
2 to 1005 are all input to the interrupt destination determination logic circuit 71. Furthermore, old data is input to these registers 72 to 75 from the system bus 5.

71 interrupt destination decision logic circuits 6 interrupt destination processor notification lines
Outputs the processor number determined to be the interrupt destination. Channel 8 is the interrupt destination determination logic circuit 72 of the system controller 7.
An interrupt request signal is output through the entire signal line 9.

Next, the operation of this embodiment will be explained. When an interrupt request is output from channel 8 to system controller 7,
The interrupt destination determination logic circuit 71 has pswc registers 72 to 7.
5 and determines the interrupt destination processor from these contents. Note that the contents held in registers 72 to 75 are PSWC, which is a copy of information necessary for determining the interrupt destination among processors 1 to 40 PSW, and this PSW-C is a prohibition/permission pit for each interrupt level. , a bit indicating whether each processor is in standby state p7hc, etc., and consists of several bits of information. When the interrupt destination determination logic circuit 71 determines the interrupt destination, it outputs the entire interrupt destination processor number through the interrupt destination processor notification thread 6, so that the designated processor processes the interrupt.

4p of pswc registers 72 to 75 > When there is a pswK history held by each processor 1 to 4, the contents of PSW registers 11 to 14 of each processor 1 to 4 are transferred to the system data bus 5ka and sent to the system controller. This is done by capturing the data into PSWc registers 2-5.

According to this embodiment, a copy of the PSW of each processor 1 to 4 is stored in the system controller 7.
Setting registers 72 to 75 ~1. ';・Input destination determination meter,
The buried circuit 71 is connected to these P S W C registers 72 to 75.
Determine the interrupt destination processor by referring to 8 k of the above, and
Since the replacement of the PSWC registers 72 to 75 when changing the PSVV of each processor 1 to 4 is performed via the system data bus 5, the contents of the PSW that connects the system controller 7 and each processor 1 to 4 are allocated. It is possible to completely eliminate the dedicated line that cannot be passed to the destination decision logic circuit 71.
The number of connection lines between the system controller 1 and the processor can be reduced. Moreover, this has the advantage of an input/output interrupt processing method that has a system controller with an interrupt destination determination logic circuit, that is, even if one of the processors goes down, the system does not go down immediately, and interrupt processing is always performed. The optimal (nearly optimal) processor can be determined, the interrupt acceptance procedure can be performed fffj simply and in a short time, and the interrupt processing is not delayed. Therefore, it is possible to reduce the number of drawing steps and costs when assembling a multiprocessor system, and to improve the reliability of the system.

〔Effect of the invention〕

Input/output i! in the stem i', 1 depending on the I-inclusive processing method
ttd", P to keep a copy of each processor's PSW warm
The SWC register is provided in the system controller, and the PS
When W is changed, the interrupt data (IJ) is transferred to the P S WC register through the entire system bus, and the interrupt destination determination logic circuit in the system controller determines the interrupt destination by referring to the contents of the PSWC register. By adopting this, there is an effect that the number of connection lines connecting the system controller having the interrupt destination determination logic circuit and the processor can be reduced.

[Brief explanation of drawings]

Figure 1 shows an example of a multiprocessor system that applies all conventional input/output interrupt processing methods.
．． 8'I↓2β' shows an example of the input/output interrupt processing method in the multiprocessor system of Kiensu. Processor 5...System bus communication system...System controller 8...Channel 11.12.13.14., PsW register 71...
Interrupt destination decision logic circuit 72.73.74.75...PS'WC register agent Patent attorney Hon 1) Takashi

Claims (1)

[Claims] An interrupt processing decision logic circuit is provided in a system controller that manages multiple processors, and when an interrupt request is received from a channel, the interrupt processing decision logic circuit determines the contents of the program status word (PSW) that indicates the status of each processor. In a multiprocessor system in which the optimum interrupt processing processor is determined by taking into account all the processors and then considering the state of each processor, the PS
P8 is a copy of the information necessary for determining the interruption among the contents of W.
A register is provided to store the WC, and the interrupt decision logic circuit refers to the contents of this register to determine which processor is to handle the interrupt, and also to change the PSW when the PSW of each processor is changed. An input/output buffer in a multiprocessor system whose function is to transfer data to the previous PSWC register through the system data bus;
J-inclusive processing method.