JPS60246196A - Convergence correcting device - Google Patents

Abstract

PURPOSE:To reduce the time required for correction and to attain an inexpensive device by including a convergence correction circuit of analog and digital systems, and storing both correction outputs, then outputting the result. CONSTITUTION:The analog system correcting circuit 31 is provided to the digital system convergence correcting device. In writing a correction data to a 1 field memory 6, a data selector 34 inhibits the output from a write data generating circuit 5 and supplies the output from an ADC33 to the memory 6. The data selector 35 acts similarly. Then the test pattern is displayed and coarse adjustment is executed by a correction circuit 31. The output of the correction circuit 31 is digitized by the ADC33, fed to a convergence coil 14 via the selector 35 and the DAC11 then the correction is attained. Further, the output of the ADC33 is written in the memory 6. Then the selector 34 feeds the output of the circuit 5 to the memory 6 and the selector 35 supplies the output of a vertical interpolation circuit 10 to the DAC11. Then the correction of the digital system is attained by increasing/decreasing the said data in the memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a convergence correction device for an image display device. The present invention relates to a convergence correction device using a convergence correction device.

Prior Art 1 As a convergence correction device for correcting the convergence of an image display device such as a color television set, a device applying digital technology is used. Conventional such devices include those that use only a digital method and those that use a combination of digital and analog methods.The device that uses only a digital method will be described first.

FIG. 1 is a block diagram schematically showing the configuration of a digital convergence correction device conventionally used in a color television receiver 1. As shown in FIG.

The device shown in Fig. 1 projects a test pattern as shown in Fig. 2 on the screen of a color television receiver, and calculates convergence correction amount data for each of the vertical and horizontal intersections that exist in this pattern. This is a device that reads a bond digitally written into one field memory, performs digital/analog conversion, and performs convergence correction.

In FIG. 1, a test pattern generation circuit 1 generates a test pattern signal, and projects a test pattern as shown in FIG. 2 on a screen 1i (not shown) of a color television receiver. Control panel 2 has cursor keys 28
and a data write key 2b, of which the cursor key 2a moves the cursor displayed superimposed on the test pattern on the screen horizontally/ ! ! It is used to move in the vertical direction (indicated by H and V in the figure). Further, the data write key 2b is used to increase or decrease the convergence correction amount indicated by a digital amount corresponding to the adjustment point in the test pattern. The cursor key 2a is connected to a write address generation circuit 3 composed of a reversible counter. The output of the write address generation circuit 3 is applied to the test pattern generation circuit 1 and one input terminal of the multiplexer 4. The data write key 2b is connected to a write data generation circuit 5 composed of a reversible counter, and the output of the write data generation circuit 5 is applied to a data input terminal of a one-field memory 6. The successive address generation circuit 7 is for generating an address for data written in the 1-field memory 6 when reading the data, and its output is given to the other input terminal of the multiplexer 4. ing. Further, the output t of this multiplexer 4 is given to a single field memory 6.

The read/llll input circuit 8 is a circuit that generates an 1lIII control signal when reading or writing, and its output is given to the ``I! input'' terminal of the 1 field memory 6. The data output of the memory 6 is branched into two and given to an input terminal of a 1-line memory 9 and one input terminal of a vertical interpolation circuit 10. This 1-line memory 9 stores data for one line. This vertical interpolation circuit 10 is for performing vertical interpolation between lines of convergence correction based on two inputs, and its output is a digital,
The signal is applied to an analog converter 11 and converted into an analog quantity. This analog output is smoothed by a low-pass filter 12, and this smoothed signal is amplified by an output amplifier 13 and then applied to a convergence coil 14 for color television reception.

Among the above configurations, the test pattern generation circuit 1, control panel 2, and write address generation circuit 3 are removed one by one, but the other components shown in FIG.
A total of 4M lines are provided corresponding to each of the convergence coils ``Green'', ``Blue Pa'', and ``Blue Lara'' (only one of them is shown in Figure 1). ).

R2O to data write key 211 of control panel 2
, B, and BL mean keys corresponding to each of these systems.

Next, the operation of the convergence correction g device shown in FIG. 1 will be explained. The operation of this device is roughly divided into an operation of writing convergence correction data into the 1-field memory 6, and an operation of reading data from the 1-field memory 6 to actually perform convergence correction.

In the write operation, first, the test pattern generating circuit 1 projects a grid-like image as shown in FIG. 2 on the screen of the color television receiver. Next, the user operates the cursor key 28 on the control panel 2 to move the cursor to an intersection in this grid-like image where word alignment is to be performed. The output of the write address generation circuit 3 changes depending on the output signal of the cursor key 28 at this time. In a write operation, the multiplexer 4 is set to give the output of the write address generation circuit 3 to the 1-field memory 6, and in the 1-field memory 6, this signal specifies the address corresponding to this intersection. Ru. Next, for example, when performing "red" convergence correction, the "R" key of the data write key 2b is operated. This causes the output of write data generation circuit 5 to change. At this time,
The 1-field memory 6 is also set to W-7 by the output of the read/write control circuit 8, and the output data from the write data generation circuit 5 is input to the 1-field memory specified by the cursor key 2a. 6 address. This operation is repeated for all intersections on the screen. By a similar method, ``green°'', ``blue pa,'' ``blue teral°'' can be obtained.
′ is also the I of all communication points! I! Then, the correction data for this adjustment point is stored in the corresponding addresses of the field memory 6 (17).

By the way, in the above-mentioned write operation, only the adjustment point (intersection) selected by the cursor key 28 is detected at the moment the data write key 2h is operated, and data is written into the 1-field memory 6. It is said to be a write mode like this. That is, when the receiver is scanning the screen, k is written only at the moment when the scanning line passes through the point on the screen selected by the cursor key 28 and the data import key 2b is being operated. The mode is set to include. 11! ! At the time of , the 1 field memory 6 is set to continuous output mode by the read 7/11 input control circuit 8, and the multiplexer 4 transfers the output of the continuous address generation circuit 7, that is, the elicitation address, to the 1 field memory 6.
It is designed to be given to

Next, the continuous output mode of the convergence correction data written in the 1-field memory 6 will be explained. In this continuation mode, the multiplexer 4 always supplies the continuation address, which is the output of the read address generation circuit 7, to the 1-field memory 6, and also the 1-field memory 6 is also used for read/write operations.
The write control circuit 8 sets the read mode. As a result, all of the data corresponding to each intersection on the screen stored in the 1-field memory 6 is stored in the field memory 6.
The data is read out according to the scanning speed. However, since the 1-field memory 6 stores only data on points corresponding to intersections on the screen, it is necessary to interpolate between each scanning line passing through vertically adjacent intersections. For example, between the first row L1 and the second row L2 of the horizontal line of the test pattern shown in FIG. ! In the case of direct interpolation, first, each data regarding the intersection existing above the 11th column L1 is read from the 1-field memory 6 and stored in the 1-line memory 9. Next, each data regarding the intersection existing above the second column L2 is read from the 1 field memory 6, and in parallel with this,
1 is read from the 1-line memory 9 and applied to the vertical interpolation circuit 10. Vertical interpolation @10 first calculates the difference between the data in the first column L1 and the second column L2, and then calculates the difference between the data in the first column L1 and the second column L2. Interpolation is performed by dividing by the number of scanning lines to find a minute change, and then adding this minute change to the data regarding the first column 11 one after another. In this way, the interpolated convergence correction data is converted into an analog quantity by the digital/analog converter 11, smoothed by the low-pass filter 12, and then amplified by the output amplifier 13 to be used in the receiver. It is applied to the convergence coil 14. This corrects convergence.

This read operation is ``Red Pa'', ``Edge''°16. Each of the blue □ and...blue lateral °° ↓ is done in detail.

However, with the device shown in Figure 1, when performing convergence correction using the pattern shown in Figure 2, for example, it is necessary to make adjustments at 9 x 7 locations (9 vertical locations and 7 horizontal locations), and in addition, the red , considering adjustment in a total of four directions: the radial direction of green and blue, and the lateral direction of blue, there are a total of 9X7X4-252 points II! This has the disadvantage that the FR interval required for adjustment is quite long.

Next, a convergence correction device that combines a digital method and an analog method will be described.

Such a device is disclosed in, for example, Japanese Patent Application Laid-Open No. 55-163985@
The outline of this item will be explained below.

Generally, a convergence correction waveform can be expressed by a polynomial of X and y, where the coordinates of an arbitrary point on the screen are expressed as <X, V>. In the shadow mask Brown constant of a delta-equipped electron gun, among the eight mounds of this polynomial, the component expressed as quadratic with respect to It has become.

A convergence correction device that combines a digital method and an analog method takes this fact into account, and performs convergence correction using the conventional analog method for the first and second orders of x and y, and We are trying to digitally correct these components and the portions of the primary and secondary components that could not be corrected by analog convergence correction. FIG. 3 shows a schematic block diagram of a device that realizes this principle.

The 3181st device is the special Pi1i11&55-1 mentioned above.
63985, a synchronizing signal 20 is input to a deflection circuit 21, and a deflection signal among the outputs of this deflection circuit 21 is given to a deflection yoke 27. Further, the synchronization signal generated by this deflection circuit 2'1 is given to an abrog convergence correction circuit 22 and a digital convergence correction circuit 23. Of these two convergence correction circuits 22 and 23, the digital convergence correction circuit 23 has almost the same configuration as the circuit shown in FIG. , the two convergence correction circuits 22, which are, for example, circuits formed by a combination of conventionally used passive elements.
The output of the digital convergence correction circuit 23 is applied to the convergence yoke 2G, and the other output of the digital convergence correction circuit 23 is applied to the dot generator 24. This dot generator generates a signal for displaying dots on the screen.

The video circuit 25 is supplied with either the video signal input 286 or the output of the dot generator 27, selected by a changeover switch 29).

Next, the operation of the apparatus shown in FIG. 3 will be explained. First, synchronization signal 2
A horizontal and vertical deflection N current synchronized with zero is generated by the deflection circuit 21 and sent to the deflection yoke 27. Further, the pulse voltage or sawtooth voltage t obtained by the deflection circuit 21 drives the analog convergence correction circuit 22 to perform convergence correction for the crosses that intersect vertically and horizontally on the screen. This performs coarse adjustment. On the other hand, a digital convergence correction circuit 23 is driven by horizontal and vertical pulses synchronized with the synchronization signal obtained from the deflection circuit 21.
Fine adjustments are mainly made to the convergence shift at screen W4) υ. When performing this adjustment, the output of the dot generator 24 is applied to the video circuit 28 to draw a dot pattern on the screen. The outputs of the two convergence correction circuits 22 and 23 are waveform-combined by the convergence yoke 26 to create a correction magnetic field.

In this type of method, correction is performed using the digital method after rough adjustment using the analog method, so the amount of correction using the digital method is a small amount compared to the overall amount of correction, and the number of bits for each adjustment point is reduced. , since the number of adjustment points itself is reduced, the adjustment time is shortened.

However, a convergence correction device using this method must always include an analog correction circuit in addition to a digital correction circuit, which increases the product price and is uneconomical. In addition, because analog circuits are constantly operating, there is a performance drawback in that the characteristics are easily affected by environmental conditions such as temperature, humidity, aging, and vibration.

[Summary of the Invention] This invention was made to eliminate the drawbacks of the conventional convergence correction device as described above. The main object of the present invention is to provide a convergence correction device that can reduce the increase in the 111i rating.

Another purpose of this invention is to achieve convergence in which characteristics are less likely to change depending on environmental conditions. f: To provide JIE g K.

To summarize the invention, there is provided a convergence correction device that includes an analog convergence correction circuit and a digital convergence correction circuit, and outputs the convergence correction outputs of both of them after recording them in a storage means. It has become.

EXAMPLES OF THE INVENTION] The details of the present invention will be clarified through a detailed explanation of the present invention.

FIG. 4 is a block diagram schematically showing the configuration of a convergence correction@key according to an embodiment of the present invention. this house,
A redundant explanation of parts having the same configuration as the apparatus shown in FIG. 1 will be omitted, and only parts unique to FIG. 4 will be explained.

The convergence correction device l shown in FIG. 4 includes an analog convergence correction circuit 31 in addition to the components of the digital convergence correction device shown in FIG.
1 inputs horizontal and vertical deflection pulses 32 and outputs an analog correction signal. This analog convergence correction circuit 31 has a conventionally used analog circuit configuration. This can be achieved, for example, by a combination of passive components.

The output of the analog convergence correction circuit 31 is sent to an analog/digital converter 3S and converted into a digital signal, and the output of this analog/digital converter 33 is sent to the first data selector 34 and the second data selector 34. Data selector 35
to one human power terminal of each. The output of the write data generation circuit 5 is given to the other input terminal of the first data selector 34, and the output of this first data selector 34 is given to the data input terminal of the 1-field memory 6. . In addition, the second data selector 3
The output of the vertical interpolation circuit 10 is applied to the other input terminal of the data selector 5, and the output of the second data selector 35 is applied to the input terminal of the digital/analog converter 11. In addition, an analog convergence correction circuit 31t
3 and analog/digital converter 32 for I! It is removable, and when writing data to 1 field memory 6 and making adjustments, k is mounted and! After completing the adjustment, that is, when reading data from the 1-field memory 6, it can be removed from the color television screen.

However, the analog convergence correction circuit 31
It is also possible to make only one part removable. The construction and connections of the other parts of the apparatus of FIG. 4, ie, the parts indicated by reference numbers 1 to 14, are the same as those of the apparatus of FIG. 1, except for the above-mentioned 8ct).

Next, the operation of @mushroom in FIG. 4 will be explained. Without further ado, let us explain the operation of writing data to the 1-field memory 6. At this time, an analog convergence correction circuit 31 and an analog/digital converter 33 are first mounted on the receiver, and horizontal and vertical deflection pulses 32,
Supplies lock signals, power, etc. as necessary. And the first
The data selector 34 is set to inhibit the output from the write data generation circuit 5 and provide the output from the analog/digital converter 33 to the 1-field memory 6.

Similarly, the second data selector 35 also operates in the vertical interpolation circuit 10.
The output from the analog/digital converter 33 is prohibited and the output from the analog/digital converter 33 is set to be provided to the digital/analog converter 111. Next, a grid-like test pattern as shown in Fig. 2 is projected on the screen of the receiver, and the variable inductance and variable resistance in the analog convergence correction circuit 31 are adjusted to adjust the red color on the screen. , perform rough adjustment so that the convergence correction for green and blue is approximately correct. At this time, the analog output of the analog convergence correction circuit 31 is transferred to the analog/digital converter 3.
3 into a digital quantity, and is applied to the digital/analog converter 11 through the second data selector 35.

This signal is converted back into an analog quantity by the digital/analog converter 11. After that, the low pass filter 12
The output signal is smoothed by the output amplifier 13, and then amplified by the output amplifying section 13 and provided to the convergence coil 14. After the convergence correction is generally correctly performed, by operating a memory switch (not shown), the output of the analog/digital converter 33 is transferred to the corresponding one field memory 6 via the first data selector 34. written to the address. The data written to the one twist memory 6 here is the convergence correction amount corresponding to the vertical and horizontal intersections of the test pattern shown in FIG. 2 during one field period. In this way, convergence correction using the analog method is completed.

Next, fine adjustment is performed using digital convergence correction data to compensate for the limits of adjustment accuracy in the analog method. In this operation, the first data selector 34 selects the output of the write data generation circuit 5 and supplies it to the 1-field memory 6, and the second data selector 35 selects the output of the vertical interpolation circuit 10. It is set so that it is selected and given to the digital/analog converter 11. When set up in this way, the signal flow in the device shown in FIG. 4 is similar to that in the device shown in FIG. 1, and its operation is almost the same as that described previously.
Duplicate explanations will be omitted. However, in the apparatus shown in FIG. 1, all convergence correction is performed by digitally writing data into one field memory 6, whereas in the apparatus shown in FIG. The analog correction data has already been written in the , and the digital correction can be adjusted by increasing or decreasing this written data, so the digital convergence correction data needs to be fine-tuned. It corresponds to

Next, in the read operation of data written in the 1-field memory 6, the first data selector 34 receives the output of the write data generation circuit 5, and the second data selector 35
selects the output of the vertical interpolation circuit 10, respectively, and in this way data reading and output are performed in the same manner as the device shown in FIG.

By doing this, when data is read from the one-field memory 6, the existence of the analog convergence correction circuit 31 becomes irrelevant to the operation. Therefore, the analog convergence correction circuit 31 and the analog/digital converter 33 are installed in the receiver only for writing adjustment, and can be removed during normal use. In this case, when the convergence deviates due to changes over time, it is possible to re-arm using a digital correction circuit installed in the receiver.

In the embodiment described above, the output of the analog convergence correction circuit 31 is converted into a digital quantity by the analog 7′ digital converter 33, and the output of the analog convergence correction circuit 31 is
1, the output of the analog convergence correction circuit 31 may be directly connected to the output side of the digital-to-analog converter 11 via an analog switch or the like.

Further, the present invention can be applied not only to the color television set 411 but also to general image display devices such as a projection type video projector using a plurality of projection type CRTs.

[Effects of the Invention] As described above, the present invention includes an analog convergence correction circuit and a digital convergence correction circuit, and outputs the convergence correction outputs of both of them after being stored in the storage means. Therefore, the i1 adjustment time can be shortened, and since the analog convergence correction circuit is not used except for adjustment, performance deterioration due to environmental characteristics is reduced. Furthermore, since the product C does not necessarily have to be equipped with an analog comparance circuit, these can be made removable, and in this case there is also the effect that the device can be made inexpensive.

[Brief explanation of the drawing]

FIG. 1 is a block diagram schematically showing the configuration of a conventional digital convergence correction device. FIG. 2 is an illustrative diagram showing a test pattern displayed on the screen of the receiver for adjusting the convergence correction. FIG. 3 is a block diagram schematically showing the configuration of a conventional convergence correction device that combines a digital system and an analog system. FIG. 4 is a block diagram schematically showing the configuration of a convergence correction device according to an embodiment of the present invention. In the figure, 1 is a test pattern generation circuit, 2 is a control panel, 3 is a write address generation circuit, 5 is a write data generation circuit, 6 is 1 field memory, 7 is a read address generation circuit, 9 is 1 line memory, 10 is a vertical interpolation circuit, 14 is a convergence coil, 31 is an analog convergence correction circuit, 32 is a horizontal and vertical deflection pulse, and 33 is an analog/digital converter. In the figures, the same reference numerals indicate the same or corresponding parts. Agent Masuo Oiwa Figure 2

Claims (6)

[Claims] (1) A convergence correction device for performing convergence correction of an image display device, which comprises analog correction data generation means for generating analog convergence correction data, and analog/digital conversion of the analog convergence correction data. , analog/digital conversion means for outputting first digital convergence correction data corresponding to the analog convergence correction data; digital correction data generation means for generating second digital convergence correction data; A convergence correction device comprising: storage means for storing digital first and second convergence correction data; and output means for reading and outputting the digital first and second convergence correction data from the storage means. (2) Among the analog correction data generation means and the analog 7/digital conversion means, at least the analog correction data generation means is removable from the w3 image II display device. The convergence correction device described in Section 1. (3) After the first digital convergence correction data is stored, the storage means stores the first digital convergence correction data in accordance with the value of the second digital convergence correction data. The convergence correction device according to claim 1 or 2, wherein the data is increased or decreased by one shift and stored, and the output means reads and outputs the increased or decreased data. (4) The convergence correction device according to any one of claims 1 to 3, wherein the storage means is a one-field memory that stores correction data for one field of the image display device. (5) The output means is also connected to the analog/digital conversion means; A convergence correction device according to any one of claims 1 to 4, comprising selective digital/analog conversion means for selectively converting correction data into an analog signal. (6) The output means is also connected to the analog correction data generation means, and the output means includes a digital/analog conversion means for converting the data read from the storage means into an analog signal, and a Any one of claims 1 to 4, comprising a selection means for selectively outputting the output of the conversion means and the analog convergence correction data that is the output of the analog correction data generation means. The convergence correction device described in .