JPS6024618B2 - Transmitting/receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmitting/receiving device that transmits and receives multiple signals in a time-division manner using two transmission lines.

Transmission lines for transmitting signals are provided between various detectors and meters inside an automobile.

Various signals are transmitted through this transmission line. conventionally,
One transmission line was associated with each signal. Therefore, as the number of signals increased, the number of transmission lines also increased. When the number of signals is small, no special problem occurs even if the number of transmission lines increases, but when the number of signals exceeds 1, the wiring system becomes complicated and the overall circuit configuration becomes It was complicated. In particular, recent automobiles are required not only to display vehicle distance and fuel, but also to display various displays such as battery status signals, brake status signals, and various lock displays. Meeting these demands naturally requires intensive and effective signal management. The present invention has been made based on the above viewpoints, and
The purpose is to reduce the number of transmission lines without corresponding signals.
An object of the present invention is to provide a transmitting/receiving device that can drive only a specific display means of a transmitter to display even if a large number of status signals are transmitted through two transmission lines.

In order to achieve the above object, the present invention includes a first transmission line;
The second transmission line and the first transmission line are provided with a clock signal that performs a line return with a constant period, a constant pulse width, and a constant level, and a reset signal that is generated when the clock signal reaches a predetermined number. Clock signal sending means that sends out signals in time series with different amplitude levels; Counts the clock signals sent from the first transmission line, and generates a count output when a predetermined count value is reached. The counter is provided with a counter that is reset when the override set signal is received, and the status signal to be sent out when the count output is generated is amplitude-modulated according to the content of the status signal and sent to the second transmission line. a counter that counts clock signals sent from the first transmission line, generates a count output when a predetermined count value is reached, and resets when the reset signal is received; At the same time, if a status signal is present on the second transmission line at the time when the count output is generated, the status signal is captured, and based on the amplitude level of this status signal, a plurality of signals determined in correspondence with the content of the status signal are acquired. The receiving means selects a specific display means from among the display means and drives the display of the selected display means.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the overall configuration of the present invention.

The transmission line 1 is exclusively loaded with a clock signal and a set signal as control signals whose amplitudes are modulated with each other. The transmission line 2 is dedicated to carrying the status signal to be transmitted in amplitude modulated form. The clock signal generator 3 is adapted to generate an output on the transmission line 1. From this generator 3,
A clock signal and a set signal whose amplitudes are modulated with respect to each other are generated in time series. The transmitters 4 and 5 receive the clock signal and set signal outputted from the clock signal generator 3 and transmitted through the transmission line 1, and send the status signal to the transmission line 2.
It is being sent to

This status signal is generated in conjunction with the operation of switches 8 and 9. Each switch 8, 9 has four contacts 1, 2, 3 respectively.
, 4. By switching and selecting these four contacts with the movable contact, the contact outputs a binary output of "1",... For example, in the case of determining whether an abnormality in a specific state of a car is normal, it indicates a binary state of abnormality or normality, and turning on and off a contact directly indicates that state. However, when detecting a specific state quantity, it cannot directly correspond to the contact point.In such a case, the state quantity is appropriately sampled and converted to a digital base.This digital quantity Each bit indicates a binary state of ``1'' or ``0'', and can correspond to one contact point.In the sense described above, it can correspond to the state quantity of each switch. Furthermore, both transmitters 4 and 5 have counters.

This counter has the capacity to count the number of clock signals that exist between the reset signal and the set signal sent via the transmission line 1, for example, if there are N clocks, N
It is a forward counter. This counter outputs a count when a specific count n (n≦N) is reached. When this count output occurs, if any of the four contacts 1, 2, 3, and 4 is on, its on state is captured.
Furthermore, the status signals inputted from the four contacts are amplitude-modulated according to each contact number. This amplitude-modulated state signal is output to the transmission line 2 in synchronization with the count output. Note that the counter is reset each time a reset signal sent from the transmission line 1 arrives. Receivers 6 and 7 receive a control signal consisting of a clock signal and an IJ set signal sent from transmission line 1, and a control signal sent from transmission line 2 from transmitter 4 or 5.
It takes in the status signal sent via the.

Both receivers 6 and 7 have counters. This counter is an N-ary counter. Furthermore, the counter counts the clock signals sent out, and by the reset signal,
Reset. The counter has a predetermined count value m (m≦N)
When the count is reached, the count output is output. If m=n, it is the same as the count value that generates the count output of the transmitter. Then, the state signal corresponding to the contact sent from the transmission line 2 when the count output is generated is taken in, and the corresponding lamp 10,
11, 12, 13, 14, 15, 16, and 17 are lit. Each receiver 6, 7 has four lamps 10, 11, 12.
, 13 and 14, 15, 16, and 17. These four lamps correspond to the four contacts of the transmitter, respectively. That is, as mentioned above, the transmitter output of each of the four contacts is amplitude modulated. Therefore,
When the state signal that has undergone amplitude modulation is output by the counter,
The data are sorted and captured based on the timing of the count output. This sorted and captured status signal can be displayed on the corresponding lamp. Note that the lamp does not necessarily mean an actual lamp, and may be, for example, a liquid crystal display element. In short, its true purpose is to somehow detect and display the received status signal. Although the number of lamps is set in correspondence with the four contacts, a numerical correspondence is not necessarily required.

Also, although both the transmitter and the receiver have one count output, multiple count values such as a first count value, a second count value, and a third count value are determined, and each count value is It is also possible to output a counting output when the As will be specifically described below, some of the counters below have a decoder function, but they will be referred to as counters without any particular distinction.

FIG. 2 is a diagram showing a specific embodiment of the present invention.

The clock signal generator 30 is a clock signal oscillator 300.
, counter 301, inverter 3 town 2, nand gate 3
03, low resistors 304, 305, 308, 309, and transistors 306, 307.

The transmitter 40 includes a counter 400, a comparator 401,
402, low resistance 403, 404, 405, 406, 407
,412,413,414,418,419,420,
NAND gate 409, 410, 411, switch 408
, transistors 415, 416, and 417.

This transmitter is defined as including a switch. The receiver 50 includes a counter 500 and comparators 501 and 5.
02,508,509,510, low resistance 503,504,
505, 506. 507, 511, 512, 513, 5
14,515,516,517,518,519,52
0,521,522,523, diode 525, NOR gate 526, delay type flip-flop 527, 528
, 529, 530, driver (amplifier) 531, 53
2,533,534, lamp 535,536,537,
It consists of 538 pieces.

This receiver is defined as including a lamp. First,
The operation of the clock signal generator 30 will now be explained.

FIG. 3 shows the respective waveforms of the clock signal generator 30 and transmitter 40. Clock signal generator 30 using FIG.
Let's explain how it works. The clock signal oscillator 300 has a constant period during a constant pulse. A basic clock signal 300a of a constant level is generated. This signal 300a is transmitted to the counter 30
1, serves as an input to the inverter 302 and NAND gate 303. The counter 301 receives an input basic clock signal 30.
It counts 0a and has a self-resetting function when it reaches N. This is a so-called N-ary counter. This counter 3
01 is a carry-out signal 301a every time N number is reached.
occurs. FIG. 3 shows the case where N=4. NAND gate 303 receives signals 301a and 300a as input, and generates signal 303a. This signal 3
03a becomes "0" only when synchronized with the basic clock signal when the reset signal is generated, and becomes "1^" on other time axes. On the other hand, the signal 300a is inverted by the inverter 302 and becomes the signal 302a.Transistor 306
, 307 are both conductive when the input becomes "or", and become "1"
When this happens, it becomes non-conducting. Transistors 306, 30
When both transistors 306 and 7 are non-conductive, the output 30a becomes 0 level, and when only the transistor 306 is conductive, the output 30a becomes 0 level.
generates a voltage approximately equal to the power supply voltage V. When only the transistor 307 is conductive, the power supply voltage is set to a low resistor 308,3.
A voltage obtained by dividing the voltage at 09 is generated. When both transistors 306 and 307 are conductive, the power supply voltage is approximately V.
generates a voltage equal to In the signal 30a of FIG.
The pulse P, has a voltage level corresponding to V, and the pulse P
2 has a voltage level divided by low resistors 308 and 309,
The pulse P3 has a voltage of 0 level. This signal 3
0a is a form in which the reset signal and the clock signal are amplitude-modulated. Next, the operation of the transmitter 40 will be explained according to FIG.

A transmission output 30a output from the clock signal generator 30 is routed on the transmission line 1 dedicated to the clock signal. A transmission output 30a is input to the transmitter 40 via this transmission line 1. Comparator 401 extracts only the clock signal from the zero transmission output, and comparator 402 extracts only the reset signal from the transmission output. Therefore, each comparator 401, 402 has a low resistance 403, 40.
4,405, a voltage obtained by dividing the power supply voltage V is applied to the negative terminal. The output 4012 of the comparator 401 is input to the count terminal C of the counter 400, and the output 402a of the comparator 402 is input to the reset terminal R of the counter. The counter 400 is an N-ary counter like the counter 301. Therefore, when N clock signals 401a are counted, the next set signal 401a is counted.
It will be reset by 2a. This counter 4
00 is the count output 400a when the predetermined count value n is reached.
occurs. In FIG. 3, n=2 is set. however,
The counter 400 continues counting until it reaches the count value N even after issuing a count output. The switch 408 has four contacts, contact 1, contact 2, contact 3, and contact 4.

The movable contact acts as if it were attached to one of the four support points.
Contact 4 is completely floating. Contacts 1, 2,
3 serves as an input to NAND gates 409, 410, and 411. Furthermore, the count output 400a of the counter 400 is commonly input to the NAND gate. These NAND gates produce a 0'' output when both inputs are both 1''. When this uo'' output occurs, the transistor that receives the uo'' output at its base becomes conductive. 4
Since only one contact is selected among the contacts, only one of the corresponding transistors 415, 416, and 417 is always suitable.

When contact 1 is selected and transistor 415 is conductive,
The transmitter output 40a is approximately at the power supply voltage. When contact 2 is selected and transistor 416 is conductive, transmitter output 40
a is the voltage V obtained by dividing the power supply voltage V by the resistors 418 and 420. When contact 3 is selected and transistor 417 is made conductive, transmitter output 40a becomes voltage y2 obtained by dividing power supply voltage V by resistors 419 and 420. When contact 4 is selected, none of the transistors conducts, and therefore transmission output 40a becomes 0 level. The resistance value of the resistor 418 is set to a value of 4.compared to that of the resistor 419. Therefore, V,>V2. The relationship between each contact and the transmission output 40a is shown in FIG. 3 as a transmission output. According to this transmitter 40, by selecting a contact point, a transmission output 40a whose voltage level is determined according to the contact number can be obtained. In the figure, the case where contact point 2 is selected and the transmission output 40a at that time are shown by solid lines. This transmission output 40a is sent to the data transmission line 2. Next, the specific operation of the receiver 50 will be explained in the third section.
Let's explain based on the diagram.

First, the clock signal generator 30 sent out from the transmission line 1
The output 30a is input to each comparator 501, 502. Comparator 501 selects only the clock signal among the signals 30a, and comparator 502 selects only the reset signal among the signals 30a. For this selection, resistors 505, 506, and 507 are set to predetermined values. The output of the comparator 501 is a signal 601a, and the output of the comparator 502 is a signal 502a. signal 5
01a is the counter input of the counter 500, signal 502a
becomes the reset input for the counter 500. counter 50
0 is an N-ary counter like the previous counter, and when the clock signal reaches a predetermined count value m, the count output is 500.
Let a be the output, now m! If n, the counter 400
The counter 500 will generate count outputs at the same timing. However, the output 30a is input in a negative manner to comparators 401 and 402 which are input to the counter 400, and the output 30a is input to comparator 5 which is input to the counter 500.
01,502, the output 30a is input to the positive terminal. As a result, even though the timing is the same, there is a phase delay of one clock signal. Thus, a counting output 500a as shown in FIG. 3 is generated. On the other hand, transmitter 4
The transmission output 40a sent from the transmission line 2 from the resistor 5
Comparators 508, 5 through 11, 512, 513
Input to the positive terminal of 09,510.

Comparator 508 selects the transmission output V when contact 1 is selected. The comparator 509 selects the transmission output V when contact 2 is selected. Comparator 510 selects transmission output 2 when contact 3 is selected. Resistance 514, 516, 520, 5
23 has the role of providing a divided voltage for the above selection. Furthermore, in order for the output of the diode 524 and the comparator 508 to become 1'', the output of the comparator 509 must be 1''.
The diode 525 is used to set the output of the comparator 510 to be 0'' when the output of the comparator 509 is 1''. This diode 5
24,525 is provided because the comparator 509 is V
and V, and the comparator 510 can select between V and V,
This is because it is possible to select between V2 and V2. The output of each comparator 508, 509, 510 is a delayed flip type
This becomes the D terminal input of flops 527, 528, and 529.
Additionally, all outputs are inputs to NOR gate 526. The output of this NOR gate 526 is a delay type flip
This becomes the D terminal input of the flop 530. This flip-flop 630 corresponds to contact 4. The clock input terminal CL of each flip-flop 527, 528, 529, 530 receives the counting output 500 of the counter 500 mentioned above.
a is inputting.

As a result, for example, when contact 2 is selected, the output 509a of the comparator 509 is generated at the timing shown in FIG. 3 and is input to the D terminal of the flip-flop 528. Then, it is taken in by the count output of the counter 500 and displayed on the lamp 536 through the driver 532. The same display can be performed when selecting other contacts. According to the above embodiment, by providing one transmitter with a changeover switch having multiple contacts and providing one receiver with multiple display functions, it is possible to transmit and receive multiple signals in a time-sharing manner. Ta.

FIG. 4 shows another embodiment of the transmitter 40. Four switches 430, 431, 432, and 433 are provided.

Each switch corresponds to four different counting outputs 400b, 400c, 400d, 400e of counter 400. The counting output 400b is output from contacts 1 and 2 of the switch 430.
, 3 along with the outputs of NAND gates 440, 441, 442
This is the input. Count output 400c is switch 43
NAND gate 443 along with the outputs of contacts 1, 2, and 3 of
444,445 are input. Counting output 400d
are the outputs of the contacts 1, 2, and 3 of the switch 432 as well as the inputs of the nasodic gates 446, 447, and 448. The counting output 400e is input to NAND gates 449, 450, and 451 together with the outputs of contacts 1, 2, and 3 of the switch 433. Nand Gate 440, 443, 446, 4
The output of transistor 49 is applied to the base of transistor 415 via resistors 452, 453, 454, and 455. The outputs of NAND gates 441, 444, 447, and 450 are input to the base of transistor 416 via resistors 456, 457, 458, and 459. Nand Gate 442,
The outputs of 445, 448, 451 are resistors 460, 461,
It is input to the base of the transistor 417 via 462 and 463. Thus, when only the transistor 415 is conductive, the transmission output 40a becomes the power supply voltage V. The conditions at this time are when contact 1 of each switch is selected and there is a corresponding count output. When only the transistor 416 is conductive, the divided voltage V, determined by the voltage dividing point between the resistors 418 and 420, becomes the transmission output 40a. The condition at this time is that contact point 2 of each switch is selected and there is a corresponding count output. When only the transistor 417 is conductive, the voltage V2 at the voltage dividing point determined by the resistors 419 and 420 becomes the transmission output 40a. Each condition at this time is when the contact 3 of each switch is selected and there is a corresponding count output. In this way, multiple outputs can be transmitted in a time-division manner using multiple switches. Although an example of four switches is shown, the number of switches is arbitrary. Next, another embodiment of the receiver is shown in FIG. The counter 500 has four counting outputs 500b, 500c, 50
It has 0d, 500e. Furthermore, each count output is outputted by delay type flip-flops 540, 541, 542, 543, 544, 545, 5 corresponding to the four contacts 1, 2, 3, 4.
46,547:548,549,550,551;55
The output of the comparator 508 is input to the clock terminal CL of the flip-flops 540, 544, 548, and 552. The output of comparator 509 is the flip-flop 5
It is input to the ○ terminals of 41, 545, 549, and 553. The output of comparator 510 is output from flip-flop 54.
It is input to the ○ terminals of 2,546,550,554.
Furthermore, the outputs of the comparators 508, 509, and 510 become inputs to a NOR gate 593, and the outputs of this gate are input to the D terminals of flip-flops 543, 547, 551, and 555. The Q outputs of all IJ flops are drivers 560, 561, 562, etc.
·, 587 through lamps 564, 565, 566, ·
...592 is lit. With this configuration, the receiver 50 corresponds to the transmitter 40 shown in FIG. 4. In this embodiment, an example corresponding to four switches is shown, but the number is not necessarily limited to four.
Note that although the above example deals with automobiles, signal transmission in other industrial fields is also possible.

As explained above, according to the present invention, by transmitting a large number of status signals to two transmission lines in a time-sharing manner without making the number of transmission lines correspond to the signals, An excellent effect can be obtained in that only a specific display means among the plurality of display means can be driven for display, contributing to the simplification of the transmission system.

[Brief explanation of drawings]

Fig. 1 is an embodiment of the overall configuration of the present invention, Fig. 2 is a specific embodiment of the invention, Fig. 3 is a waveform diagram of each part, Figs.
The figure shows another embodiment. 1, 2...Transmission line, 3,30...Clock signal generator, 4,5,40...Transmitter, 6
,7,50...Receiver. Fig. 1 Fig. 3 Fig. N Ship drawing Dimensional figure Yamaja

Claims (1)

[Claims] 1 A first transmission line, a second transmission line, and a clock signal that repeats a certain period, a certain pulse width, and a certain level on the first transmission line, and every time the clock signal selects a predetermined number of times. clock signal transmitting means for transmitting reset signals generated at different amplitude levels in time series; counting the clock signals transmitted from the first transmission line to a predetermined count value; The counter is provided with a counter that generates a count output when the count output is reached and reset when the reset signal arrives, and modulates the amplitude of the status signal to be sent out when the count output occurs according to the content of the status signal. a transmission means for transmitting to the transmission line;
Counts the clock signals sent from the transmission line, generates a count output when a predetermined count value is reached, and is equipped with a counter that resets when the above reset signal is received, and generates the count output. At the point when the second
If a status signal is present on the transmission line, the status signal is captured, and depending on the amplitude level of the status signal, a specific display unit is selected from among a plurality of display units determined in correspondence with the content of the status signal, A transmitting/receiving device comprising: receiving means for driving a selected display means.