JPS60245305A - Transversal filter - Google Patents

Abstract

PURPOSE:To decrease the number of weighting circuits by connecting in common a delaying circuit corresponding to a tap whose weight coefficient is equal, to the weight circuit. CONSTITUTION:An impulse response of a transversal filter of this device is a symmetrical waveform centering around a peak point as shown in the figure. Accordingly, when a delaying circuit being in a symmetrical relation is connected to a common weighting circuit, the number of weighting circuits can be reduced to half. Delaying circuits 3-1, 3-c are connected to a weighting circuit 2-1, delaying circuits 3-2, 3-B are connected to a weighting circuit 2-2, and subsequently, each corresponding circuit is connected. In this way, the number of weighting circuits is reduced to half, and the conversion to an integrated circuit is executed more easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a transversal filter in which a delay circuit is constructed of switched capacitors.

Prior Art and Problems Figure 2 is a block diagram of a transversal filter, where 1 is an input terminal, 2-1 to 2-n are weighting circuits, and 3 is a block diagram of a transversal filter.
-1 to 3-n are delay circuits, 4 is an addition circuit, and 5 is an output terminal. The input signal applied to input terminal 1 is V =
For n% weighting, the weighting coefficients of circuits 2-1 to 2-n are hh
(k=1.2.3...n), delay circuits 3-1 to 3-n
Letting the delay time d5 and the sampling period be T, the delay time d of the delay circuits 3-1 to 3-n is selected so that j,=-T. Also, weighting is done by circuits 2-1 to 2-n.
The output signals are ■, , ・h, and the delay circuit 3-1
The output signals of ~3-n are as follows: ■1. ．．・h ・z−K becomes.

Since the adder circuit 4 adds the output signals of the respective delay circuits 3-1 to 3-n, the output signal V out is outputted to the output terminal 5.

FIG. 3 is an explanatory diagram of the weighting coefficients of the 12-tap transversal filter, and the weighting coefficients hk (h+ -hq, hA to hc) corresponding to the impulse response are set. The frequency characteristics of such a 12-tap transversal filter are shown in FIG. 4, where the horizontal axis represents frequency and the vertical axis represents loss (dB).

FIG. 5 shows the circuit configuration of the main part of the transversal filter using the Swisso-Cacacitor type delay circuit proposed earlier. 9. 2-A to 2-C are connected, and each weighting circuit 2-1 to 2-9.2-A to 2-C is connected to a switched capacitor type delay circuit 3-1 to 3-9.3-. A~
3-C is connected. Delay circuits 3-1 to 3-9.2
-A to 3-C delay time d 1 ”' d q r d
a “” d Capacitor C+j (1,
j=1-9. A to C), and weighting is performed by circuits 2-1 to 2-1.
2-9.2-A to 2-C are weighting coefficients h1 to h, respectively.
,.

It has hA-hc.

Further, each of the delay circuits 3-1 to 3-9.3-A to 3-C is connected to the output terminal 5, and the delayed signals are combined and output. Delay circuit 3-1 to 3-9.2-A to input terminal 1
3-C and each delay circuit 3-1 to 3-9.2-A to
3-C is weighted respectively in circuits 2-1 to 2-9.2-A
It is also possible to connect ~2-C. That is, whether the weighted signal is delayed or the delayed signal is weighted, the combined output signal will be the same.

FIG. 6 shows a unit switched capacitor, in which the switch Sij, St=゛ connects the capacitor Ci and the terminal 6.
．． The connection with 7 is switched. That is, the signal from terminal 6 is connected to capacitor C! in the illustrated state. j, and is output to terminal 7 by switching the switches S, ij+Sfj''.

FIG. 7 shows a case where the switch S ij+ Sijo is configured with a CMOS transistor, and the clock (No. 8 φ!j+ $ij+ φij' + Jij")
A switching operation of the switches S i j + S i j' is performed. Each clock signal φ! j+ dth, φ
, J", positive 8j" is φ, j="1", positive 1 j' =
"0", φ1. When ゛ = "θ", Lj' = "1", the capacitor Cj j is connected between the terminal 6 and the ground, is charged by the signal from the terminal 6, and then the clock signal φij is set to "0". Therefore, the capacitor Ci j is disconnected from the terminal 6 and the charged charge is held.
−“O”, positive irregularity = 11″, φij” = “1”, positive I
J" - "0", the capacitor C4J is connected between the terminal 7 and the ground, and the signal charge is output to the terminal 7. Therefore, the signal at the terminal A is generated when the capacitor C4J is disconnected from the terminal 6. After being connected to the terminal 7, there is a time delay before the signal is output to the terminal 7.

Delay circuits 3-1 to 3-9.3-A to 3- in Fig. 5
C connects the unit switched capacitor shown in FIG. 7 with delay times d, -d9. It is constructed by connecting a number corresponding to dA-dc. That is, the delay circuit 3-1
is composed of one unit switched capacitor, the delay circuit 3-2 is composed of two unit switched capacitors, and the delay circuit 3-C is composed of 12 unit switched capacitors.
It consists of a capacitor.

FIG. 8 shows the delay circuits kl~3-9.3-A~3-C with delay times d, ~d,, dA-dc.
Clock signal φij that operates +S i j゛
, φ4J゛ is an explanatory diagram. Switch S i j +
Write the clock signal φ to connect the capacitor Cj between the terminal 6 and the ground by operating the S i j'', and write the clock signal φ to connect the capacitor C4j between the terminal 7 and the ground. The clock signal S1j'' will be referred to as a read clock signal.

In the delay circuit 3-1, the write clock signal φ11 and the successive clock signal φ,1゛ have a period T and are 180° apart.
The capacitor C11 is connected between the weighted circuit 2-1 and the ground when the write clock signal φ11 is “1”, and the output terminal is connected to the output terminal when the successive clock signal φ, l is “1”. 5 and ground, and the output signal of the weighting circuit 2-1 is delayed and outputted to the output terminal 5.

Also, in the delay circuit 3-2, the write clock signal φz3
．． φ2m+φ21'' and φ2□° each have a period of 2T, and when the write clock signal φ2□ is "1", the capacitor C72 is connected between the weighting circuit 2-2 and the ground, and the period is 2T. When the subsequent write clock signal φ1 is "1", the capacitor CZ+ is connected between the weighted circuit 2-2 and ground, and the write clock signal φ2. from 1.5
When the successive cross-cross signal φ22' is "1" after time T, the capacitor C2□ is connected between the output terminal 5 and the ground, and the successive clock signal φ2. When ゛ is "L", the capacitor C21 is connected between the output terminal 5 and the ground. Therefore, the delay time difference between the delay circuit 3-1 and the delay device 1iIi3-2 is T time. Similarly, the delay time difference between adjacent delay circuits becomes T time. Also, delay circuit 3-
At C, write clock signals φC1 to φ0 . and successive clock signals φ6.
゛ ~φcc' each has a period of 12T,
The write clock signals φ, 1 to ψcc sequentially have a phase difference of T, and the successive clock signals φC1° to φCC' also sequentially have a phase difference of T.
It has a phase difference of .

Moreover, the weighting circuits 2-1 to 2-9.2-A to 2-C can be realized, for example, by the configurations shown in FIGS. 9 and 10, and FIG. The weighting that gives the weighting coefficient hij indicates a circuit, 8 is an input terminal, 9 is an output terminal, OPI is an operational amplifier, and R1 and R2 are resistors. The negative weighting factor h 4j is given by h+J=R2/R1. Also, in the 10th time, the weighting that gives a positive weighting coefficient h1j indicates a circuit, 10 is an input terminal, 11 is an output terminal, OF2
is an operational amplifier, and R3 and R4 are resistors. The positive weighting factor h ij is given by h, ,=R3/(R3+R4).

As mentioned above, the previously proposed transversal filter using a switched capacitor type delay circuit has a capacitor C4j and a switch Sij constituting the delay circuit.
+Sij゛ and weighting have the advantage that the resistors, operational amplifiers, etc. constituting the circuit can be easily integrated into an integrated circuit. However, since a weighting circuit is provided for each tap, the structure is still complicated and further miniaturization cannot be achieved.

OBJECTS OF THE INVENTION It is an object of the present invention to make it possible for weighting to reduce the number of circuits.

Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a switched capacitor type delay circuit corresponding to a tap that branches an input signal into a plurality of parts, and a switched capacitor type delay circuit that is connected in common to the delay circuit corresponding to the taps having the same weighting coefficient. The proposed weighting can be made with a circuit and the weighting can be halved compared to the previously proposed circuit. Examples will be described in detail below.

Embodiment of the Invention FIG. 1 is a circuit diagram of a main part of a 12-tap transversal filter according to an embodiment of the invention. Six weighting circuits 2-1 to 2-6 are connected to input terminal 1. The delay circuits 3-1 and 3-C are connected to the weighting circuit 2-1, the delay circuits 3-2.3-B are connected to the weighting circuit 2-2, and the weighting circuit A delay circuit 3-3.3-A is connected to 2-3. Similarly, delay circuits 3-6 and 3-7 (not shown) are connected to the weighting circuit 2-6. Each of the delay circuits 3-1 to 3-9.3-A to 3-C is connected to the output terminal 5. Therefore, two taps of each of the 12 taps are shared and weighted in circuits 2-1 to 2-6.
are connected, and one weighting circuit has a configuration in which two delay circuits are connected to the circuit. Also, each delay circuit 3-1
~3-9゜3~A~3-C are of the switched capacitor type similar to the configuration shown in FIG. It has a capacitor.

Looking at the impulse response, as shown in Figure 3,
The waveform becomes symmetrical around the peak point.

Therefore, in a 12-tap transversal filter, the weighting coefficients are h,=hc, ht=tl+, h3
= hA, ha = hq, hs = h, hb = h. Weighting is used to share the circuit for taps corresponding to the same weighting coefficient, and weighting is applied to circuit 2.
-1 is the weighting coefficient. Weighting is the circuit 2-2 is the weighting coefficient h2.
, the weighting is done by the weighting coefficient h3 for the circuit 2-3, and the weighting is done by the circuit 2
-4 is the weighting coefficient h4, the weighting is 1 for the circuit 2-5, the weighting coefficient h6 is the weighting for the circuit 2-6, and the weighting coefficient h c "" h ? The weighting is shared with the circuit. Therefore, for even taps, weight the circuit first? It can be halved for the proposed circuit. Further, in the case of an odd number of taps, when the number of taps is N, the weighting of (N+1)/2 can be set to the number of circuits.

As described in detail, the present invention includes switched capacitor type delay circuits 3-1 to 3-9.3-A to 3-C corresponding to taps that branch an input signal into a plurality of Delay circuits 3-1 to l-9, 3-A to corresponding to taps with equal coefficients
The weighting commonly connected to 3-C includes circuits 2-1 to 2-6, and compared to the previously proposed transversal filter, the weighting reduces the number of circuits by half. This has the advantage of making it easier to integrate the circuit.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a main part of an embodiment of the present invention, Fig. 2 is a block diagram of a transversal filter, Fig. 3 is an explanatory diagram of impulse response waveforms and weighting coefficients, Fig. 4 is a frequency characteristic curve diagram, Fig. 5 is a circuit diagram of the main part of the transversal filter proposed earlier, Fig. 6 is a circuit diagram of a unit switched capacitor, and Fig. 7 is a circuit diagram of a unit switched capacitor whose switch is configured by a CMO3) transistor. , FIG. 8 is an explanatory diagram of a clock signal, and FIGS. 9 and 10 are weighted circuits. 1 is an input terminal, 2-1 to 2-n, 2-A to 2-C
are weighted circuits, 3-1 to 3-n,' 3-A to 3-
C is a delay circuit, 4 is an adder circuit, 5 is an output terminal, CI j
is a capacitor, φij+? ;ij is a write clock signal, φ8, ”,?;.゛ is a read clock signal, S8 is a switch. Patent applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 10 Figure 2 (1 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] It is characterized by comprising a switched capacitor type delay circuit corresponding to a tap that branches an input signal into plurality, and a weighting circuit connected in common to the delay circuit corresponding to the taps having the same weighting coefficient. transversal filter.