JPS60245257A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the improvement in yield of appearance screening by preventing cracks from generating in a passivation film, by a method wherein heat treatment is carried out in a state that a metal is adhered over the whole surface of a semiconductor substrate. CONSTITUTION:A through-hole is bored in a field oxide film 2 located on a semiconductor substrate at point to form a bump electrode, i.e. above an A electrode pad 3. After Al 5 is evaporated over the whole surface of the substrate 1, Ti 6 and Pt 7 are evaporated. The Ti 6 and Pt 7 as the intermediate matallic layer is patterned by fusing resist and heat-treated. At this time, a one-layer electrode wiring 10 and a passivation film 4 do not come into bi-metal structure because of metal adhesion over the whole surface of the substrate 1; therefore, cracks do not generate. Since cracks in the passivation film can be thus prevented, the yield of appearance screening can be improved, and the surface of the substrate can be protected from moisture and the like. Consequently, the titled device of high reliability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method of manufacturing a semiconductor device having bump electrodes.

(Prior art) Semiconductor devices having bump electrodes are generally TAB (TAPE AUTO-MAT) using a film carrier.
It is used for the ED BONDING method and flip chip bonding using solder.

An example of a method for manufacturing a semiconductor device having bump electrodes ThT
Taking an AB banzo electrode as an example, the steps of the manufacturing method of the present invention will be described with reference to FIG. 1.

As shown in FIG. 1(a), an At electrode 9 electrode 3 is formed on a filled oxide film 2 formed on a semiconductor substrate 1 at a location where a bump electrode is to be formed, and a passivation film is further formed by CVD. After growing the At electrode pad 4, a through hole is formed on the At electrode pad 3.

Generally, a phosphorus-doped glass film (PEG film) is used for the cipation film 4.

Next, as shown in FIG. 1(b), after t5' is deposited on the entire surface of the semiconductor substrate 10 (as a current conducting layer for electroplating used in subsequent steps), except for the areas where bump electrodes will be formed. After patterning with a resist in a normal photolithography process, Ti6, Pt7 is vapor-deposited, and then the resist is bath-dissolved with a solvent such as acetone to form bumps with QrKTi6, Pt. 7
Do nono and turning.

Here, the Ti 6 as the intermediate metal layer is a metal in close contact with the field oxide film 2 and the A/=5 as the current conducting layer, and the Pt 7 At electrode pad 3 as the intermediate gold maple layer.
, A45 and the subsequently formed Au bumps or solder bumps.

Next, as shown in FIG. 1(c), a normal photolithography process is performed to cover the areas other than the areas where bump electrodes will be formed using the cyst 8, and then the At layer 5 is used as a current conductive layer. Then, a pan film and a weld 9 are formed by a plating method.

Next, as shown in FIG. 1(d), after the plating mask resist 8 is removed using a normal solvent, the AtS is removed using an At etchant used in the semiconductor industry.

After that, the modern interface, that is, the At electrode A' end 3 and the At
5, the interface between At5 and Ti6, the interface between Ti6 and Pt7, and the interface between Pt7 and bump electrowelding metal 9, and to improve the adhesion strength of the interface. In order to restore the electrical characteristics of bipolar transistors (MOS) transistors, heat treatment is usually performed at a temperature of 350 to 450°C.

After performing this heat treatment and checking the quality of the electrical characteristics, the semiconductor substrate 1 is divided into individual chips.

In the above, an example of a method for manufacturing a semiconductor device in which the pan f electric contact is completely blind is shown in FIG. 1, but other examples include At5 and T
There is a method of manufacturing a semiconductor device having a structure in which Ti, Cr-t, etc. are used as i6, Cu, Ni, etc. are used as Pt7 as an intermediate gold layer for diffusion barrier.

However, either manufacturing method ultimately requires heat treatment to reduce the contact resistance at the metal interface and restore the trough transistor characteristics.

However, performing this heat treatment causes the following drawbacks. That is, by carrying out the heat treatment, cracks are very likely to occur in the sorption film 4, and it no longer functions as a surface stabilizing film. The occurrence of these cracks reduces the yield of appearance screening on chips.

Furthermore, when all the packages of semiconductor devices with cracks are mounted, if moisture or contaminants such as impurity ions contained in the package 1 reach the cracks, each element may be interconnected. It corrodes the electrode wiring.

Furthermore, the ingress of moisture and dirt adversely affects the electrical characteristics (leakage current, breakdown voltage, etc.) of the semiconductor element. In any case, the occurrence of cracks in the passivation film 4 is undesirable from the viewpoint of reliability.

Although the occurrence of cracks can be prevented by performing heat treatment at a low temperature, it is not possible to sufficiently recover the characteristics of the semiconductor element, reduce the contact resistance, or increase the adhesion strength.

In particular, this crack is likely to occur in the groove 4 on the electrode wiring (1-layer wiring) that interconnects each element, and the cross section where the crack has occurred is shown in the circle A in Figure 2. show. The mechanism of this occurrence is the one-layer electrode wiring 10 and No. 4.
This can be explained by the difference in thermal expansion coefficient with the cipation film 4.

In other words, the commonly used 4cipation film 4I
The thermal expansion coefficient of the riPSG film (phosphorus silica glass) is 8.7 x 10 'dgg-'', and the thermal expansion coefficient of AtO used in the single-layer electrode arrangement m10 is 29.
X 110-5de'', which is a difference of approximately two orders of magnitude.

Therefore, in the heat treatment process, when the temperature is elevated, the single-layer electrode wiring 10 has a large coefficient of thermal expansion, so the passivation film 4 receives tensile stress, causing the surface of the passivation film 40 to become concave. Warp.

Further, in the heat treatment step, when the temperature is lowered, the oscivation film 4 is subjected to compressive stress and the surface of the oscivation film 4 is warped to make it convex.

As described above, by performing the heat treatment process, the passivation film 4 is subjected to high thermal stress, and when the thermal stress exceeds a certain critical value, cracks occur in the passivation film 4.

This occurs because the two materials with different coefficients of thermal expansion form a bimetallic structure, and the heat treatment can be performed without forming a bimetallic structure.

(Objective of the invention) The object of the invention is to completely prevent the occurrence of cracks in the passivation film, improve the appearance screening yield p, completely protect the surface of the semiconductor substrate from moisture, etc., and achieve high reliability. An object of the present invention is to obtain a method for manufacturing a semiconductor device that allows a semiconductor device to be obtained.

(Summary of the Invention) The key point of the present invention is to perform heat treatment (sink) on the entire surface of a semiconductor substrate with metal completely deposited thereon.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described again with reference to FIG. 1 (aJ to FIG. 1 (dl).

First, as shown in FIG. 1(a), a through hole is formed on the field oxide film 2 formed on the semiconductor substrate 1 where all the bump electrodes are to be formed, that is, on the At pad 3. .

Subsequently, as shown in FIG. 1(b), after AtS is deposited on the entire surface of the semiconductor substrate 1 as a current conducting layer for electroplating to be used in subsequent steps, ordinary photorin is applied to areas other than those where bump electrodes can be formed. In the process, after patterning with a resist, Ti6 and Pt7 are vapor-deposited, and then all the cysts are dissolved with a solvent such as A7T, and an intermediate metal layer is formed at the location where the bump electrode is to be formed. Ti6. Perform Pt7 no and turning.

After patterning Ti6 and Pt7, the interface between At electrode pad 3 and At5 as a current conducting layer, At5
Reduction of contact resistance and improvement of adhesion strength at the interface between At5 and Ti6, and the interface between Ti6 and Pt7, and At5, Ti6.
In order to recover the NM damage of Pt7, heat treatment is performed 1. This heat treatment is called the first heat treatment. In this example, since At5 and Pt7 were exposed on the surface of the semiconductor substrate 1, the heat treatment could be performed in a normal nitrogen atmosphere.

Since the entire surface of the semiconductor substrate 1 is coated with metal,
Since the single-layer electrode arrangement IwJO and the passivation film 4 do not have a bimetal structure, cracks do not occur.

Strictly speaking, since the thermal expansion coefficients of the semiconductor substrate 1 and the field oxide film 2 are also involved, cracks do not occur even in areas where the single-layer electrode wiring 10 is not present. therefore,
The heat treatment temperature can also be as high as about 450°C.

Next, as shown in FIG. 1(c), after using a normal photolithography process, the resist 8 is used to remove the areas where bump electrodes are to be formed, and then the At layer 5 is used as a current conductive layer to conduct electricity. The bump electric weld 9 is formed by a plating method.

Next, as shown in FIG. 1 (dl), after removing the plating mask resist 8 with an ordinary solvent, and removing At5 with an At elastomer used in the semiconductor industry, P
A second heat treatment is performed to reduce the contact resistance and improve the adhesion strength at the interface between t7 and the bump electroweld metal 91. Usually, in the second heat treatment, the damage caused by vapor deposition has already been removed from the first one.
Since it is recovered by heat treatment, it has low In (300℃
The following heat treatment is sufficient.

Further, since the heat treatment is performed at a low temperature, cracks do not occur in the passivation film 4. Furthermore, this second heat treatment may be omitted since heat is added in the subsequent bonding process.

As described above, one embodiment of the present invention is characterized in that the heat treatment is performed while the entire surface of the semiconductor substrate 1 is coated with metal.

In the embodiment of the present invention, the first-layer electrical wiring 1o and the At10 of the IP shielding film 4 are placed in the middle of the passivation film 4t to form a sandwich structure, so that stress balance is maintained. Therefore, even if heat treatment is performed at a high temperature of about 450° C., no cracks are observed in the passivation film 4.

As another example, even if Ti or Cr is used for At5, the passivation film 4 can be cracked by performing heat treatment with Ti or Or metal deposited on the entire surface of the semiconductor substrate 1. can be prevented from occurring.

(Effects of the Invention) As described above, in the present invention, since the heat treatment is performed with the metal coated on the entire surface of the semiconductor substrate, it is possible to prevent the occurrence of cracks in the passivation film. As a result, the appearance selection yield is improved, and the entire surface of the semiconductor substrate can be completely protected from moisture, making it possible to provide a highly reliable semiconductor device.

In addition, since the heat treatment can be carried out at a sufficiently high temperature, it is possible to completely recover from the damage caused by vapor deposition9, especially the current amplification factor of bipolar transistors or the deterioration of the threshold voltage characteristics of MOS transistors, and the yield of electrical characteristics is also significantly improved. can be done.

[Brief explanation of drawings]

FIGS. 1(al) to 1(d) are process explanatory diagrams of the conventional method and the embodiment of the semiconductor device manufacturing method of the present invention, respectively, and FIG. 2 is a /4' in the conventional semiconductor device manufacturing method.
FIG. 3 is a diagram showing a sivation crack. 1... Semiconductor substrate, 2... Field oxide film, 3...
...Alt! Pad, 4... Riyascivation film, 5
...M. 6...Ti, 7...Pt, 8...Resist, 9...
...Banzo electric rod, 10...1 layer electrode wiring. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 (a) Figure 1 (b) Figure 1 (c) Figure 1vyJ (d) Figure 2

Claims (1)

[Claims] A step is to form a polar pad at the location where the contact electrode is to be formed on the field barrier film on the semiconductor substrate and to fully open the through hole, and to form a current conductive layer by electroplating on the entire surface of the semiconductor substrate. There is an intermediate gold nugget layer where the electrode is formed and swells! a step of turning and performing a first heat treatment, and a step of applying electricity to the current conductive layer after the first heat treatment to form a vanzo electrode on the intermediate metal layer, and then removing the current conductive layer and performing a second heat treatment. A method for manufacturing a semiconductor device, comprising: