JPS60245179A - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory deviceInfo
- Publication number
- JPS60245179A JPS60245179A JP10099884A JP10099884A JPS60245179A JP S60245179 A JPS60245179 A JP S60245179A JP 10099884 A JP10099884 A JP 10099884A JP 10099884 A JP10099884 A JP 10099884A JP S60245179 A JPS60245179 A JP S60245179A
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate insulating
- semiconductor memory
- nonvolatile semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 14
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 14
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 8
- 230000001590 oxidative effect Effects 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 3
- 229910052710 silicon Inorganic materials 0.000 claims 3
- 239000010703 silicon Substances 0.000 claims 3
- 238000000034 method Methods 0.000 abstract description 7
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 239000010408 film Substances 0.000 abstract 8
- 150000002500 ions Chemical class 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体集積回路、特に不揮発性半導体メモリ
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to semiconductor integrated circuits, and in particular to nonvolatile semiconductor memory devices.
２１＼−７
従来例の構成とその問題点
不揮発性半導体メモリ装置は、電源が切られても書き込
まれた情報を記憶している装置であり、構造としては、
絶縁膜中のトラ、ノブを利用するＭＮＯＳ型と絶縁膜中
にゲートを設けたフローティングゲート型に代表される
。本発明は、前記ＭＮＯＳ型と類似した構造および情報
記憶機構をもつので、以下にＮＭＯ８構造不揮発性半導
体メモリ装置の構造とその問題点について述べる。21\-7 Configuration of conventional example and its problems A nonvolatile semiconductor memory device is a device that stores written information even when the power is turned off, and its structure is as follows:
Typical examples include the MNOS type, which uses tabs and knobs in the insulating film, and the floating gate type, which has a gate in the insulating film. Since the present invention has a structure and information storage mechanism similar to the MNOS type, the structure of the NMO8 structure nonvolatile semiconductor memory device and its problems will be described below.
第１図に従来のＭＮＯ８構造不揮発半導体メモリ装置の
基本構造を示した。これはソース・ドレイン５の形成工
程捷での断面図を表わしている。FIG. 1 shows the basic structure of a conventional MNO8 structure nonvolatile semiconductor memory device. This shows a cross-sectional view of the source/drain 5 during the formation process.
ゲート絶縁膜は、２０人程度の薄いＳｉｏ２からなる第
１層ゲート絶縁膜２（以下ではトンネルＳ１０２膜とい
う）と、２ｏｏ入程度のＳ ｉ ａ、 Ｎ４からなる第
２層ゲート絶縁膜３によって構成されており、その上に
多結晶Ｓｉ あるいは金属によるゲート電極４が形成さ
れている。記憶情報の書き込みは、ゲート電極４へ通常
動作電圧より高い電圧を印加することにより、Ｓｉ基板
１からトンネルＳｉＯ２２全通して電子をトンネル５ｉ
Ｏ−２と５１３Ｎ４膜３の界面に注入し、ここにある界
面トラップに電子をトラップすることによって行なわれ
る。この書込み電圧はトンネルＳ １０２膜に印加され
る電界によって規定される。最近の高集積化された半導
体装置においては、ホットエレクトロン等の問題に起因
して動作電圧を低くするという必要性に迫られているが
、不揮発半導体メモリ装置の書き込みあるいは消去の電
圧も、上記の必要性に伴なって低電圧化が望まれている
。書き込みあるいは消去の低電圧化を図るためには、先
に述べたようにトンネルＳ ｉＯ２２に印加される電界
が低い外部電圧でも書き込みあるいけ消去に必要な電界
となるようにしなければならない。したがって第２層ゲ
ート絶縁膜を薄くするかあるいは第２層ゲート絶縁膜と
して高誘電率材料を用いることが必要となる。第２層ゲ
ート絶縁膜としてのＳｉ３Ｎ４膜３は１９０人程変効限
界といわれているので、Ｓｉ３Ｎ４膜に代わる高誘電率
材料の採用が望捷れる。The gate insulating film is composed of a first layer gate insulating film 2 (hereinafter referred to as tunnel S102 film) made of about 20 thin Sio2 and a second layer gate insulating film 3 made of Si a, N4 of about 2000 ml. A gate electrode 4 made of polycrystalline Si or metal is formed thereon. Writing of memory information is performed by applying a voltage higher than the normal operating voltage to the gate electrode 4 to send electrons from the Si substrate 1 through the entire tunnel SiO22 to the tunnel 5i.
This is done by injecting into the interface between O-2 and 513N4 film 3 and trapping electrons in the interface traps there. This write voltage is defined by the electric field applied to the tunnel S102 film. In recent highly integrated semiconductor devices, there is a need to lower the operating voltage due to problems such as hot electrons, but the write or erase voltage of nonvolatile semiconductor memory devices is also As the need arises, lower voltage is desired. In order to reduce the voltage for writing or erasing, it is necessary to ensure that the electric field applied to the tunnel SiO 22 is sufficient for writing or erasing even at a low external voltage, as described above. Therefore, it is necessary to make the second layer gate insulating film thinner or to use a high dielectric constant material as the second layer gate insulating film. Since the Si3N4 film 3 as the second layer gate insulating film is said to have an effective limit of about 190, it is desirable to use a high dielectric constant material in place of the Si3N4 film.
また、第１層ゲート絶縁膜として用いるトンネルＳｉＯ
２膜は非常に薄い（約２０人）ことが必要であるが、こ
のような膜を良質でかつ均一性よく形成することはプロ
セス的に難しく、問題であった。In addition, tunnel SiO used as the first layer gate insulating film
The two films need to be very thin (approximately 20 people), but it is difficult to form such a film with good quality and uniformity in terms of process, which poses a problem.
発明の目的
本発明はこのような問題に鑑み、低書き込みおよび消去
電圧で、かつ良質のトンネルＳ ｉｏ ２膜を有する不
揮発性半導体メモリ装置を提供することを目的とする。OBJECTS OF THE INVENTION In view of the above problems, an object of the present invention is to provide a nonvolatile semiconductor memory device having low write and erase voltages and a high quality tunnel S io 2 film.
発明の構成
本発明は、Ｓｉ基板上に複数層のゲート絶縁膜を有する
半導体装置において、第２層ゲート絶縁膜としてＴａ２
０６という高誘電率材料を用いることにより低い書き込
みおよび消去電圧の不揮発性半導体メモリ装置を実現し
、第１層ゲート絶縁膜である薄いＳ １０２膜をＴａ２
０５膜形成の後に酸化雰囲気中でＳｔ基板とＴａ２Ｏ，
膜との界面酸化により形成することにより良質のトンネ
ルＳ ＩＯ２膜を形成可能とするものである。Structure of the Invention The present invention provides a semiconductor device having multiple layers of gate insulating films on a Si substrate, in which Ta2 is used as the second layer gate insulating film.
A nonvolatile semiconductor memory device with low write and erase voltages was realized by using a high dielectric constant material called 06, and the thin S102 film, which is the first layer gate insulating film, was replaced with Ta2.
05 After film formation, St substrate and Ta2O,
By forming the film by oxidation at the interface with the film, it is possible to form a high quality tunnel SIO2 film.
実施例の説明 ６ ／、 。Description of examples 6/,.
第２図に本発明の実施例を工程順に断面構造で示した。FIG. 2 shows a cross-sectional structure of an embodiment of the present invention in the order of steps.
捷ずＳｔ基板１上にＴａ２０６膜６を形成する。（第２
図（ａ））Ｔａ２０６膜６の形成にはＴａ膜の堆積の後
酸化雰囲気中、５００〜６００℃で酸化処理を行なうあ
るいはＴａ膜の陽極酸化を行なうあるいはＴａやＴａ２
Ｏ，ターゲットを用いた反応性スパッタによりＴａ２０
６膜を堆積するあるいはＣＶＤ法によりＴａ２０６膜を
堆積するなどの方法を用い、たとえば膜厚４００八程度
のＴａ２ｏ６膜６を形成する。次に７００〜８００℃の
水蒸気雰囲気中または８００〜１ｏｏｏ℃の酸素雰囲気
中で、Ｔａ２ｏ５膜６を通して酸化種をＳｉ基板１との
界面にまで到達させＳｔ基板１表面を酸化し、たとえば
膜厚２〇八程度のトンネルＳｉＯ２膜２を形成する（第
２図（ｂ））
次にＴａ２０５膜６上に多結晶シリコンあるいは金属あ
るいは金属シリサイドからなるゲート電極４を形成する
。（第２図（Ｃ））このゲート電極４あるいはそのパタ
ーン形成に用いたレジスト膜をマスクとして、Ｔａ２０
５膜６とトンネルＳｉＯ２膜２′６ メ＼−１
とをエツチングする。（第２図（ｄ））エツチングには
、たとえば０３Ｆ８あるいはＣＨＦ３等のガスを用いた
反応性スパッタエツチングを用いる。つづいて、イオン
注入によりソース・ドレイン領域６を形成する。（第２
図（ｅ））この後層間絶縁膜形成。A Ta206 film 6 is formed on the St substrate 1 without removing it. (Second
Figure (a)) To form the Ta206 film 6, oxidation treatment is performed at 500 to 600°C in an oxidizing atmosphere after the Ta film is deposited, or the Ta film is anodized, or Ta or Ta2
Ta20 by reactive sputtering using O, target
Using a method such as depositing a Ta206 film or depositing a Ta206 film by CVD, a Ta2O6 film 6 having a thickness of, for example, about 400.88 cm is formed. Next, in a water vapor atmosphere at 700 to 800°C or an oxygen atmosphere at 800 to 100°C, oxidizing species are allowed to reach the interface with the Si substrate 1 through the Ta2O5 film 6 to oxidize the surface of the St substrate 1. A tunnel SiO2 film 2 of about 08 is formed (FIG. 2(b)). Next, a gate electrode 4 made of polycrystalline silicon, metal, or metal silicide is formed on the Ta205 film 6. (FIG. 2(C)) Using this gate electrode 4 or the resist film used for its pattern formation as a mask,
5 film 6 and tunnel SiO2 film 2'6 me\-1 are etched. (FIG. 2(d)) For etching, reactive sputter etching using a gas such as 03F8 or CHF3 is used. Subsequently, source/drain regions 6 are formed by ion implantation. (Second
Figure (e)) After this, interlayer insulating film is formed.
コンタクト孔形成、金属配線形成、パッシベーション膜
形成等の工程を経て、不揮発性半導体メモリ装置が完成
される。A nonvolatile semiconductor memory device is completed through steps such as forming contact holes, forming metal wiring, and forming a passivation film.
以上のようにしてトンネルＳ １０２膜上に高誘電率を
もつＴ ａ ２０ ｓ膜を形成した構造にすると、ＭＮ
Ｏ８構造に比べ書き込みあるいは消去電圧を低くするこ
とができる。具体的に言うと、トンネルＳｉＯ２膜２′
の膜厚と比誘電率をｔｌ、ε１ とし、第２層ゲート絶
縁膜６の膜厚と比誘電率をｔ２゜ε２とすると、トンネ
ルＳ １０２膜２′に一定の電界を印加するために必要
な外部電圧は、ｔ、＋ｔ２×（６１／ε２）に比例する
。ｔｌに比べてｔ２がか゛なり大きいことと、ＳｉＯ２
、Ｓｉ３Ｎ４ 、Ｔａ２０６のそれぞれの誘電率が約４
、７ 、２５であることを考慮すれば、ＭＮＯ８構造
のＳｉ３Ｎ４膜をＴａ２０５膜に置き換えることにより
書き込み／消去のかなりの低電圧化が実現できる。If a structure is formed in which a T a 20 s film with a high dielectric constant is formed on a tunnel S 102 film as described above, MN
The write or erase voltage can be lowered compared to the O8 structure. Specifically, the tunnel SiO2 film 2'
Let the film thickness and dielectric constant of the second layer gate insulating film 6 be tl, ε1, and the film thickness and dielectric constant of the second layer gate insulating film 6 be t2°ε2. The external voltage is proportional to t, +t2×(61/ε2). t2 is much larger than tl, and SiO2
, Si3N4, and Ta206 each have a dielectric constant of about 4.
, 7, and 25, by replacing the Si3N4 film of the MNO8 structure with a Ta205 film, a considerably lower write/erase voltage can be realized.
さらにトランジスタのゲート絶縁膜の誘電率が高くなる
と、トランジスタの相互コンダクタンスが大きくなり、
読み出し速度の大きい不揮発性半導体メモリ装置を実現
することができる。Furthermore, as the dielectric constant of the gate insulating film of the transistor increases, the mutual conductance of the transistor increases.
A nonvolatile semiconductor memory device with high read speed can be realized.
また、トンネルＳ １０２形成方法として、Ｔａ２０５
膜を通して酸化種をＳｉ基板界面に到達させる方法を採
用することにより、酸化種に含捷れる不純物等がＴａ２
０５膜にとらえられて、絶縁耐圧が１５ＭＶ／、以上で
あるなどの良質な酸化膜を形成することができる。In addition, as a method for forming the tunnel S 102, Ta205
By adopting a method in which the oxidizing species reaches the Si substrate interface through the film, impurities etc. contained in the oxidizing species are removed from Ta2.
05 film, it is possible to form a high-quality oxide film with a dielectric strength of 15 MV/or more.
なお、ゲート電極からトンネルＳｉＯ２／Ｔａ２０５界
面への正孔の流入を防ぐために、Ｔ ａ ２０ ｓ膜と
ゲート電極との間にたとえば薄い５１０２膜のような正
孔の流入防市膜をそう人すれば、Ｔａ２０６膜をさらに
薄く形成することが可能となる。In addition, in order to prevent the inflow of holes from the gate electrode to the tunnel SiO2/Ta205 interface, a hole inflow prevention film such as a thin 5102 film is placed between the Ta20s film and the gate electrode. For example, it becomes possible to form the Ta206 film even thinner.
発明の効果
以上のように、本発明はＴａ２０６膜を第２層ゲート絶
縁膜として用いることにより、低い書き込みおよび消去
電圧が実現できるとともに、トランジスタの相互コンダ
クタンスが大きいため動作速度が大きくなるという効果
を有し、さらに第１層ゲート絶縁膜である薄いＳ １０
２膜を第２層ゲート絶縁膜であるＴａ２０６膜形成後の
Ｓ１／／′Ｉ′ａ２ｏ５界面の酸化により形成したこと
により、良質の酸化膜が得られるという効果を有するす
ぐれた不揮発性半導体メモリ装置を実現できるものであ
る。Effects of the Invention As described above, the present invention has the effect that by using a Ta206 film as the second layer gate insulating film, low write and erase voltages can be realized, and the operation speed is increased due to the large mutual conductance of the transistor. and a thin S10 which is the first layer gate insulating film.
2 film is formed by oxidizing the S1//'I'a2o5 interface after forming the Ta206 film, which is the second layer gate insulating film, to provide an excellent nonvolatile semiconductor memory device that has the effect of obtaining a high-quality oxide film. It is possible to achieve this.
第１図は従来のＭＮＯ８構造不揮発性半導体メモリ装置
の断面図、第２図（、）〜（ｅ）は本発明の一実施例の
メモリの工程断面図である。
１・・・・・・Ｓｉ基板、２・・・・・・トンネルＳ
１０２膜、３・・・・・・Ｓｉ３Ｎ４膜、４・・・・・
・ゲート電極、５・・・・・・ソース・ドレイン領域、
６・・・・・・Ｔａ２０６膜 ２１・・・・・トンネル
Ｓ ｉＯ２膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第２図FIG. 1 is a sectional view of a conventional MNO8 structure nonvolatile semiconductor memory device, and FIGS. 2(a) to 2(e) are process sectional views of a memory according to an embodiment of the present invention. 1...Si substrate, 2...Tunnel S
102 film, 3...Si3N4 film, 4...
・Gate electrode, 5...source/drain region,
6...Ta206 film 21...Tunnel SiO2 film. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2
Claims (2)
、第１層ゲート絶縁膜として薄いＳｉＯ２膜を用い、第
２層ゲート絶縁膜としてＴ ａ、 ０５膜を用い、前記
多層ゲート絶縁膜上に多結晶Ｓｔあるいは金属あるいは
金属シリサイドをゲート電極とするＭＩＳ）ランジスタ
構造を有することを特徴とする不揮発性半導体メモリ装
置。(1) A plurality of layers of gate insulating films are provided on a silicon substrate, a thin SiO2 film is used as the first layer gate insulating film, a T a,05 film is used as the second layer gate insulating film, and the multilayer gate insulating film is 1. A nonvolatile semiconductor memory device characterized by having an MIS (MIS) transistor structure having polycrystalline St, metal, or metal silicide as a gate electrode thereon.
た後に、酸化雰囲気中で前記シリコン基板と前記Ｔ ａ
２０ ｓ膜との界面に薄いＳｉｏ２膜を形成すること
を特徴とする特許請求の範囲第１項記載の不揮発性半導
体メモリ装置。(2) After forming the Ta 20s film on the silicon substrate, the silicon substrate and the Ta 20 s film are formed in an oxidizing atmosphere.
20. The nonvolatile semiconductor memory device according to claim 1, wherein a thin Sio2 film is formed at the interface with the 20S film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10099884A JPS60245179A (en) | 1984-05-18 | 1984-05-18 | Nonvolatile semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10099884A JPS60245179A (en) | 1984-05-18 | 1984-05-18 | Nonvolatile semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60245179A true JPS60245179A (en) | 1985-12-04 |
Family
ID=14288957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10099884A Pending JPS60245179A (en) | 1984-05-18 | 1984-05-18 | Nonvolatile semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60245179A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677438A (en) * | 1990-09-22 | 1994-03-18 | Samsung Electron Co Ltd | Manufacture and structure for nonvolatile semiconductor memory device provided with storage cell array and with peripheral circuit |
| JP2005537662A (en) * | 2002-08-29 | 2005-12-08 | フリースケール セミコンダクター インコーポレイテッド | Dielectric storage memory cell (MONOS) with high dielectric constant top dielectric and method therefor |
-
1984
- 1984-05-18 JP JP10099884A patent/JPS60245179A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0677438A (en) * | 1990-09-22 | 1994-03-18 | Samsung Electron Co Ltd | Manufacture and structure for nonvolatile semiconductor memory device provided with storage cell array and with peripheral circuit |
| JP2005537662A (en) * | 2002-08-29 | 2005-12-08 | フリースケール セミコンダクター インコーポレイテッド | Dielectric storage memory cell (MONOS) with high dielectric constant top dielectric and method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2933902B2 (en) | Method for incorporating non-volatile memory and logic components into a single sub-0.3 micron fabrication process to obtain integrated non-volatile memory | |
| JPH10163348A (en) | Manufcture of nonvolatile semiconductor storage device | |
| JP2001156276A (en) | Forming method of gate oxide layer of different thickness | |
| US5679590A (en) | Method for manufacturing contact hole for a nonvolatile semiconductor device | |
| RU2168797C2 (en) | Process of manufacture of elements of structures of very small size on semiconductor substrate | |
| JPS60245179A (en) | Nonvolatile semiconductor memory device | |
| JP3054422B2 (en) | Method for manufacturing semiconductor device | |
| JPH08107158A (en) | Floating gate type non-volatile semiconductor memory device and manufacture thereof | |
| JP3436315B2 (en) | Method of manufacturing MONOS type semiconductor nonvolatile memory device and method of manufacturing semiconductor device | |
| JP2650925B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP3082288B2 (en) | Thin film memory transistor and method of manufacturing the same | |
| JPH10189922A (en) | Manufacture of flash memory element | |
| JPH04196175A (en) | Semiconductor device and manufacture thereof | |
| TWI304642B (en) | ||
| JPH09298281A (en) | Manufacturing method of semiconductor device | |
| JPS6042632B2 (en) | semiconductor equipment | |
| JPH06196497A (en) | Manufacture of semiconductor device | |
| JP3138538B2 (en) | Semiconductor nonvolatile memory element and method of manufacturing the same | |
| KR0150669B1 (en) | Forming method of dielectric material film in the semiconductor device | |
| JPS6336575A (en) | Manufacture of semiconductor device | |
| JPH1154639A (en) | Nonvolatile semiconductor memory and fabrication thereof | |
| JPS61236165A (en) | Semiconductor memory device and manufacture thereof | |
| JPH09129758A (en) | Manufacture of semiconductor integrated circuit device | |
| JP2000332014A (en) | Insulating film | |
| JPH0936358A (en) | Fabrication of semiconductor device |