JPS60242678A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS60242678A
JPS60242678A JP9897184A JP9897184A JPS60242678A JP S60242678 A JPS60242678 A JP S60242678A JP 9897184 A JP9897184 A JP 9897184A JP 9897184 A JP9897184 A JP 9897184A JP S60242678 A JPS60242678 A JP S60242678A
Authority
JP
Japan
Prior art keywords
amorphous silicon
amorphous
film
silicon carbide
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9897184A
Other languages
Japanese (ja)
Inventor
Tetsuyoshi Takeshita
竹下 哲義
Hajime Kurihara
一 栗原
Hideaki Oka
秀明 岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP9897184A priority Critical patent/JPS60242678A/en
Publication of JPS60242678A publication Critical patent/JPS60242678A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain an amorphous nonvolatile memory, which has excellent holding characteristics and reproducibility and a large area and large capacitance and cost thereof is low, by using an amorphous silicon carbide film in place of an amorphous silicon nitride film. CONSTITUTION:An insulating substrate 11, a lower electrode 12, an N<+> type 13, which is hydrogenated previously by amorphous silicon and to which phosphorus is doped to a high degree, and an N type 14 to which phosphorus is doped similarly to a low degree are formed in the order. An silicon oxide film 15 in which amorphous silicon in oxidized through plasma anodizing, etc., a film 16, which consists of a hydrogenated amorphous silicon carbide film and contains carbon by 35atom% or more, and an upper electrode 17 are shaped in the order. Accordingly, a device having performance, which has not exist as nonvolatile memories, such as, a holding time of ten years or more, a writing time of 0.1musec or less, even fast erasing speed, a large area and large capacitance and low cost is obtained.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は非晶質や微結晶もしくは多結晶のシリコン(以
下、非晶質シリコンで代表する。)を用いた不揮発性メ
モリーに関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a nonvolatile memory using amorphous, microcrystalline, or polycrystalline silicon (hereinafter referred to as amorphous silicon).

〔従来技術〕[Prior art]

不揮発性メモリーとして酸化模と窒化@を半導体基板上
に形成した所謂NO8構造は高密度記録が可能であり、
内容の書き替えが容易に出来る等のすぐf′した利点全
数多く持っている。そのために近年、数多くの研究がな
されており固体撮像・記憶デバイス(電子通信学会技術
報告、KI)82−138)やビデオディスク(工EK
K Trans、 onE、D、、ED728−854
)などの応用が提案されている。しかし半導体基板とし
て結晶シリコンを用いる限シ大面積化して大容量にする
ことは難しく、非常に高コストとなる。そnで低コスト
で大面積化が可能な非晶質7リコンを基板として用いる
ことが提案されている(電子通信学会技術報告、5SD
−83−28)。金属−窒化膜−酸′化膜−半導体基板
型(以下、MNOSと略す。)ダイオードにおいて窒化
膜の特性にメモリー書込み特性や保持特性に大きな影響
會与える。また基板に非晶質シリコンなどを用いる限り
高温でのプロセスを用いることは水素の離脱などのため
不適当であり、プラズマ分解法による非晶質シリコン窒
化膜の堆積が用いられている。しかしプラズマ分解法に
よるシリコン窒化膜は堆積条件によって大きく変化し、
191/N比が化学当量比と異なる。
The so-called NO8 structure, in which oxide and nitride are formed on a semiconductor substrate, is capable of high-density recording as a non-volatile memory.
It has many immediate advantages, such as the ability to easily rewrite the contents. For this purpose, a large amount of research has been conducted in recent years, including solid-state imaging/storage devices (IEICE technical report, KI 82-138) and video disks (Eng.
K Trans, onE, D,, ED728-854
) and other applications have been proposed. However, as long as crystalline silicon is used as the semiconductor substrate, it is difficult to increase the area and increase the capacity, and the cost becomes extremely high. Therefore, it has been proposed to use amorphous 7-licon as a substrate, which can be made large in area at low cost (IEICE technical report, 5SD
-83-28). In a metal-nitride film-oxide film-semiconductor substrate type (hereinafter abbreviated as MNOS) diode, the characteristics of the nitride film have a large influence on the memory write characteristics and retention characteristics. Furthermore, as long as amorphous silicon or the like is used for the substrate, it is inappropriate to use a process at high temperature due to the release of hydrogen, etc., and therefore deposition of an amorphous silicon nitride film by plasma decomposition is used. However, silicon nitride films produced by plasma decomposition vary greatly depending on the deposition conditions.
The 191/N ratio is different from the chemical equivalent ratio.

そ几ゆえに結合が不完全になりやすぐ低抵抗の窒化膜と
なってしまい、MNOSダイオードとしての保持特性や
再現性に対して大きな問題となる。
As a result, the coupling becomes incomplete and the film quickly becomes a low-resistance nitride film, which poses a major problem in terms of retention characteristics and reproducibility as an MNOS diode.

該非晶質シリコン窒化膜を高抵抗にするにはプラズマ分
解用高周波電力を大きぐすることや堆積時の基板温度を
高くすることが考えられるが前者は装置が太きぐなり高
コストとなり後者は基板である非晶質シリコンに悪影響
を及ぼしメモリーとして再現性が問題となる。
In order to make the amorphous silicon nitride film high in resistance, it is possible to increase the high-frequency power for plasma decomposition or to raise the substrate temperature during deposition, but the former requires a thicker device and is more expensive, and the latter increases the substrate temperature. This has a negative effect on amorphous silicon, which causes problems in reproducibility as a memory.

〔目的〕〔the purpose〕

不発明にこnらの欠点全除去するもので、非晶質不揮発
性メモリーとして保持特性や再現性がすぐれていて、大
面積で大容量かつ低コストな非晶質不揮発性メモリーを
提供すること全目的とする。
To provide an amorphous nonvolatile memory which has excellent retention characteristics and reproducibility, has a large area, has a large capacity, and is low in cost, by completely eliminating these drawbacks. For all purposes.

〔概要〕〔overview〕

すなわち、該非晶質シリコン窒化膜(以下、a−8iN
と略す。)にかえて非晶質シリコン炭化膜(以下、a−
8iCと略す。)セ用いることで、すぐT′した非晶質
不揮発性メモリーが提供できる。
That is, the amorphous silicon nitride film (hereinafter, a-8iN
It is abbreviated as ) instead of an amorphous silicon carbide film (hereinafter a-
It is abbreviated as 8iC. ), it is possible to provide an amorphous nonvolatile memory that quickly reaches T'.

〔実施例〕〔Example〕

第1図は本発明の実施例の非晶質不揮発性メモリーの断
面図である。11はガラス、石英など絶縁基板、12は
アルミニウム、モリブデン、クロム、■Toなど下部電
極、15と14は非晶質シリコンで水素化されておシ、
13はリン高ドープのr3+型、14はリン低ドープの
n型で模厚はそnぞれ100〜2000Xと2000〜
20000λである、15はプラズマ陽極酸化などにニ
ジ非晶質シリコン全酸化したシリコン酸化俟で厚さ5〜
100X、16は水素化非晶質シリコン炭化膜で炭素含
有率35原子チ以上のものでち勺厚さ300〜3ooo
X、17は上部電極でアルミニウム、モリブデン、クロ
ム、■Toなどである。
FIG. 1 is a sectional view of an amorphous nonvolatile memory according to an embodiment of the present invention. 11 is an insulating substrate such as glass or quartz; 12 is a lower electrode such as aluminum, molybdenum, chromium, or To; 15 and 14 are hydrogenated amorphous silicon;
13 is a highly phosphorus-doped r3+ type, 14 is a lightly phosphorus-doped n-type, and the model thicknesses are 100~2000X and 2000~n, respectively.
20,000λ, 15 is a silicon oxide layer that has been completely oxidized by plasma anodization etc. and has a thickness of 5~
100X, 16 is a hydrogenated amorphous silicon carbide film with a carbon content of 35 atoms or more, and a thickness of 300 to 300 mm.
X and 17 are upper electrodes made of aluminum, molybdenum, chromium, ■To, or the like.

13.14.16はいずれもプラズマ分解法を用いて堆
積し*、もので、13から16は同一真空槽内で真空を
破ることなく堆積できる(以下、この構造によるものを
MOOSメモリーと呼ぶ。)。
13, 14, and 16 are all deposited using the plasma decomposition method*, and 13 to 16 can be deposited in the same vacuum chamber without breaking the vacuum (hereinafter, devices with this structure will be referred to as MOOS memories. ).

ここで、本発明で用いたa−BlCの堆積条件と従来よ
シ用いられているa、−8iNの一般的々堆積条件を比
較する(表1に示す)。
Here, the deposition conditions for a-BlC used in the present invention will be compared with the general deposition conditions for a, -8iN conventionally used (shown in Table 1).

表1 堆積条件のちがい 表1より明らかなように一般的にa−81C@の方が堆
積温度は低くてよく、かつ高周波電力は1ケタ位少なく
てすむ。しかも堆積速度はa−8’10の方が速いため
非常に低コストとなシ、装置はlJX規模のもので十分
である。また表1の条件で作製した膜の抵抗率に関して
もa−8iCはa−8i、Nと同質以上の高抵抗となる
Table 1 Differences in Deposition Conditions As is clear from Table 1, a-81C@ generally requires a lower deposition temperature and an order of magnitude less high-frequency power. Furthermore, since the deposition rate of A-8'10 is faster, the cost is very low, and an apparatus on the scale of IJX is sufficient. Also, regarding the resistivity of the film produced under the conditions shown in Table 1, a-8iC has a high resistance equal to or higher than that of a-8i and N.

さらに、電気的特性を第2図と第3図に示す。Furthermore, the electrical characteristics are shown in FIGS. 2 and 3.

第2図は本発明によるa−8iCを用いた不揮発性メモ
リー(MC!OSメモリー)の容量対電圧曲線のシフト
例であシ、21は書き込み前の曲線であシ、22は1.
0μ就幅で高さ15Vのノくルス書き込み後の曲線であ
る。書き込み時間は1.0μ就で十分である。比較とし
てa7siNを用いたメモリー(MNo sメモリー)
の容量対電圧曲線のシフト例を第4図に示す。41は書
き込む前の曲線であシ、42は1.0sec幅で高さ1
5Vのノくルス書き込み後の曲線である。従来のa−I
EiNを用いたメモリーでも書き込み時間1.0μ(6
)までは十分に卯答できるが、書き込み前とのシフトの
量を比べてみると明らかに本発明によるa−6iOを用
いたメモリーの方が太きぐ、本発明によるメモリーはさ
らに高速での書き込みに対応出来る。不揮発性メモリー
に要求されている書き込み時間が短かい(少なくとも1
.0μ就以下)という条件に本発明による例は十分に満
足しておシ、さらに短かいcL1〜Q、01μ方という
書き込み時間にも十分に応答しうるものである。
FIG. 2 shows an example of a shift in the capacity versus voltage curve of a nonvolatile memory (MC!OS memory) using a-8iC according to the present invention, 21 is the curve before writing, 22 is 1.
This is a curve after Nordic writing with a width of 0μ and a height of 15V. A writing time of 1.0 μm is sufficient. Memory using a7siN for comparison (MNo s memory)
An example of the shift of the capacitance vs. voltage curve is shown in FIG. 41 is the curve before writing, 42 is 1.0 sec wide and 1 high.
This is a curve after 5V Norculus writing. Conventional a-I
Even with memory using EiN, the write time is 1.0μ (6
), but when comparing the amount of shift before writing, it is clear that the memory using a-6iO according to the present invention is thicker, and the memory according to the present invention can write at even faster speeds. Can respond to Write times required for non-volatile memory are short (at least 1
.. The example according to the present invention fully satisfies the condition of 0μ or less) and can also respond satisfactorily to a shorter writing time of cL1 to Q, 01μ.

不揮発性メモリーとして、書き込み時間以上に重要な要
求条件として保持時間の問題がある。保持時間は出来る
だけ長い方がよく、数年以上であることが望オしい。第
6図は本発明装置のフラットバンド電圧を経過時間に対
して示したものである。書き込み条件は幅1.0μ冠で
高さ15Vのパルスによっていて、その後の放置時間を
横軸に取ッテイル。書き込み前のフラットバンド電圧ハ
2V程度であるので第3図の31のグラフより保持時間
(ここではフラットバンド電圧が上記の2vとの差で初
期電圧のIAとなる時間とする。)は10年(5600
日位)以上となり、不揮発性メモリーとして十分に使用
し得る。比較として従来のa−8iNを用いたMNOE
I型メモリーでの保持時間の特性を第5図に示す。51
が第3図と同様に書き込みパルスを15V1幅1.0μ
気としたもので保持時間は100日以下となシ用をなさ
ず、書き込みパルスを15V9幅5.5μ冠として第3
図、52のように初期のフラットバンド電圧を本発明装
置と同じ(4v程度としても保持時間は1000日(2
,7年位)以下である。さらに本発明による装置は消去
に関しても非晶質N’MO8型より短時間に問題な(消
去可能である。
As a non-volatile memory, retention time is a more important requirement than write time. The retention time should be as long as possible, preferably several years or more. FIG. 6 shows the flat band voltage of the device of the invention versus elapsed time. The writing conditions were a pulse with a width of 1.0μ and a height of 15V, and the subsequent standing time was plotted on the horizontal axis. Since the flat band voltage before writing is about 2V, the retention time (here, the time when the flat band voltage reaches the initial voltage IA due to the difference from the above 2V) is 10 years from the graph 31 in Figure 3. (5600
date) or more, and can be used satisfactorily as a non-volatile memory. MNOE using conventional a-8iN for comparison
FIG. 5 shows the retention time characteristics in type I memory. 51
The write pulse is 15V1 width 1.0μ as in Figure 3.
If the retention time is 100 days or less, the writing pulse should be set to 15V9 with a width of 5.5μ and the third
As shown in Figure 52, even if the initial flat band voltage is the same as the device of the present invention (approximately 4 V), the holding time is 1000 days (2
, 7th grade) and below. Furthermore, the device according to the present invention can be erased in a shorter time than the amorphous N'MO8 type.

以上、本発明に用いた装置の電気的特性例は第1図で1
5のシリコン酸化膜の厚さ35X、16の非晶質シリコ
ン炭化膵は炭素含有量が75原子チで厚さ850Xであ
る装置によっている。膜厚や炭素含有量に関しては第1
図を説明したときに用いた数値の範囲であるなら良好な
特性を出し得るが電気的特性例はその中で比較的良好な
ものを示しである。また第1図で16の炭化膜にボロン
やガリウムなど元素周期表■族元素を11ppBから1
100pp、%には7ppm程度添加することで保持時
間は長ぐな9、結果的に短いパルスにて書き込んでも数
年は保持出来る。第1図で16の炭化膜の炭素含有量は
35原子パ一セント以上、特には50原子パーセントか
ら85原子パーセントで炭化@製造条件を選ぶことで艮
好な結果が得られる。
As mentioned above, an example of the electrical characteristics of the device used in the present invention is shown in FIG.
The silicon oxide film of No. 5 had a thickness of 35X, and the amorphous silicon carbonized pancreas of No. 16 had a carbon content of 75 atoms and a thickness of 850X. Regarding film thickness and carbon content, it is the first
Although good characteristics can be obtained within the range of numerical values used when explaining the figures, the examples of electrical characteristics show relatively good ones within that range. In addition, in Figure 1, 16 carbide films contain elements from group II of the periodic table, such as boron and gallium, from 11 ppB to 1.
By adding about 7 ppm to 100 pp.%, the retention time is long9, and as a result, it can be retained for several years even when written with short pulses. Excellent results can be obtained by selecting carbonization conditions in which the carbon content of the 16 carbonized films in FIG. 1 is 35 atomic percent or more, particularly 50 atomic percent to 85 atomic percent.

〔効果〕〔effect〕

以上の実施例に示されるようにa−8iCを用いた非晶
質シリコン不揮発性メモリーは保持時間10年以上、書
き込み時間0.1μx以下であり、消去スピードも速く
、しかも大面積、大容量かつ低コストと不揮発性メモリ
ーとして過去にない性能を持つ装置である。
As shown in the above examples, the amorphous silicon nonvolatile memory using a-8iC has a retention time of 10 years or more, a write time of 0.1 μx or less, a fast erase speed, and a large area, large capacity, and This device is low cost and has unprecedented performance as a non-volatile memory.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のメモリー構造の断面図。第2図、第3
図は本発明の非晶質メモリーでの電気的特性図。第4図
、第5図は従来の非晶質メモリーでの電気的特性図であ
る。 以 上 第1図。 印80電Fi(V) 第2図 経恵ホ(Q) 印tIrIIJi (v) 第4図 絞過日牧 (日)
FIG. 1 is a cross-sectional view of the memory structure of the present invention. Figures 2 and 3
The figure is an electrical characteristic diagram of the amorphous memory of the present invention. FIGS. 4 and 5 are electrical characteristic diagrams of conventional amorphous memories. Above is Figure 1. Mark 80 Den Fi (V) Fig. 2 Keieho (Q) Mark tIrIIJi (v) Fig. 4 Shikaku Himaki (Japanese)

Claims (1)

【特許請求の範囲】[Claims] (1)絶縁基板上に設けた導電性電極に接して非晶質シ
リコン、微結晶シリコンもしくけ多結晶シリコンを形成
、さらにノリコン酸化膜全形成し、該酸化膜上に炭素含
有率35原子パ一セント以上の非晶質、微結晶もしくa
多゛結晶シリコン炭化膜を形成したこと全特徴とする半
導体記憶装置。 (2、特許請求の範囲第1項記載の非晶質、微結晶もし
くは多結晶シリコン炭化模にボロンやガリウムなど元素
周期表■族元素全α111)I)mから100 p p
、m添加したことを特徴とする半導体記憶装置。
(1) Amorphous silicon, microcrystalline silicon, or polycrystalline silicon is formed in contact with the conductive electrode provided on the insulating substrate, and a Noricon oxide film is entirely formed, and a carbon content of 35 atomic particles is formed on the oxide film. Amorphous, microcrystalline or a of 1 cent or more
A semiconductor memory device characterized in that a polycrystalline silicon carbide film is formed. (2. The amorphous, microcrystalline, or polycrystalline silicon carbide model described in claim 1, including boron, gallium, and other elements of group II of the periodic table, all α111) I) m to 100 p p
, m is added to the semiconductor memory device.
JP9897184A 1984-05-17 1984-05-17 Semiconductor memory device Pending JPS60242678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9897184A JPS60242678A (en) 1984-05-17 1984-05-17 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9897184A JPS60242678A (en) 1984-05-17 1984-05-17 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS60242678A true JPS60242678A (en) 1985-12-02

Family

ID=14233924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9897184A Pending JPS60242678A (en) 1984-05-17 1984-05-17 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS60242678A (en)

Cited By (14)

* Cited by examiner, † Cited by third party
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FR2677810A1 (en) * 1991-06-12 1992-12-18 Samsung Electronics Co Ltd Method of fabricating a device with semiconductors
US5411917A (en) * 1990-04-12 1995-05-02 Actel Corporation Electrically programmable antifuse incorporating dielectric and amorphous silicon interlayer
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5543656A (en) * 1990-04-12 1996-08-06 Actel Corporation Metal to metal antifuse
US5723358A (en) * 1996-04-29 1998-03-03 Vlsi Technology, Inc. Method of manufacturing amorphous silicon antifuse structures
US5789764A (en) * 1995-04-14 1998-08-04 Actel Corporation Antifuse with improved antifuse material
US6249020B1 (en) 1997-07-29 2001-06-19 Micron Technology, Inc. DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate
US6728126B1 (en) 2002-12-20 2004-04-27 Actel Corporation Programming methods for an amorphous carbon metal-to-metal antifuse
US6731531B1 (en) 1997-07-29 2004-05-04 Micron Technology, Inc. Carburized silicon gate insulators for integrated circuits
US6767769B2 (en) 2001-10-02 2004-07-27 Actel Corporation Metal-to-metal antifuse employing carbon-containing antifuse material
US6835638B1 (en) 1997-07-29 2004-12-28 Micron Technology, Inc. Silicon carbide gate transistor and fabrication process
US6965156B1 (en) 2002-12-27 2005-11-15 Actel Corporation Amorphous carbon metal-to-metal antifuse with adhesion promoting layers
US7390726B1 (en) 2001-10-02 2008-06-24 Actel Corporation Switching ratio and on-state resistance of an antifuse programmed below 5 mA and having a Ta or TaN barrier metal layer
US7459763B1 (en) 2001-10-02 2008-12-02 Actel Corporation Reprogrammable metal-to-metal antifuse employing carbon-containing antifuse material

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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