JPH05136429A - Semiconductor storage device and operation thereof - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device easily conducting read even when transistor characteristics are deteriorated when writing by forming two or more of channel regions having different threshold voltage in one transistor. CONSTITUTION:A pad oxide film 10 and a nitride film 11 are formed onto a silicon substrate 1 through LOCOS isolation and patterned, a field-oxide film 9 is formed through thermal oxidation, the nitride film 11 and the pad film 10 are removed and the field oxide film 9 is etched up to the intermediate section of the oxide film 9. When a tunnel oxide film 4 is shaped through thermal oxidation, positive charges are generated in a region, in which the field oxide film 4 is removed, and the threshold voltage of a channel region under the region is lowered. The ions of P-type impurities such as boron are implanted, a P<-> layer is formed to the silicon substrate 1, and threshold voltage is controlled at a fixed value, thus easily conducting read even when transistor characteristics are deteriorated by hot carriers on write.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash EEPRO which is one of semiconductor memory devices having a non-volatile memory.
The present invention relates to the structure of the M memory cell and its operating method.

[0002]

2. Description of the Related Art At present, the most noticeable non-volatile memory is a flash EEPROM (Electrical).
cally Erasable Programmab
LeRead Only Memory), for example, Nikkei Microdevice [73] (1991-7-1).
p. 73-75. FIG. 3 shows an example of the configuration of the flash EEPROM.

Since this flash EEPROM is composed of one transistor, it is a nonvolatile memory that is most easily integrated. An n ⁺ type drain 2 and a source 3 are formed on the surface of a P type silicon substrate 1, and a floating gate 5 for charge storage and a control gate 6 are further formed on the drain 2 and source 3 via a tunnel oxide film 4. ing. Further, the intermediate insulating film 7 is formed on the control gate 6.
Is formed, and the Al wiring 8 is connected to the drain 2 and the like through a contact hole provided in the intermediate insulating film 7.

Next, referring to Table 3, the writing of FIG.
The erasing / reading method will be described. Table 3 is a table showing applied voltage conditions for driving the flash memory cell. Here, the state in which electrons are injected into the floating gate 5 to increase the threshold voltage is referred to as writing, and conversely, the state in which electrons are extracted from the floating gate 5 to decrease the threshold voltage is referred to as erasing.

[0005]

[Table 3]

At the time of writing, the control gate 6 shown in FIG.
A positive voltage, for example, 10 V and 5 V is applied to the drain 2 and the drain 2, respectively, and electrons are injected from the silicon substrate 1 near the drain 2 to the floating gate 5 by channel hot electrons to write information.

At the time of erasing, the drain 2 is opened, the source 3 is 5 V and the control gate 6 is a negative voltage, for example, -1.
0V is applied to make the tunnel oxide film 4 on the source 3 have a high electric field. Then, Fowler Nordheim (Fow
tunneling, electrons are emitted from the floating gate 5 to the source 3 to erase information.

At the time of reading, a positive voltage, for example, 5 V and 1 V is applied to the control gate 6 and the drain 2, respectively, and information is read by detecting the on / off state of the transistor. By performing erasing / writing / reading in this way, it functions as a non-volatile memory cell.

[0009]

However, in the conventional flash EEPROM, since erasing / writing / reading is performed by one transistor, the transistor characteristics are deteriorated by channel hot carriers during writing, which makes reading difficult. There was a point.

The present invention is a conventional flash EEPRO.
It is an object of the present invention to provide a semiconductor memory device which fundamentally solves the above-mentioned problems derived from the structural characteristics of M while maintaining the characteristics of high integration.

[0011]

For the above-mentioned purpose, the present invention provides a semiconductor memory device comprising a non-volatile memory cell of a MOS type structure having two or more channel regions having different threshold voltages. It is made up of transistors.

[0012]

As described above, according to the present invention, one transistor is provided with two or more channel regions having different threshold voltages. Therefore, even if the transistor characteristics are deteriorated by hot carriers at the time of writing, reading can be performed. It can be done easily.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A feature of the present invention is a flash EEPROM using one transistor having channel regions having different threshold voltages. The threshold voltage V _T is expressed by the following equation.

[0014]

[Equation 1]

Here, φ _ms is the work function difference between the gate electrode and the silicon substrate, Q _f is the charge amount of the gate oxide film, C _i is the gate oxide film capacitance, ε _s is the dielectric constant of silicon, and q is the elementary charge, N _A is the acceptor concentration in the silicon substrate, V _BS is the substrate bias voltage, k is the Boltzmann constant, T is the absolute temperature,
_ni is the intrinsic carrier concentration. Therefore, by changing the variable on the right side of equation (1) in one transistor,
One transistor having channel regions with different threshold voltages can be manufactured.

FIGS. 1 and 2 are explanatory views of structural examples of the first and second embodiments of the n-channel semiconductor memory device of the present invention, which are taken along the line AA 'in FIG. 3 of the conventional example. Corresponds to the sectional structure. FIG. 1 shows a first embodiment of the present invention, in which the acceptor concentration in the channel region is not uniform and the P ⁻ region 12
And the P region other than that (the formation method will be described later). As can be seen from the formula (1), if the acceptor concentration (corresponding to N _A in the formula (1)) is different, the threshold voltage changes, so that in FIG. 1, one transistor has a different threshold voltage. It has two channel regions, P
^- the threshold voltage is high in the region 12. Although the n-channel type is shown in this figure, if the acceptor type is changed to a donor type impurity, it is possible to form two channel regions having different threshold voltages similarly in the P-channel type.

FIG. 2 shows a second embodiment of the present invention, in which the tunnel oxide film 4 is formed so that a positive charge exists in a part thereof (a forming method will be described later). This positive charge is Q _{f in} equation (1).
In the positive charge region, the threshold voltage becomes lower than that in other regions. Therefore, as in the first embodiment, one transistor has two channel regions. Even if a negative charge is present in a part of the tunnel oxide film 4 instead of the positive charge, the threshold voltage can be changed. Also for the P-channel type, two channels can be formed by allowing charges to exist in a part of the tunnel oxide film.

Next, a method of operating the memory cell described with reference to FIGS. 1 and 2 will be described. Table 1 shows applied voltage conditions of the n-channel type memory cell. Here, description will be made assuming that the tunnel oxide film thickness is 15 nm, the coupling ratio is 0.6, and the threshold voltages of the two channel regions are 2V and 5V.

[0019]

[Table 1]

At the time of writing, 15, 5 and 0 V are applied to the control gate, drain and source, respectively.
Under this application condition, channel hot carriers are injected into the floating gate through the tunnel oxide film in the channel region having a high threshold voltage, but become 1/10 or less in the region having a low threshold voltage. This is because the generation rate of channel hot carriers is maximized under the application condition that the drain voltage and (control gate voltage-threshold voltage) x coupling ratio are equal.

At the time of erasing, when -15, open and 5 V are applied to the control gate, drain and source, respectively, electrons are emitted from the floating gate to the source by FN tunneling, and information is erased.

At the time of reading, information is read by applying 4, 1, 0 V to the control gate, drain, and source, respectively, and detecting the on / off state of the transistor. Under this application condition, the channel region having a high threshold voltage is always in the off state, and at the time of reading, information can be read only in the channel region having a low threshold voltage. Therefore, since the channel region with a high threshold voltage is used for writing and the region with a low threshold voltage is used for reading, even if the transistor characteristics deteriorate due to channel hot carrier injection during writing, reading is easy. Can be done.

Table 2 shows applied voltage conditions of the P-channel type memory cell. Here, description will be made assuming that the tunnel oxide film thickness is 15 nm, the coupling ratio is 0.6, and the threshold voltages of the two channel regions are -6V and -9V.

[0024]

[Table 2]

At the time of writing, −9, −5 and 0 V are applied to the control gate, drain and source, respectively. Under this application condition, avalanche hot carriers (electrons) are injected into the floating gate through the tunnel oxide film in the channel region having a low threshold voltage, but become 1/10 or less in the region having a high threshold voltage. This is because the avalanche hot carrier generation rate is maximized under the application condition that the control gate voltage and the threshold voltage are equal.

At the time of erasing, if −15, open, and 5 V are applied to the control gate, drain, and source, respectively, electrons are emitted from the floating gate to the source by FN tunneling, and information is erased. This application condition is exactly the same as that of the n-channel type.

At the time of reading, -4, -1, 0 V are applied to the control gate, drain and source, respectively,
Information is read by detecting the on / off state of the transistor. Under this application condition, the channel region having a low threshold voltage is always in the off state, and at the time of reading, information can be read only in the channel region having a high threshold voltage. Therefore, like the n-channel type, the channels for writing and the channel for reading are different, so that even if the transistor characteristics deteriorate due to avalanche hot carrier injection during writing, reading can be easily performed.

The applied voltage conditions of the n-channel type and P-channel type memory cells have been described above, but the applied voltage conditions of the present invention are not limited, and the tunnel oxide film thickness, the coupling ratio, and the two channel regions are not limited. When the threshold voltage or the like changes, the optimum applied voltage condition also changes.

Next, five methods of manufacturing the device of this embodiment will be described in order, referring to FIGS. 4 to 8. In the present description, the n-channel type is shown, but the p-channel type can be manufactured by the same method only by changing the type of impurities.

(1) First Manufacturing Embodiment (corresponding to the apparatus of the above-mentioned first embodiment) FIG. 4 shows a first embodiment.

First, as shown in FIG. 4A, the silicon substrate 1
A field oxide film 9 is formed thereon by using the conventional LOCOS isolation method. For LOCOS isolation, pad oxide film 1
0 and the nitride film 11 are formed, and after the nitride film 11 is patterned, the field oxide film 9 is formed by thermal oxidation, for example, wet oxidation. Next, as shown in FIG. 4B, after removing the nitride film 11 and the pad oxide film 10, a tunnel oxide film 4 having a film thickness of, for example, about 15 nm is formed by thermal oxidation. After depositing the first-layer polysilicon 5 thereon, an n-type impurity such as phosphorus is introduced into the polysilicon layer 5.

Next, as shown in FIG. 4C, the polysilicon layer 5 is patterned to reduce the thickness of a part of the polysilicon layer 5 on the channel region to, for example, about 50 nm. Subsequently, P-type impurities such as boron are ion-implanted. In the region where the polysilicon layer 5 is thin, the P-type impurities reach the substrate 1 and the channel region 12 having a high threshold voltage can be formed. Next, as shown in FIG. 4 (d), the polysilicon layer 5 is patterned into a floating gate, and a second insulating film of polysilicon, for example, a 30 nm oxide film / nitride film / oxide film, is formed on the floating gate. Deposit layer 6. An n-type impurity is introduced into the polysilicon layer 6 and patterned to form the control gate 6. After that, although not shown, an n-type impurity, for example, arsenic is ion-implanted, and this impurity is activated by heat treatment to form a source / drain, an intermediate insulating film is deposited and an Al wiring is formed to form a memory cell.

(2) Second Manufacturing Example FIG. 5 shows a second example.

First, as shown in FIG. 5A, the silicon substrate 1
A pad oxide film 10 and a nitride film 11 are formed thereon, and the nitride film 11 is patterned and then ion-implanted to form P
A type impurity, for example, boron is ion-implanted to form a P ⁻ layer on the silicon substrate 1.

Next, as shown in FIG. 5B, a nitride film is deposited again, and the sidewall nitride film 13 is formed by anisotropic etching.

Next, as shown in FIG. 5C, when the field oxide film 9 is formed by thermal oxidation, for example, wet oxidation,
A channel region 12 having a high threshold voltage is formed.

Next, as shown in FIG. 5D, after removing the nitride film 11 and the pad oxide film 10, a tunnel oxide film 4 having a film thickness of, for example, about 15 nm is formed by thermal oxidation. After depositing the first-layer polysilicon 5 thereon, an n-type impurity such as phosphorus is introduced into the polysilicon layer 5 and patterning is performed to form the floating gate 5. After that, the memory cell is formed through the same procedure as in the first manufacturing example.

(3) Third Manufacturing Example FIG. 6 shows a third example.

First, as shown in FIG. 6A, the silicon substrate 1
A field oxide film 9 is formed on the above by the same procedure as in the first manufacturing example.

Next, as shown in FIG. 6B, after removing the nitride film 11 and the pad oxide film 10, a mask oxide film having a film thickness of, for example, about 20 nm is formed by thermal oxidation. Subsequently, P-type impurities such as boron are ion-implanted to form a P ⁻ layer on the silicon substrate 1.

Next, as shown in FIG. 6C, a part of the channel region is patterned and etched deeper than the P ⁻ layer, so that the channel region 12 having a higher threshold voltage can be formed. Further, after removing the mask oxide film 14, a tunnel oxide film of, for example, 15 nm is formed by thermal oxidation. After that, as shown in FIG. 6D, the memory cell is formed through the same procedure as in the second manufacturing example.

(4) Fourth Manufacturing Example FIG. 7 shows a fourth example.

First, as shown in FIG. 7A, the silicon substrate 1
N-type impurity such as boron is ion-implanted into or, P ^-
The layer is epitaxially grown to form a P ^- layer.

Next, as shown in FIG. 7B, the field oxide film 9 is formed through the same procedure as in the first manufacturing example.

Next, as shown in FIG. 7C, after the nitride film 11 and the pad oxide film 10 are removed, a part of the channel region is patterned and etched deeper than the P ⁻ layer.
The channel region 12 higher than the threshold voltage can be formed. Further, a 15 nm tunnel oxide film is formed by thermal oxidation. Thereafter, as shown in FIG. 7D, the memory cell is formed through the same procedure as in the second manufacturing example.

(5) Fifth Embodiment (corresponding to the device of the above-mentioned second embodiment) FIG. 8 shows a fifth embodiment. The field oxide film 9 is formed through the same procedure as in the first manufacturing example.

Next, as shown in FIG. 8B, after removing the nitride film 11 and the pad oxide film 10, the field oxide film 9 is partially etched to generate positive charges in the tunnel oxide film.

Next, as shown in FIG. 8C, when the tunnel oxide film 4 of 15 nm, for example, is formed by thermal oxidation, positive charges are generated in the region where the field oxide film 9 is removed, and the channel region below the positive charge is generated. The threshold voltage drops. Subsequently, P-type impurities such as boron are ion-implanted to form a P ⁻ layer on the silicon substrate 1 and the threshold voltage is controlled to a predetermined value. After that, as shown in FIG. 8D, the memory cell is formed through the same procedure as in the second manufacturing example.

[0049]

As described above in detail, according to the present invention, one transistor has two different threshold voltages.
Since it has three or more channel regions, reading can be easily performed even if the transistor characteristics are deteriorated by hot carriers during writing. Further, it is not necessary to use any new manufacturing technique for manufacturing the above transistor, and the manufacturing process is easy.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a first embodiment of the present invention.

FIG. 2 is a structural explanatory view of a second embodiment of the present invention.

FIG. 3 is a structural explanatory view of a conventional example.

FIG. 4 is a manufacturing process of the first embodiment of the present invention.

FIG. 5 is a manufacturing process of the second embodiment of the present invention.

FIG. 6 is a manufacturing process of a third embodiment of the present invention.

FIG. 7 is a manufacturing process of a fourth embodiment of the present invention.

FIG. 8 is a manufacturing process of a fifth embodiment of the present invention.

[Explanation of symbols]

4 tunnel oxide film 5 floating gate 6 control gate 12 high V _T channel region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location G11C 16/04

Claims (5)

[Claims] 1. A semiconductor memory device having a non-volatile memory cell having a MOS type structure, and having two or more channel regions having different threshold voltages between a source and a drain of the memory cell. A semiconductor memory device characterized by. 2. The two or more channel regions having different thresholds are provided with two or more regions having different impurity concentrations between the source and the drain. The semiconductor storage device described. 3. The semiconductor memory device according to claim 1, wherein as the two or more channel regions having different threshold values, positive charges are made to exist in an insulating film above the channel regions. .. 4. A method for operating a semiconductor memory device according to claim 1, wherein writing is performed in a channel region having a high threshold voltage and reading is performed in a channel region having a low threshold voltage. A method of operating an N-channel type semiconductor memory device, which is characterized by being performed. 5. The method for operating the semiconductor memory device according to claim 1, wherein writing is performed in a channel region having a low threshold voltage, and reading is performed in a channel region having a high threshold voltage. A method of operating a characteristic P-channel semiconductor memory device.