JPS6024072A - Field-effect type transistor - Google Patents

Abstract

PURPOSE:To obtain a GaAs FET, which has large mutual conductance and characteristics thereof do not deteriorate even at a temperature of approximately 500 deg.C, by directly forming a source electrode, a drain electrode and a gate electrode on a GaAs active layer and constituting the gate electrode by an Ir thin- film. CONSTITUTION:A GaAs active layer 2 containing S as an impurity is grown on a semi-insulating GaAs substrate 1 in the vapor phse, and formed to a desired shape through mesa etching by using an etchant mainly comprising NaOH. A source electrode 3 and a drain electrode 4 are each applied in an ohmic manner extending over the surface of the substrate 1 from the upper section of the layer 2 while being mutually opposed by using an Au alloy containing 12wt% Ge, and a gate electrode film 5 consisting of Ir-Ti-Al extending on the surface of the substrate 1 from the upper section of the layer 2 while being positioned in a clearance between these mutually opposite electrodes 3 and 4 is formed. Accordingly, the quality of a Schottky junction in the gate electrode film 5 is improved, and large mutual conductance is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a gallium arsenide (GaAS) field effect transistor (hereinafter referred to as an electric field This relates to effect type transistors (all called MEs/FETs).

Conventional configurations and their problems In recent years, gallium arsenide (GaAs) M7C3-FIT has come to be regarded as a key element in communication in high frequency bands of several Gllz or higher, and in the industry, there is a lot of effort in the development and development of elements. Manufacturing is active.

Here, MES and FET will be explained.

The figure shows a perspective view showing the configuration of the MKS-FET.

1 is an insulating or semi-insulating substrate, 2 is an active layer made of a Fi gallium arsenide (GaAS) semiconductor, 3 and 4 are a source and a drain, and 5 is a gate. The meaning of semi-insulating is the volume resistivity. is q1 o'Ω・(1 m or more. The operating principle of the MES-FET is that the spread of the depletion layer inside the semiconductor 2 due to the contact between the gate metal 6 and the active layer semiconductor 2 is This is due to the fact that it can be controlled by the potential of

This semiconductor is gallium arsenide (GaAs).

In the MKS-F''ET as shown in the figure, the gate 6 is conventionally made of aluminum (Al, titanium ('['i
), rim (Or), platinum (pt), p-ungsten (
W) has been used.

In these conventional MES-FETs, also.

Insufficient mutual conductance (crm). Currently, the gate length (L in Figure 1) is 1 μm, and the gate width (W) is a normal structure that does not have a recess near the gate.
) 160-200m per 1mm (millimetre)
It would be around 5 (milliSiemens).

When the gate is 6'j5Aβ, at around 400° C., kl diffuses into the semiconductor 2, and each atom of the semiconductor 2 diffuses into this Al, significantly deteriorating the characteristics of the MES-FET.

If the gate is 6iTi, it will be oxidized at around 460° C. due to moisture in the air.

When the gate 5 is made entirely of Cr, Cr becomes the semiconductor 2 at 400°C.
Among the atoms constituting the semiconductor 2, gallium (Ga), indium (In), aluminum (A#), etc. diffuse into the Cr of the gate.

When the gate 6 is made of PT, it reacts with the surface layer of the semiconductor 20 at 260 to 300°C to form a new compound.

According to the experience of field safety experts with a gate of 5'kW (tungsten), at 400°C, gate 6 is made of semiconductor 2.
Peel from.

As mentioned above, there is no gate material whose properties remain unchanged even when the MES-FET experiences temperatures of 600°C.

As described above, two unsatisfactory points remain in the conventional MKS and FET: qm is still unsatisfactory, and characteristics etc. change at high temperatures, which is assumed to affect reliability.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a UWS-trET2 which has a larger gm than conventional devices and whose overall characteristics do not deteriorate even when exposed to temperatures of approximately 500°C.

Structure of the Invention Ml of the present invention! :5-FIT includes an active layer made of gallium arsenide, a source electrode provided on the active layer, a drain electrode provided on the active layer, and at least iridium (Ir) provided on the active layer. ) A MES-FET consisting of a gate electrode having a thin film. The present invention also includes a case where the gate electrode further has a metal thin film laminated on the iridium (Ir) thin film, that is, has a groove structure of a multilayer film. As a result, the ME
The S-FET has a larger qIII'e than the conventional one, and even after experiencing a temperature of about 6 oO ℃, it is completely different from the MES-FET.
The characteristics do not deteriorate.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to all the drawings.

On semi-insulating gallium arsenide (GaAs) 1, a concentration of about 2
Ga containing sulfur (S) impurity of X 1 o”/crl
All substrates on which As active layers (about 20 μm thick) were formed by vapor phase growth were prepared.

In addition, caustic soda (Nail) is applied to the substrate.
Etch the mesa as shown in the figure. In the same figure, Ga A
The thickness A of the active layer is about 200 degrees.

Next, source and drain ohmic electrodes were formed as shown below. Gold (Au)-germanium (Ge) alloy (
Ge contains 12w10) about 13ω people, nickel (
Approximately 300 Ni) and 3000 gold (Au)
Electrode beam deposition was performed sequentially, and the entire electrode pattern was formed using the lift-off method, and then in an argon (Ar) stream.
Heat treatment was performed at 450'C for 3 minutes.

Next, the gate 5 is formed. The electrode pattern was formed by the lift-off method. Immediately before forming the Ge I/metal film O, the active layer is lightly etched with a tartaric acid-based etchant. The metal materials used in this example were aluminum (Al), titanium (T1), chromium (Or), and platinum (
pt), tungsten (W), gold (Au) and iridium (Ir). In the case of iridium (Ir), multiple sheets of foil are welded to a flat plate to form a gate film for these metals. In the case of tungsten (W), the same method is used. D.C.
・By magnetron sputtering method, other methods are lX1
It was formed by electron beam evaporation in a vacuum under O-6 Torr Id. In the figure, the gate length was 1 μm and the channel width W was 260 μm.

Measurements of MES, FET transconductance (cim) were performed using a curve tracer.

The mutual conductance (qm) is a measured value when the drain voltage is 3V and the drain current is around 2smA. qm is expressed in millimeters (ms).

The results of the examples are shown in Table 1.

In the gate configuration shown in Table 1 below, in the case of a metal multilayer film, G
Metal layers are sequentially formed on the aAs active layer starting from the leftmost metal layer. The values in parentheses are approximately 5 film thickness values obtained from the film thickness monitor at this time.

Each loft uses multiple GaAS substrates, and
There are several hundred measurement ME S-F ET on each board. The qm values in Table 1 are average values over these measured MES/FETs.

In the case of an experiment in which a temperature stress of 600°C was applied to all MR8-FETs in order to understand the influence of temperature, MES-
The FET manufacturing procedure has been changed from the previous one. That is, first the gate is formed, and then the 600
A temperature stress of 10 minutes at °C was applied in a total argon (Ar) atmosphere, and further, ohmic electrodes for the source and drain were formed, and M E S -F E '11'? Obtained. The results are shown in the column "Results after 60oC experience".

Tables 1 to 6 are comparative examples using the conventional method. When using a multilayer film of gate metal '1A7J or Ti-kl, the temperature is 600℃.
The whole temperature you experience. Increased gate leakage. In severe cases, the MES and FET characteristics will no longer be exhibited.

Next, the gate metal is made of Cr-Pt-Au or W-Ti.
- When a temperature stress of 500° C. is applied to a multilayer film of 500° C., the drain current becomes extremely small, and a drain current of 25 mA cannot flow, making measurement impossible.

An example with an iridium (Ir) gate according to the present invention is shown in No. 6. qm is also higher than the conventional one. In addition, heat treatment at 500'C tends to further improve qm.

Next, in accordance with the present invention, as a multilayer film containing an iridium (Ir) thin film, ■r-Pt-Au or Ir-T
The results for i-Al are shown in numbers 6-8. qmII'i is higher than the comparative example using the conventional method,
In addition, even under temperature stress of 600° C., qm slightly improves (when the gate is Ir-Pt-Au) or slightly decreases (when the gate is Ir=Ti, AI). In any case, it is much better than the comparative example.

The above improvement in qm at a temperature adjustment of 600″C is due to
) We estimate that the surface has reacted slightly and the quality of the Schottky junction directly under the gate has improved slightly. The decrease in gm upon application of a temperature stress of 500°C is due to the fact that the multilayer film I
It is estimated that this is due to the oxidation of aluminum (Aβ) in r-Ti-Aβ.

Effects of the Invention As is clear from the above explanation, the present invention comprises a multilayer film including an iridium (IrH) film or an iridium (Ir) film, and furthermore, the iridium (Ir)P
The iJ film is in contact with the surface of a gallium arsenide (GaAs) semiconductor.
)'a = has, and is more resistant to stress than conventional ones.
Female MES, Fl! :T is obtained.

[Brief explanation of drawings]

The figure is a perspective view of a field effect transistor according to an embodiment of the present invention. 1...Insulating or semi-insulating substrate, 2... River/semiconductor active layer, 3.4... Source or drain, 6... Gate.

Claims (2)

[Claims] (1) An active layer made of gallium arsenide, a source electrode provided on the active layer, a drain electrode provided on the active layer, and a gate electrode provided on the active layer and having at least an iridium thin film. A field effect transistor consisting of. (2) The field effect transistor according to claim 1, wherein the gate electrode is a multilayer film containing an iridium thin film.