JPS6024052A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6024052A JPS6024052A JP13107083A JP13107083A JPS6024052A JP S6024052 A JPS6024052 A JP S6024052A JP 13107083 A JP13107083 A JP 13107083A JP 13107083 A JP13107083 A JP 13107083A JP S6024052 A JPS6024052 A JP S6024052A
- Authority
- JP
- Japan
- Prior art keywords
- region
- regions
- type
- emitter
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の技術分野]
本発明は例えばモータ制御に用いられる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device used for example in motor control.
し発明の技術的背景とその問題点コ
一般に、電力用の半導体装置、例えば電力用トランジス
タをモータ制御に用いる場合は、第1図に示すように回
路構成されている。すなわち、モータ駆動用トランジス
タQl 、Q2が電源■と接地点間ニ直列接続され、こ
のトランジスタQl、Q2のコレクタ・エミッタ間には
それぞれダイオードDI。Technical Background of the Invention and Problems Therein Generally, when a power semiconductor device, such as a power transistor, is used for motor control, the circuit is configured as shown in FIG. That is, motor driving transistors Ql and Q2 are connected in series between a power supply and a ground point, and diodes DI are connected between the collectors and emitters of these transistors Ql and Q2, respectively.
D2が接続される。そして、上記トランジスタQ1゜Q
2をそれぞれ制御信号81.82で導通制御し、トラン
ジスタQl、Q2の接続点の電位でモータMを駆動制御
する。このような回路構成は、通常第2図に示すような
トランジスタQとダイオードDとを対にした半導体装置
を2個直列に接続して形成される。そしてこの半導体装
置は従来第3図に示すようにハイブリッドに構成されて
いた。D2 is connected. And the above transistor Q1゜Q
2 are controlled to be conductive by control signals 81 and 82, respectively, and the motor M is driven and controlled by the potential at the connection point of the transistors Ql and Q2. Such a circuit configuration is usually formed by connecting two semiconductor devices in series, each pairing a transistor Q and a diode D as shown in FIG. Conventionally, this semiconductor device has been configured in a hybrid manner as shown in FIG.
まず電力用トランジスタQのチップとダイオードDのチ
ップとをそれぞれ別の工程で形成した後、金属板10を
設置してトランジスタQのコレクタ領域QCとダイオー
ドDのカソードDkとを接続するとともに、エミッタQ
eとアノードDaとをアルミニウム等の金属線でボンデ
ィングして配線する。First, after forming the power transistor Q chip and the diode D chip in separate processes, a metal plate 10 is installed to connect the collector region QC of the transistor Q and the cathode Dk of the diode D, and also connect the emitter Q
e and the anode Da are wired by bonding with a metal wire such as aluminum.
ここでQbはトランジスタQのベース領域である。Here, Qb is the base region of transistor Q.
しかし、上記のような構成では、組立て時の部品点数が
多いため組立て工程が煩緒となシ、製品歩留シが向上で
きず組立て工程において発生する不良が数10チ程度忙
もなる。このため低コスト化が困難である。またトラン
ジスタQのエミッタQe上に金属線をボンディングしな
ければならないためエミツトQeの形状が制限されてし
まう。これはモータ制御等に用られる電力用トランジス
タでは一般KO15jIIl程度の直径の金属線がボン
ディングワイヤとして使用されるためであシ、ポンディ
ングパッドとして少なくとも1關×2顛尊の領域が必要
となり、同時にエミッタQeも1uX2關勺以上の領域
を備えていなければならない。However, with the above configuration, the number of parts during assembly is large, making the assembly process cumbersome, the product yield cannot be improved, and the number of defects occurring during the assembly process is approximately several dozen. Therefore, it is difficult to reduce costs. Furthermore, since a metal line must be bonded onto the emitter Qe of the transistor Q, the shape of the emitter Qe is restricted. This is because a metal wire with a diameter of about KO15jIIl is generally used as a bonding wire in power transistors used for motor control, etc., and an area of at least 1 x 2 x 2 is required as a bonding pad. The emitter Qe must also have an area of 1u×2 or more.
さらにエミッタ領域のワイヤ直下に電流集中が起とシ所
定の特性が得られない、又トランジスタQが破壊されて
しまう等の問題があった。Furthermore, current concentration occurs directly under the wire in the emitter region, resulting in problems such as failure to obtain desired characteristics and destruction of the transistor Q.
[発明の目的]
本発明は上記の事情を考慮してなされたもので比較的簡
単な工程で製造が可能であり、かつ所望ノ形状のエミッ
タ領域を得ることができ、さらにはエミッタの一部に電
流集中が起こることがない半導体装置を提供することを
目的とする。[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and can be manufactured through a relatively simple process, and can obtain an emitter region of a desired shape, and furthermore, can form a part of the emitter. An object of the present invention is to provide a semiconductor device in which current concentration does not occur.
[発明の概要コ
一導電型の第1の領域中に反対導電型の第2及び第3の
領域を形成し、第2の領域中に一導電型の第4の領域を
形成して、第1.第2−及び第4の領域よりトランジス
タを、また第1及び第3の領域よりダイオードを構成す
る。第3の領域と第4の領域とを接続し、第3及び第4
の領域の共通電極を第3の領域上から取シ出す。[Summary of the Invention] Second and third regions of opposite conductivity type are formed in a first region of one conductivity type, a fourth region of one conductivity type is formed in the second region, and a fourth region of one conductivity type is formed in the second region. 1. The second and fourth regions constitute a transistor, and the first and third regions constitute a diode. connecting the third area and the fourth area;
The common electrode in the area is taken out from above the third area.
[発明の実施例コ 本発明の一実施例を第4図を用いて説明する。[Embodiments of the invention] An embodiment of the present invention will be described using FIG. 4.
N型の半導体基板21KP型領域n、23を形成し、さ
らにP型領域ρ中にN型領域列を形成する。半導体基板
21.P型領域η、N型領域列がそれぞれNPN型トラ
ンジスタのコレクタ、ベース、エミッタに、また半導体
基板21、P型領域nがそれぞれダイオードのカソード
、アノードとなる。P型領域田とN型領域列をアルミ等
の金属IXかによ多接続し、P型領域お上にアルミ金属
線釘をボンディングしてP型領域る及びN型領域列の共
通電極を取り出す。またP型領域n上の表面にアルミ金
属線路をボンディングする。なお5は酸化膜である。KP type regions n and 23 are formed in an N type semiconductor substrate 21, and an N type region array is further formed in the P type region ρ. Semiconductor substrate 21. The P-type region η and the N-type region array serve as the collector, base, and emitter of the NPN transistor, respectively, and the semiconductor substrate 21 and the P-type region n serve as the cathode and anode of the diode, respectively. Connect the P-type area and the N-type area column with a metal IX such as aluminum, bond an aluminum metal wire nail onto the P-type area, and take out the common electrode of the P-type area and the N-type area column. . Further, an aluminum metal line is bonded to the surface of the P-type region n. Note that 5 is an oxide film.
このようにモノリシックに構成することによシトランジ
スタとダイオードを同時に形成スルコトができ、ボンデ
ィング回数も減るため製造が容易となる。またP型領域
お上から電極を取り出しているため、エミッタの一部に
電流集中が生じることがなくエミッタ全域にほぼ均一な
電流が流れる。This monolithic structure allows the transistor and the diode to be formed at the same time, and the number of bonding operations is reduced, which facilitates manufacturing. Further, since the electrode is taken out from above the P-type region, current concentration does not occur in a part of the emitter, and a substantially uniform current flows throughout the emitter.
さらにN型領域列はボンディングではなく金属膜かによ
シP型領域るに接続されるためポンディングパッドが不
要となりN型領域列は自由な形状を取ることができる。Furthermore, since the N-type region array is connected to the P-type region through a metal film rather than bonding, a bonding pad is not required, and the N-type region array can take any shape.
例えばこのトランジスタを高周波領域で使用したい場合
にはエミッタ、すなわちN型領域列の周囲長を長くする
キラな形状とすることができ、またエミッタを分割して
複数のN型領域列をP型領域n中に形成することもでき
る。For example, if you want to use this transistor in a high frequency region, you can make it have a unique shape that increases the perimeter of the emitter, that is, the N-type region array, or divide the emitter and use multiple N-type region arrays as the P-type region. It can also be formed in n.
なおエミッタの一部に電流集中が起こらないようにする
ためには、アルミ金属線nのボンディング位置を半導体
基板21のP型領域nとおとによりはさまれた部分の上
方の金属膜あ上とする方法も考えられる。しかし、この
位置では金属[26の膜厚が他部よシも薄いため、金属
膜のマイグレーシ茸ンもしくは水分によるコロージ冒ン
等が生じ易く、さらにボンディング位置からP型領域る
とを結ぶ部分の金属膜%が配線抵抗となるため、ダイオ
ードの順方向電圧が高くなってしまうという欠点があり
、実用的ではない。−
[発明の効果コ
本発明によれば比較的簡単な工程で、所望の形状の工き
ツタ領域を備えかつ工ぐツタ領域の一部に電流集中が起
こることがない半導体装置を得ることができる。In order to prevent current concentration from occurring in a part of the emitter, the bonding position of the aluminum metal line n must be placed above the metal film above the part sandwiched between the P-type region n and the bottom of the semiconductor substrate 21. Another possible method is to do so. However, since the film thickness of the metal [26] is thinner than other parts at this position, migration of the metal film or corrosion due to moisture is likely to occur. Since the metal film % becomes wiring resistance, the forward voltage of the diode becomes high, which is not practical. - [Effects of the Invention] According to the present invention, it is possible to obtain a semiconductor device having a carved ivy region of a desired shape and in which current concentration does not occur in a part of the carved ivy region, through a relatively simple process. can.
第1図はモータ制御回路を示す回路図、第2図は電力用
半導体装置の回路図、第3図は従来の電力用半導体装置
を示す断面図、第4図は本発明の一実施例を示す断面図
である。
21・・・半導体基板、
n、23・・・P型頭域、
U・・・N型領域、
拠・・・金属膜、
n、28・・・金属線。
第 1 図
第2図
第 3 図
第4図Fig. 1 is a circuit diagram showing a motor control circuit, Fig. 2 is a circuit diagram of a power semiconductor device, Fig. 3 is a sectional view showing a conventional power semiconductor device, and Fig. 4 is a circuit diagram showing an embodiment of the present invention. FIG. 21...Semiconductor substrate, n, 23...P-type head region, U...N-type region, base...metal film, n, 28...metal line. Figure 1 Figure 2 Figure 3 Figure 4
Claims (2)
成された反対導電型の第2及び第3の領域と、この第2
の領域中に形成された一導電型の第4の領域と、前記第
3及び第4の領域を接続する手段とを具備し、前記第1
.第2及び第4の領域よシトランジスタを構成し、前記
第1及び第3の領域よシダイオードを構成する半導体装
置において、前記第3及び第4の領域の共通電極が前記
第3の領域上から取り出されていることを特徴とする半
導体装置。(1) - A first region of conductivity type, second and third regions of opposite conductivity type formed in this first region, and this second region.
a fourth region of one conductivity type formed in the region; and means for connecting the third and fourth regions;
.. In the semiconductor device in which the second and fourth regions constitute a transistor and the first and third regions constitute a diode, a common electrode of the third and fourth regions is arranged on the third region. A semiconductor device characterized in that it is taken out from.
る特許請求の範囲第1項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the connecting means is a metal film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13107083A JPS6024052A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13107083A JPS6024052A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6024052A true JPS6024052A (en) | 1985-02-06 |
Family
ID=15049291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13107083A Pending JPS6024052A (en) | 1983-07-20 | 1983-07-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6024052A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521463A (en) * | 1992-08-21 | 1996-05-28 | Sony Corporation | Cathode ray tube having a cancel coil for earth magnetism |
-
1983
- 1983-07-20 JP JP13107083A patent/JPS6024052A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5521463A (en) * | 1992-08-21 | 1996-05-28 | Sony Corporation | Cathode ray tube having a cancel coil for earth magnetism |
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