JPS60237550A - Measuring device for cpu load factor - Google Patents
Measuring device for cpu load factorInfo
- Publication number
- JPS60237550A JPS60237550A JP59094359A JP9435984A JPS60237550A JP S60237550 A JPS60237550 A JP S60237550A JP 59094359 A JP59094359 A JP 59094359A JP 9435984 A JP9435984 A JP 9435984A JP S60237550 A JPS60237550 A JP S60237550A
- Authority
- JP
- Japan
- Prior art keywords
- load factor
- program
- cpu load
- cpu
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）技術分野
この発明は、ＣＰＵが処理するアプリケーションプログ
ラムのＣＰＵ負荷率を測定するＣＰＵ負荷率測定装置に
関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to a CPU load factor measuring device that measures the CPU load factor of an application program processed by a CPU.
（ｂ）発明の背景
マイクロプロセッサ等を処理装置に装備して実時間制御
を行う場合、マイクロプロセッサに処理させるプログラ
ムの難易でその応答速度が異なってくる。そのためＣＰ
Ｕの負荷率の測定は重要である。しかし、マイクロプロ
セッサ程度の規模のＣＰＵに対して価格的、精度的に最
適な負荷率測定装置は従来存在しなかった。(b) Background of the Invention When real-time control is performed by equipping a processing device with a microprocessor, the response speed varies depending on the difficulty of the program that the microprocessor is processed. Therefore, CP
Measuring the loading factor of U is important. However, there has not been a load factor measuring device that is optimal in terms of cost and accuracy for a CPU as large as a microprocessor.
（Ｃ１発明の目的
この発明は上記現状とその必要性に鑑み、ｃＰＵ自身が
持つタイマ機能と処理能力を利用して、簡便に負荷率を
計測できるｃｐｕ負荷率測定装置を提供することを目的
とする。(C1 Purpose of the Invention In view of the above-mentioned current situation and necessity, the purpose of the present invention is to provide a CPU load factor measuring device that can easily measure the load factor by using the timer function and processing power of the CPU itself. do.
（ｄ）発明の構成
この発明は、一定時間内に命令待ちプログラムをまわる
回数を計測する計測手段と、前記一定時間内に命令が入
力されることなく前記命令待ちプログラムをまわる回数
を基準値とし稼働中の前記計測手段の計測値と前記基準
値とでＣＰＵ負荷率を計算する演算手段と、計算された
ＣＰＵ負荷率を表示する表示装置を有することを特徴と
する特（ｅ）実施例
第２図はこの発明の実施例であるＣＰＵ負荷率測定装置
を装備した処理装置の構成を示すプロ・ツク図である。(d) Structure of the Invention The present invention includes a measuring means for measuring the number of times the command waiting program is cycled within a certain period of time, and a reference value that is the number of times the command waiting program is cycled without an instruction being input within the certain period of time. Particular (e) Embodiment 1, characterized in that it has an arithmetic means for calculating a CPU load factor using the measured value of the measuring means during operation and the reference value, and a display device for displaying the calculated CPU load factor. FIG. 2 is a block diagram showing the configuration of a processing device equipped with a CPU load factor measuring device according to an embodiment of the present invention.
入出力装置３は、処理装置からデータを得るセンサや制
御信号を出力する制御部等で構成されている。ＣＰＵＩ
は前記入出力装置３から受け取る情報によって所定のア
プリケーションプログラムを処理しその結果を再び入出
力袋Ｗ３に供給する。前記ＣＰ ｔＪ １にはメモリ２
とＣＲＴディスプレイである表示装置４が接続されてい
る第１図は上記実施例のＣＰＵＩの処理手順を示すフロ
ーチャートを示す。同図において、ステップｎｌ（以下
ステップｎ＋を単にｎｉと呼ぶ）。The input/output device 3 includes a sensor that obtains data from the processing device, a control section that outputs a control signal, and the like. C.P.U.I.
processes a predetermined application program based on the information received from the input/output device 3 and supplies the result to the input/output bag W3 again. The CP tJ 1 has a memory 2
FIG. 1 shows a flowchart showing the processing procedure of the CPUI of the above embodiment. In the figure, step nl (hereinafter step n+ will be simply referred to as ni).
ｎ２．ｎ３はそれぞれｎｉｌ、ｎｌ２．ｎ１３の応用プ
ログラムを実行する命令の入力有無を判断し入力があれ
ば所定のアブリケーショ・ンプログラムを実行する。ｎ
４ではカウント値Ｃに１を加え、一定時間経過すれば処
理をｎ６に進め経過していなければ処理をｎｌに戻す（
ｎ５）。このｎ４がこの発明の計測手段に対応する。ｎ
６では、ＣＰＵ負荷負荷率針算する。ｎｌではその値を
表示装置４に表示する。またｎ８でカウント値ＣをＢに
設定する。ｎ８は、今回ｎ５→ｎ６と抜けたときのカウ
ント値を前回の値として設定するステップである。この
ｎ８を終えると再びｎ１以下を実行する。n2. n3 are nil, nl2. It is determined whether an instruction to execute the application program n13 is input or not, and if there is an input, a predetermined application program is executed. n
4, add 1 to the count value C, and if a certain period of time has elapsed, proceed to n6, and if not, return to nl (
n5). This n4 corresponds to the measuring means of the present invention. n
In step 6, the CPU load load factor is calculated. At nl, the value is displayed on the display device 4. Further, the count value C is set to B at n8. n8 is a step in which the count value when the current count goes from n5 to n6 is set as the previous value. When this n8 is finished, n1 and subsequent steps are executed again.
ここで前記命令の入力がなく前記一定時間ｎ１〜ｎ５を
まわりつづけて、ｎ５−＝ｎ５と進んだときの一定時間
内におけるｎ４を処理する回数を基準値Ａとした場合、
命令の入力があってｎｉｌ〜ｎ１３が実行されている経
過において、ｎ５→ｎ６と抜けた時の負荷率ｌはβ−（
’Ａ−（Ｃ−Ｂ））／Ａで計算することができる。つま
り、命令が入力されることによって一定時間内にｎ１〜
ｎ５の処理をまわる回数が減れば、減少した処理回数骨
の時間だけ前記命令によって実行されたプログラムがＣ
ＰＵＩを占用したことになるわけである。ｎｌで前記負
荷率ｌを表示画面４に表示し、カウント値Ｃを前回値Ｂ
とした後処理をｎｌに戻ず。If the reference value A is the number of times n4 is processed within a certain period of time when the command is not input and the period of n1 to n5 continues for the certain period of time and progresses to n5-=n5,
In the process where an instruction is input and nil to n13 are executed, the load factor l when n5 → n6 is executed is β-(
It can be calculated as 'A-(C-B))/A. In other words, by inputting a command, n1~
If the number of times it goes through the process of n5 decreases, the program executed by the above instruction will change to C
This means that the PUI is occupied. nl displays the load factor l on the display screen 4, and sets the count value C to the previous value B.
Do not return the post-processing to nl.
第３図は上記実施例のメモリ２の要部構成図である。エ
リアＭ１にはｎ ｌ １． ｎ １２． ｎ １３で実
行される応用プログラムが記憶され、エリアＭ２にはｎ
１〜ｎ５で処理されるプログラムが記憶されている。ｎ
４で積算されるカウント値Ｃはアイドルカウントエリア
であるエリアＭ５に記憶されている。ｎ５．ｎｌ、ｎ１
３で処理される負荷率計算プログラムはエリアＭ３に記
憶され、前回値Ｂの値はエリアＭ４に記憶されている。FIG. 3 is a diagram showing the main part of the memory 2 of the above embodiment. Area M1 has n l 1. n 12. An application program executed in n13 is stored, and area M2 has n13 stored in it.
Programs to be processed in steps 1 to n5 are stored. n
The count value C accumulated in step 4 is stored in area M5, which is an idle count area. n5. nl, n1
The load factor calculation program processed in step 3 is stored in area M3, and the previous value B is stored in area M4.
上記の構成からなる負荷率測定装置を装備する処理装置
を稼働させた場合、ＣＰＵＩは目的とするアプリケーシ
ョンプログラムを実行しながら一定時間毎に表示装置４
にＣＰＵＩの負荷率を表示してゆく。When a processing device equipped with a load factor measuring device having the above-mentioned configuration is operated, the CPU 4 updates the display device 4 at regular intervals while executing the target application program.
The CPU load factor will be displayed.
（ｆ１発明の効果
以上のようにこの発明によると、ＣＰＵ自身が持つタイ
マ機能と、ＣＩ）Ｕ、がアプリケーションプログラムを
処理する場合に命令待ちプログラムとして一時的に実行
されるプログラムの処理時間を利用して簡便にｃｐｕ負
荷率を測定表示できるので、マイクロプロセッサ等を装
備する処理装置に最適のＣＰＵ負荷率測定装置を提供す
ることができる。(Effects of the f1 invention) As described above, according to this invention, the timer function of the CPU itself and the processing time of a program that is temporarily executed as an instruction waiting program when the CI) U processes an application program are utilized. Since the CPU load factor can be easily measured and displayed, it is possible to provide a CPU load factor measuring device that is most suitable for a processing device equipped with a microprocessor or the like.
第１図はこの発明の実施例であるＣＰＵ負荷率測定装置
を装備する処理装置の構成を示すブロック図である。第
２図は上記実施例のｃｐｕの処理手順を示すフローチャ
ートである。第３図は上記メモリの要部構成図である。
１−ＣＰＵ、２−メモリ、３−入出力装置、４−表示画
面、
Ｍ２−命令待ちプログラム記憶エリア、Ｍ３−負荷率計
算プログラム記憶エリア。
出願人 立石電機株式会社
代理人 弁理士 小森久夫
第１ ＩＴ
第２図
第３図FIG. 1 is a block diagram showing the configuration of a processing device equipped with a CPU load factor measuring device according to an embodiment of the present invention. FIG. 2 is a flowchart showing the processing procedure of the CPU in the above embodiment. FIG. 3 is a diagram showing the main part of the memory. 1-CPU, 2-memory, 3-input/output device, 4-display screen, M2-instruction waiting program storage area, M3-load factor calculation program storage area. Applicant Tateishi Electric Co., Ltd. Agent Patent Attorney Hisao Komori 1st IT Figure 2 Figure 3
Claims (1)
ションプログラムを実時間で処理するＣＰＵを備えた処
理装置において、 一定時間内に前記命令待ちプログラムをまわる回数を計
測する計測手段と、前記一定時間内に命令が入力される
ことなく前記命令待ちプログラムをまわる回数を基準値
とし稼働中の前記計測手段の計測値と前記基準値とでＣ
ＰＵ負荷率を計算する演算手段と、計算されたＣＰＵ負
荷率を表示する表示装置を有してなるＣＰＵ負荷率測定
装置。[Scope of Claims] (In a processing device including a program waiting for an instruction and a CPU that processes an application program in real time according to the instruction, a measuring means for measuring the number of times the program waiting for an instruction is executed within a certain period of time; The number of times the command-waiting program passes through the command waiting program within the certain period of time is set as a reference value, and the measurement value of the measuring means in operation and the reference value are calculated as C.
A CPU load factor measuring device comprising a calculation means for calculating a CPU load factor and a display device for displaying the calculated CPU load factor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59094359A JPS60237550A (en) | 1984-05-10 | 1984-05-10 | Measuring device for cpu load factor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59094359A JPS60237550A (en) | 1984-05-10 | 1984-05-10 | Measuring device for cpu load factor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60237550A true JPS60237550A (en) | 1985-11-26 |
Family
ID=14108099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59094359A Pending JPS60237550A (en) | 1984-05-10 | 1984-05-10 | Measuring device for cpu load factor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60237550A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0320329A2 (en) * | 1987-12-08 | 1989-06-14 | Northern Telecom Limited | Real time digital signal processor idle indicator |
| WO1999034292A1 (en) * | 1997-12-24 | 1999-07-08 | Robert Bosch Gmbh | Method for determining the load of a computing device |
-
1984
- 1984-05-10 JP JP59094359A patent/JPS60237550A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0320329A2 (en) * | 1987-12-08 | 1989-06-14 | Northern Telecom Limited | Real time digital signal processor idle indicator |
| EP0320329A3 (en) * | 1987-12-08 | 1990-12-05 | Northern Telecom Limited | Real time digital signal processor idle indicator |
| WO1999034292A1 (en) * | 1997-12-24 | 1999-07-08 | Robert Bosch Gmbh | Method for determining the load of a computing device |
| US6477484B1 (en) | 1997-12-24 | 2002-11-05 | Robert Bosch Gmbh | Method for determining the load of a computing device |
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