JPS60236339A - First-in priority circuit - Google Patents

Abstract

PURPOSE:To fetch automatically the first-in one of both signals by using the output of a first-in discriminating circuit which discriminates the first-in signal to open one of both gates connected to those two signals and closing the other gate. CONSTITUTION:A signal (a) sent from a line A is supplied to an FF31A and a first-in discriminating circuit 36; while a signal (b) given from a line B is supplied to an FF31B via the circuit 36. The circuit 36 transmits the signal (b) when the input of the signal (b) is faster than that of the signal (a) by an amount equal to a cycle of a clock pulse (g) and otherwise inhibits the transmission of the signal (b). The Q output signals of both FF31A and 31B are turned into reception signals (i) through an OR gate 33 and supplied to FF32A and 32B respectively. The FF31B and 31A are reset with Q outputs of FF32A and 32B respectively. Thus the first-in signal is transmitted but the other signal is inhibited. The signal (i) is supplied to a transmission control initial resetting circuit 34, and the circuit 34 outputs a transmission unable signal for a prescribed period of time after the input of the signal (i) is discontinued. Then the circuit 34 resets the FF32A and 32B when a prescribed period of time elapses.

Description

DETAILED DESCRIPTION OF THE INVENTION Background and Summary of the Invention The present invention relates to a first-come, first-served priority circuit that prioritizes whichever of two input signals arrives first.

The present invention provides a first-come, first-served priority circuit suitable for selectively receiving only one signal in a communication system in which the same signal is always transmitted through two pairs of communication lines, for example. be.

The first-come-first-served priority circuit according to the present invention includes a gate circuit connected to each of two input terminals, a first-come-first-served discrimination circuit for discriminating the signal that arrived first among the input signals of the two input terminals, and an input signal according to the first-come-first-served discrimination result. The present invention is characterized in that it is equipped with a gate control circuit that opens the gate circuit corresponding to the terminal that arrives first and closes the other gate circuit.

Such a first-come, first-served priority circuit can be applied, for example, to a communication control device equipped with two receiving terminals. Although the same signal is always received at the two receiving terminals, the arrival times of these received signals are often slightly different. In such a case, if the first-come-first-served priority circuit according to the present invention is used, the signals that arrive first are automatically taken in with priority, so a switching circuit that requires some kind of switching operation becomes unnecessary.

In order to adapt to the case where two received signals arrive at the same time, it is preferable that the first-arrival discrimination circuit gives priority to a predetermined one in the case of simultaneous arrival.

This invention is applicable not only to communication systems as described above, but also to l
[For example, it can also be applied to first-come, first-served priority for interrupt signals.

Hereinafter, an embodiment in which the present invention is applied to a communication control device in a communication system configured with two pairs of transmitting and receiving lines will be described in detail.

Description of Embodiment This embodiment relates to an optical communication system using an optical fiber as a communication line, and a full duplex communication method is adopted as the communication method.

In Fig. 1, a plurality of devices (10 lines) are connected in a loop by an optical communication line.
) has two pairs of transmitting and receiving terminals T.
%R is provided, and two pairs of transmitting/receiving lines A and B are connected to these.

Both of the transmission and reception lines A and B are composed of a transmission line and a reception line, and are respectively connected to other devices (10) adjacent to each other on the communication loop. Multiple devices (1
0) may be used as a central @ location (hereinafter referred to as a solid device for convenience). In this case, a polling/selecting method in which the solid device takes initiative may be adopted as the startup method. Of course, all @If(10) may have equal communication rights, or an appropriate priority may be assigned in advance to the communication rights of each I@(10).

In any case, the same message (data) is always transmitted on the transmission/reception lines A and 8.

In this way, the same message is sent using two pairs of transmission/reception lines A1B, so even if a failure occurs at any one point on the transmission/reception line, each device (10) or solid device will not be able to communicate with all other devices. It is possible to communicate with (10). Also, if any of the communication control devices (←11) fails, that device (10)
All other devices except the . Furthermore, the device (10
) Any device (10) or transmitting/receiving line can be repaired even when communication is taking place between each other or between a solid device and another device, and any device (10)
0) can be removed from the loop or new devices can be added to the loop.

Figure 2 shows an overview of the configuration of the communication control device M (11). Generally, there is a slight difference in the time when the received message and the message sent from line B arrive at the communication control device, so if the two messages are simply superimposed, the data in the message may change.This problem Communication control equipment to deal with!
(11) is provided with a first-come, first-served priority circuit (23).

The configuration of the first-come, first-served priority circuit (23) will be detailed later.

Transmission signals (telegrams) from the CPU, etc. of the device (10) are sent to electrical/optical ('E'10) conversion circuits (21A) (21B), and converted into optical signals by these circuits (21A) (21B). After that, they are simultaneously sent out to the transmission lines of lines A and B, respectively.

The optical signal input to the optical/electrical (0/E>m detection circuit (22A) on line A is converted into an electrical signal and
3) and is also sent to Line B's E10 conversion circuit (
21B) and is sent out as an optical signal to the transmission line of line B. Also, line B O/E conversion circuit (22
The optical signal received by B) is converted into an electrical signal and sent to the first-come-first-served priority circuit (23), and is also sent to the E10 conversion circuit (23).
21A>, it is converted into an optical signal and sent out to the transmission line. In this way, a signal received from line A is immediately sent to the transmission line of line B, and a signal received from line B is immediately sent to the transmission line of line A, thereby creating a double loop communication. achieved. The received optical signal is first converted into an electrical signal, then converted into an optical signal and sent out to the transmission line, so the
The /E, E10 transformer circuit plays the role of a kind of repeater, and even if the loop communication line as a whole is quite long, there is no need to consider the problem of optical signal attenuation due to the optical fiber.

Further, even if the first-come-first-served priority circuit (23) fails, the signal received by the 07E conversion circuit is sent to the E10 conversion circuit and sent out to the transmission line, so the communication loop will not be interrupted.

When the signal is received by the 0/E conversion circuit (22A) (22B) and input to the first-come-first-served priority circuit (23), this circuit (23
) determines which of the signals input from both circuits C22A) (22, 8) is earlier in time, and outputs the earlier signal as the received signal (+). The slower signal is prohibited from passing through this circuit (23). Further, the first-come-first-served priority circuit (23) outputs a transmission impossible signal (j) while receiving the signal. This transmission impossible signal (j) is sent to the CPLI of the device (10), and based on this, the C
The PU stops sending out transmission signals while the transmission prohibition signal (j) is input. The transmitted signal is sent to the E10 conversion circuit (21A>(21B>) as described above, so when there is a received signal, it is sent to the O/E conversion circuit (22A) (22B).
) to the circuit (21A) (21B>).As we will see later, the 0/
When signals are input to the E conversion circuits (22A) (22B) at the same time, priority is given to the signal on line (A).

FIG. 3 shows details of the first-come, first-served priority circuit (23), and FIG. 4 shows its operation. In FIG. 3, the output signal (a) of the 0/E conversion circuit (22A) to the line is input to the data input terminal (D) of the D flip-flop (gate circuit) (31A), and the first-come-first-served discrimination circuit (36 )
sent to.

Output signal (b) of O/E conversion circuit (22B) on line B
is input to the D flip 70 tube (gate circuit) (31B) as a signal (bl) via the first-arrival discrimination circuit (3G).

The output signals (non-inverted outputs) (c) (d) of these D-flip 70 tubes (31A>(31B)) pass through the OR circuit (33) and become the received signal (+).As will be described later, the output signal ( C) and (d) are never output at the same time.The first-come-first-served discrimination circuit (36) determines if the input of the signal (b) is earlier than the input of the signal <a> by one period or more of the clock pulse (0). The signal (b) is allowed to pass through, and the signal (b) is prohibited from passing in other cases.

D flip 70 tube (31A>(31B> is JK flip 70 tube (gate control circuit) (32B) (32A)
controlled by D flip 70 tube (31A>
(31B) (p output signal (c) (d) is the input terminal (J) of the JK flip-flop (32A) (32B)
Also enter each. JK flip flop O tube (32A
)'s inverted output (Q) is connected to the forced reset terminal (R) of the D flip-flop (31B>
The inverted output (Q) of 2B) is a D flip-flop (31A
) are sent to the forced reset terminal (R) of each.

These D flip 70 knobs (31A> (31B) are normally in a state where they can pass input signals (a) and (bl), respectively, in synchronization with the clock pulse (0) input to the clock input terminal (T). However, when the JK flip-flop (32A) is set by the input signal (l), its inverted output (Q) goes to the positive level, so the D flip-flop (31B) is forcibly reset and the input Passage of the signal (bl) is prohibited.On the other hand, when the JK flip 7U tube (32B) is set by the input signal (bl), its inverted output (Q) becomes L level and the D flip-flop (32A) becomes It is forcibly reset and the passage of the input signal <a> is prohibited.

The transmission control and initial reset circuit (34) has two functions. This circuit (34) has a received signal (+)
is being input, and the circuit (34) measures a certain period of time <1) after the reception signal (+) stops being input. Then, when a certain period of time (1) has elapsed without the received signal (i) being input again, the circuit (34) outputs an initial reset pulse (h) at a high level. This pulse (h) forces the JK flip-flops (32A) (32B) to be reset. Further, from the time when the received signal (+) is input until the above-mentioned fixed time fit(t) has elapsed, the L level transmission disable signal (j) is output from the open circuit (34). The system clock generation circuit (35) outputs a series of clock pulses l), which
Tsuku pulse (C+) is D flip 70 Tsubu (31A
) (31B) and JK flip flop 0 tube (32A) (
32B) is input to the clock input terminal (T).

In FIG. 4, the period of the clock threat pulse (0) is shown significantly enlarged. Also, signals (a) (b) (b
1), (c), (d), and (i) are actually repeatedly inverted depending on the data represented by these signals, but in FIG. 4, they are uniformly expressed as H and L. FIG. 4 (D) shows a case where the signal (a) to the line arrives earlier than the signal (b) to the line B.

The same (If) is the case where the signal (b) arrives earlier than the signal (a), and the same (III) is the case where both the signals (a) (b
) arrive at the same time.

One input terminal of the AND circuit (37) of the first-come-first-served discrimination circuit (36) receives the output signal (e) of the inverted output terminal (Q) of the JK flip 70 tube (32B), and the other input terminal receives the signal (a). ) is now entered. AND circuit (
37) is led to one input terminal of the NANDAND circuit), and the input terminal of this NANDAND circuit has an N
The line B signal (b) inverted by the OT circuit (38) is input. In the initial state, the JK flip-flop (32B) is initially reset, so the signal (e) is at H level. Therefore, the signal (a) (
When a high level) is input, the output of the AND circuit (37) is high.
become the level. This H level output is sent to one input terminal of the NANDAND circuit.
circuit) has its gate closed and the passage of signal (b) is prohibited. Therefore, signal (a) becomes signal (b
) or earlier than signal (b), signal (b) cannot pass through this first-arrival discrimination circuit (36) (see Figure 4 (I) (■), especially (1)) .

When the signal (a) is input to the D flip-flop (31A), from the rising edge of the low clock pulse (Q), this signal (a) passes through the D flip-flop 70 (31A) (signal (C) ) The received signal (+
), JK, flip-flop (32A
) input terminal (J). Clock pulse (
9), the JK flip-flop is set to 0 (32A>
is set, so its inverted output (Q) becomes L level. This L level signal is JK flip 70 tube (32
Since it is fed back to the input terminal (K) of A>, J
K flip-flop (32A) is kept set.

JK flip-flop O tube (32A> inverted output terminal (Q)
The L level signal (f) of the D flip 70 tube (31
Since the signal is input to the forced reset terminal (R) of signal B), the D flip 70 tube (31B) is forcibly reset by this L level signal (f). Therefore, the output (d) of the non-inverting output terminal (Q) of the D flip-flop (31B>
) is held at the edge level, and the JK flip-flop (32
B) is also held in a reset state, and the NAN[) circuit (39) also keeps its gate closed while the signal <8) is input. This signal <1> is held at L level until the JK flipflop 0 tube (32A>) is initialized by the initial reset circuit (34), so even if the signal (a) is stopped and the gate of the NANDAND circuit is opened. Even if the signal (b) passes through this circuit (39) (signal (bl)), the D flip 70 knob (31B) will not be set. The signal (f) is a line A priority signal that prohibits the line B signal (bl) from passing through the D flip-flop (31B) (Fig. 4 (I)).
(see III)).

Signal (b) is processed by the first-come-first-served discrimination circuit (
36), even if one input signal (e) of the AND circuit (37) is at H level, the other input signal (a) is at L level. The output is L level, and the signal (b) is N, AND circuit (
39). Since the signal (b) is inverted by the NOT circuit (38) and further inverted by the NAND circuit (39), the output signal (bl) of the NAND circuit (39) and the signal (
b) is isomorphic. The signal (bl) input to the data input terminal (D) of the D-flip 70 tube (31B) passes through this D-flip-flop (31B) from the rising edge of the clock pulse (0) and becomes signal (d). , further passes through the OR circuit (33) and becomes the received signal (+>.The signal (d) is also input to the input terminal (J) of the JK flip 7O tube (32B), so the riOtsuk pulse ((1) The JK flip-flop 70 (32B) is set by the falling edge of the JK flip-flop (32B).The output (e) of the inverting output terminal (Q) of this JK flip-flop (32B) becomes L level, and the D flip-flop
Input to forced reset terminal (R) of flip-flop (31A).

Therefore, after this, even if the signal (a 2 ) is input, the D flip-flop (31A) is held in the reset state, and the input signal (a 2 ) cannot pass through this D flip 70 tube <31A>. Signal (e) is the line B priority signal (
(See Figure 4 (II)).

The JK flip-flop (32B> is set and the signal (
When e) becomes L level, the output of the AND circuit (37) continues to be held at L level regardless of the presence or absence of the signal (a), so the gate of the NAND circuit (39) remains open and the input signal (b ) can pass through the NAND circuit (39).

Even if signal (b) arrives slightly earlier than signal (a), the clock pulse (0
) rises and does not fall, the NAND circuit (3
Since the gate of 9) is closed by the signal (a), the signal (a) to the line will have priority.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a communication system between multiple devices, Fig. 2 is a block diagram showing a communication control device, Fig. 3 is a block diagram showing a first-come-first-served priority circuit, and Fig. 4 shows the operation of the first-come-first-served priority circuit. FIG. (23)...First-come-first-served priority circuit, (31A) (31B)
...D flip-flop (gate circuit), (32A
') (32B)...JK flip-flop Otub (gate control circuit), (34)...Transmission control and initial reset circuit, (36)...First-come-first-served discrimination circuit. Figure 2 above

Claims (3)

[Claims] (1) A gate circuit connected to each of the two input terminals, a first-come-first-served discrimination circuit that discriminates which signal arrives first among the input signals of the two input terminals, and an input signal that arrives first according to the first-come-first-served discrimination result. A first-come, first-served priority circuit comprising: a gate control circuit that opens a gate circuit corresponding to a terminal that has been received and closes the other gate circuit; (2) The first-come-first-served priority circuit according to claim (1), wherein when signals are simultaneously input to two input terminals, the first-come-first-served discrimination circuit gives priority to a predetermined one. (3) The first-come-first-served priority circuit according to claim (1), further comprising a transmission control circuit that outputs a transmission prohibition signal while receiving either one of the input signals.