JPH0323028B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Background and Summary of the Invention The present invention relates to a first-come, first-served priority circuit that gives priority to whichever of two input signals arrives first.

The present invention provides a first-come, first-served priority circuit suitable for selectively receiving only one signal in a communication system in which the same signal is always transmitted through two pairs of communication lines, for example. be.

The first-come-first-served priority circuit according to the present invention includes first and second bistable circuits each connected to two input terminals and serving as a gate circuit, and a first-come-first-served discrimination circuit that determines which signal arrives first among the input signals of the two input terminals. circuit, third and fourth bistable circuits that act as gate control circuits for controlling the first and second bistable circuits and the first-come-first-served discrimination circuit, and a system clock generation circuit that outputs clock pulses of a constant period. , an OR circuit, and a transmission control and initial reset circuit.

The first bistable circuit passes the input signal from one input terminal in synchronization with the clock pulse, and the second bistable circuit passes the input signal from the other input terminal through the first-come-first-served discrimination circuit. The OR circuit outputs the input signal that has passed through either the first or second bistable circuit as a received signal.

The third bistable circuit changes from one stable state to the other stable state when an input signal is applied via the first bistable circuit, and its output changes the second bistable circuit. The fourth bistable circuit is in a disabled state, and the fourth bistable circuit is in a disabled state.
When an input signal is given through a bistable circuit, one stable state changes to the other stable state,
The output disables the first bistable circuit.

The first-come-first-served discrimination circuit includes a gate circuit controlled by the input signal of the one input terminal and the output signal of the fourth bistable circuit, and the gate circuit is controlled by the input signal of the one input terminal. The fourth terminal allows the input signal of the other input terminal to pass through, which has reached the other input terminal earlier, and thereby the other input terminal becomes in a stable state.
The output signal of the bistable circuit maintains the enabled state regardless of the presence or absence of the input signal of the one input terminal, and the input signal of the one input terminal arrives earlier or at the same time as the input signal of the other input terminal. It is disabled by an input signal and prohibits the input signal from the other input terminal from passing through.

The above-mentioned reception signal is given to the above-mentioned transmission control and initial reset circuit, and this circuit outputs a transmission-disabled signal from the time when the above-mentioned reception signal is input until a certain period of time has passed after the reception signal stops, and also outputs a reception-disabled signal. When a certain period of time has elapsed after the signal stopped, an initial reset signal is applied to the third and fourth bistable circuits to return these bistable circuits to one of the stable states.

Such a first-come, first-served priority circuit is applied, for example, to a communication control device that has two receiving terminals, receives the same signal at these receiving terminals, and generally has slightly different arrival times for the two received signals. . In such a case, if the first-come-first-served priority circuit according to the present invention is used, the first-arriving signal will be discriminated by the first-come-first-served discrimination circuit, and will be taken in via the corresponding first or second bistable circuit and OR circuit, and the signal that arrived later will be taken in through the corresponding first or second bistable circuit and OR circuit. The input of the input signal is prohibited by disabling the second or first bistable circuit by the output signal of the corresponding third or fourth bistable circuit. Even when two received signals arrive at the same time, one predetermined input signal is accepted preferentially and the input of the other is prohibited. Then, after a certain period of time has passed after the reception signal stops, the third and fourth bistable circuits are initialized by the transmission control and initial reset circuit, so they return to their original state and can accept the next input signal. becomes. Furthermore, while a receive signal is being input, a transmission disable signal is output from the transmission control and initial reset circuit, so the transmission of signals from the communication control device is prohibited, and the input and output signals are routed on the same line. This prevents a situation where both are mixed.

The present invention can be applied not only to communication systems as described above, but also to, for example, first-come, first-served interrupt signals.

Hereinafter, an embodiment in which the present invention is applied to a communication control device in a communication system configured with two pairs of transmitting and receiving lines will be described in detail.

Description of Embodiment This embodiment relates to an optical communication system using an optical fiber as a communication line.
A full-duplex communication method is used for the communication method.

In FIG. 1, a plurality of devices 10 are connected in a loop through optical communication lines. Furthermore, the communication control device 11 of each device 10 is provided with two pairs of transmitting and receiving terminals T and R, and two pairs of transmitting and receiving lines A and B are connected to these. Both of the transmission and reception lines A and B are composed of a transmission line and a reception line, and are respectively connected to other devices 10 adjacent to each other on the communication loop. Multiple devices 1
0 as the central device (hereinafter referred to as
For convenience, it may be referred to as a central device). In this case, a polling/selecting method in which the central device takes initiative may be adopted as the activation method. Of course, all devices 10 may have equal communication rights, or appropriate priorities may be assigned in advance to the communication rights of each device 10.

In any case, the same message (data) is always transmitted on the transmission/reception lines A and B. In this way, the same message is sent using the two pairs of transmission/reception lines A and B, so even if a failure occurs at any one point on the transmission/reception lines, each device 10 or the central device will not be able to communicate with all other devices 10. It is possible to communicate with Furthermore, even if any of the communication control devices 11 fails, all other devices except that device 10 can normally communicate with each other or with the central device. Furthermore, repair of any device 10 or transmitting/receiving line is possible even when communication is taking place between devices 10 or between a central device and other devices, and any device 10 can be repaired from the loop. Removal or new devices 10 can be added to the loop.

FIG. 2 shows an overview of the configuration of the communication control device 11. The same message is always transmitted on the two pairs of transmission/reception lines A and B, but the time when the message sent from line A and the message sent from line B arrive at the communication control device is generally different. Since there is a slight deviation, there is a risk that the data in the message will change if the two messages are simply superimposed. To deal with this problem, the communication control device 11 is provided with a first-come-first-served priority circuit 23. First come first priority circuit 2
The configuration of No. 3 will be explained in detail later.

Transmission signals (telegrams) from the CPU, etc. of the device 10 are sent to electrical/optical (E/O) conversion circuits 21A and 21B, and after being converted into optical signals by these circuits 21A and 21B, they are sent to lines A and B, respectively. are simultaneously sent out to the transmission line.

Line A optical/electrical (O/E) conversion circuit 22A
The optical signal input to the line B is converted into an electrical signal and sent to the first-come-first-served priority circuit 23.
Line B is sent to the O conversion circuit 21B as an optical signal.
is sent to the transmission line. Further, the optical signal received by the O/E conversion circuit 22B of line B is converted into an electrical signal and sent to the first-come-first-served priority circuit 23, and is also converted to an optical signal by the E/O conversion circuit 21A, which is transmitted to the transmission line of line A. sent to. In this way, a signal received from line A is immediately sent to the transmission line of line B, and a signal received from line B is immediately sent to the transmission line of line A, thereby creating a double loop communication. achieved. The received optical signal is first converted into an electrical signal, and then further converted into an optical signal and sent to the transmission line, so the O/E, E/O conversion circuit plays the role of a kind of relay device, and the loop communication line Even if the optical fiber is quite long as a whole, there is no need to consider the problem of optical signal attenuation due to the optical fiber. Further, even if the first-come-first-served priority circuit 23 breaks down, the signal received by the O/E conversion circuit is sent to the E/O conversion circuit and sent out to the transmission line, so the communication loop will not be interrupted.

When the signal is received by the O/E conversion circuits 22A and 22B and inputted to the first-come-first-served priority circuit 23, this circuit 23
determines which of the signals inputted from both circuits 22A and 22B is earlier in time, and outputs the earlier signal as the received signal i. The slower signal is prohibited from passing through this circuit 23. Further, the first-come-first-served priority circuit 23 outputs a transmission impossible signal j while receiving the signal. This transmission impossible signal j is sent to the CPU of the device 10, and based on this, the CPU
stops sending out the transmission signal while the transmission enable signal j is input. Since the transmission signal is sent to the E/O conversion circuits 21A and 21B as described above, when there is a reception signal, the O/E conversion circuits 22A and 22B
This is because the signal is superimposed on the received signal sent from the source to the circuits 21A and 21B. As you will see later,
When signals are input to the O/E conversion circuits 22A and 22B at the same time, the signal on line A is given priority.

FIG. 3 shows details of the first-come-first-served priority circuit 23, and FIG. 4 shows its operation. In FIG. 3, the output signal a of the O/E conversion circuit 22A on line A is input to the data input terminal D of a D flip-flop (gate circuit) 31A, and is also sent to the first-arrival discrimination circuit 36. The output signal b of the O/E conversion circuit 22B on line B passes through the first-arrival discrimination circuit 36 and is output as a signal b1 to a D flip-flop (gate circuit).
31B. Output signals (non-inverted output) of these D flip-flops 31A and 31B c, d
passes through the OR circuit 33 and becomes the received signal i. As will be described later, output signals c and d are never output at the same time. The first-arrival discrimination circuit 36 allows signal b to pass if the input of signal b is earlier than the input of signal a by one cycle or more of the clock pulse g, and otherwise prohibits the passage of signal b.

D flip-flops 31A and 31B are JK flip-flops (gate control circuit) 32B and 32A.
controlled by. D flip-flop 31
The output signals c and d of A and 31B are also input to input terminals J of JK flip-flops 32A and 32B, respectively. The inverted output Q of the JK flip-flop 32A is sent to the forced reset terminal R of the D flip-flop 31B, and the inverted output Q of the JK flip-flop 32B is sent to the forced reset terminal R of the D flip-flop 31A. These D flip-flops 31A and 31B are normally in a state in which they can pass input signals a and b1, respectively, in synchronization with the clock pulse g input to the clock input terminal T. However, depending on the input signal c
When JK flip-flop 32A is set,
Since the inverted output becomes L level, the D flip-flop 31B is forcibly reset and prohibits the passage of the input signal b1. Conversely, when the JK flip-flop 32B is set by the input signal b1, its inverted output goes to L level, the D flip-flop 32A is forcibly reset, and the passage of the input signal a is prohibited.

Transmission control and initial reset circuit 34 has two functions. This circuit 34 has a received signal i.
is input, and the circuit 34 measures a certain period of time t after the input of the received signal i stops. Then, when a certain period of time t has elapsed without the received signal i being input again, the circuit 34 outputs an initial reset pulse h at L level. By this pulse h
JK flip-flops 32A and 32B are forcibly reset. In addition, the circuit 3
4 outputs an L level transmission disable signal j. The system clock generator circuit 35 outputs a series of clock pulses g, which are applied to the D flip-flop 31.
A, 31B and JK flip-flop 32A,
It is input to the clock input terminal T of 32B.

In FIG. 4, the period of clock pulse g is shown considerably enlarged. Also, the signal a,
Although b, b1, c, d and i are actually repeatedly inverted depending on the data represented by these signals, they are uniformly expressed as H level in FIG. FIG. 4 shows the case where signal a on line A arrives earlier than signal b on line B. This figure shows the case where signal b arrives earlier than signal a, and the same figure shows the case where both signals a and b arrive at the same time.

The output signal e from the inverted output terminal of the JK flip-flop 32B is input to one input terminal of the AND circuit 37 of the first arrival discrimination circuit 36, and the signal a is input to the other input terminal. AND circuit 3
The output of 7 is led to one input terminal of the NAND circuit 39, and the other input terminal of this NAND circuit is
The signal b of line B, which has been inverted by the NOT circuit 38, is input. In the initial state, the JK flip-flop 32B is initially reset, so the signal e is at H level. Therefore, when signal a (H level) is input, the output of the AND circuit 37 becomes H level. This H level output is
Since the signal is sent to one input terminal of the NAND circuit 39, the gate of the NAND circuit 39 is closed, and the passage of the signal b is prohibited. Therefore, if signal a arrives at the same time as signal b or earlier than signal b, signal b cannot pass through the first-arrival determination circuit 36 (see especially FIG. 4).

When the signal a is input to the D flip-flop 31A, from the time of the rising edge of the clock pulse g, this signal a passes through the D flip-flop 31A (signal c) and becomes the received signal i through the OR circuit 33, and also becomes the received signal i of the JK flip-flop 32A. Input to input terminal J. Since the JK flip-flop 32A is set by the fall of the clock pulse g, its inverted output becomes L level. This L
Since the level signal is fed back to the input terminal K of the JK flip-flop 32A, the JK flip-flop 32A is held in the set state.

The L level signal f at the inverting output terminal of the JK flip-flop 32A is applied to the D flip-flop 31.
Since the D flip-flop 31B is input to the B forced reset terminal R, the D flip-flop 31B is forcibly reset by this L level signal f. Therefore, the output d of the non-inverting output terminal Q of the D flip-flop 31B
is held at L level, and JK flip-flop 3
2B is also held in a reset state, and the NAND circuit 39 also keeps its gate closed while the signal a is being input. This signal f is held at the L level until the initial reset circuit 34 initializes the JK flip-flop 32A, so even if the signal a stops and the gate of the NAND circuit 39 opens, the signal b will not pass through this circuit 39. Even if it passes (signal b1), the D flip-flop 31B is not set. The signal f is a line A priority signal that prohibits the line B signal b1 from passing through the D flip-flop 31B (see FIG. 4).
reference).

The signal b is sent to the first-arrival discrimination circuit 3 before the signal a.
6, even if one input signal e of the AND circuit 37 is at H level, the other input signal a is at L level, so the output of the AND circuit 37 is at L level, and the signal b is at Passes through a NAND circuit 39. Since the signal b is inverted by the NOT circuit 38 and further inverted by the NAND circuit 39, it becomes a NAND signal.
The output signal b1 of the circuit 39 and the signal b have the same shape. The signal b1 inputted to the data input terminal D of the D flip-flop 31B changes from the rising edge of the clock pulse g to the data input terminal D of the D flip-flop 31B.
The signal passes through , becomes a signal d, and further passes through an OR circuit 33 to become a received signal i. Since the signal d is also input to the input terminal J of the JK flip-flop 32B, the JK flip-flop 32B is set by the fall of the clock pulse g. The output e of the inverted output terminal of this JK flip-flop 32B is L
level, and is input to the forced reset terminal R of the D flip-flop 31A. Therefore, even if the signal a is input after this, the D flip-flop 31
A is held in the reset state and input signal a cannot pass through this D flip-flop 31A. Signal e is a line B priority signal (see FIG. 4).

When the JK flip-flop 32B is set and the signal e goes to the L level, the output of the AND circuit 37 continues to be held at the L level regardless of the presence or absence of the signal a, so the gate of the NAND circuit 39 remains open and the input signal b can pass through the NAND circuit 39.

Even if signal b arrives slightly earlier than signal a, if clock pulse g does not rise and fall during this time difference, line B
Before priority signal (L level) e is output
Since the gate of the NAND circuit 39 is closed by the signal a, the signal a on line A is prioritized.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a communication system between multiple devices, Fig. 2 is a block diagram showing a communication control device, Fig. 3 is a block diagram showing a first-come-first-served priority circuit, and Fig. 4 shows the operation of the first-come-first-served priority circuit. This is a time chart. 23...First-come-first-served priority circuit, 31A, 31B...D
Flip-flop (gate circuit), 32A, 32
B...JK flip-flop (gate control circuit),
34... Transmission control and initial reset circuit, 36
...First-come-first-served discrimination circuit.

Claims (1)

[Claims] 1. First and second bistable circuits 31 each connected to two input terminals and functioning as a gate circuit.
A, 31B, a first-come-first-served discrimination circuit 36 that discriminates which signal arrives first among the input signals at the two input terminals, and serves as a gate control circuit for controlling the first and second bistable circuits and the first-come-first-served discrimination circuit. It consists of third and fourth bistable circuits 32A, 32B, a system clock generation circuit 35 that outputs clock pulses of a constant period, an OR circuit 33, and a transmission control and initial reset circuit 34, and The stabilizing circuit 31A passes an input signal from one input terminal in synchronization with a clock pulse, and the second bistable circuit 31B clocks a signal input from the other input terminal via the first-come-first-served discrimination circuit. - The OR circuit 33 outputs the input signal that has passed through either the first or second bistable circuit as a received signal, and the third The bistable circuit 32A changes from one stable state to the other stable state when an input signal is applied through the first bistable circuit, and its output disables the second bistable circuit. The fourth bistable circuit 32B changes from one stable state to the other stable state when a signal input via the second bistable circuit is given, and its output causes the above The first bistable circuit is disabled, and the first-arrival discrimination circuit 36 includes a gate circuit 37 that is controlled by the input signal of the one input terminal and the output signal of the fourth bistable circuit. , 39,
This gate circuit allows the input signal of the other input terminal that has arrived earlier than the input signal of the one input terminal to pass through, thereby causing the output signal of the fourth bistable circuit to be in the other stable state. maintains the enabled state regardless of the presence or absence of an input signal to the one input terminal, and is disabled by the input signal to the one input terminal that arrives earlier or at the same time as the input signal to the other input terminal. The above-mentioned transmission control and initial reset circuit 34 is given the above-mentioned received signal, and this circuit starts receiving the above-mentioned received signal from the time it is input. It outputs a transmission-disabled signal until a certain period of time elapses after the stop of the signal, and when a certain period of time elapses after the stop of the received signal, it gives an initial reset signal to the third and fourth bistable circuits. A first-come, first-served circuit that returns a bistable circuit to one stable state.