JPS60235453A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60235453A JPS60235453A JP59090953A JP9095384A JPS60235453A JP S60235453 A JPS60235453 A JP S60235453A JP 59090953 A JP59090953 A JP 59090953A JP 9095384 A JP9095384 A JP 9095384A JP S60235453 A JPS60235453 A JP S60235453A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- implantation
- heat treatment
- boron
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高濃度の拡散層を製造する方法に係り、特に２
Ｘ１０ ｃｍ 以上のイオン打ち込みによる拡散層を結
晶欠陥なく製造する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a highly concentrated diffusion layer, and in particular to a method for manufacturing a highly concentrated diffusion layer.
The present invention relates to a method for manufacturing a diffusion layer by ion implantation with a size of X10 cm or more without crystal defects.
本発明の拡散層をここでは０ＭＯ８構造をもつ０ＭＯ８
素子に必要なＰ形つェル拡散層に適用して、従来例、本
発明の詳細な説明する。Here, the diffusion layer of the present invention has an 0MO8 structure.
The conventional example and the present invention will be described in detail as applied to a P-type well diffusion layer necessary for an element.
従来の問題点を第１図を用いて説明する。第１図は０Ｍ
Ｏ８素子の断面を示したものであり１例えば、ｌはＮ形
Ｓｔ基板であり、２はＰチャネルＭＯ８）ランジスタ群
、３はＰ形つェル拡散層４内に形成するＮチャネルＭＯ
Ｓトランジスタ群である。５〜８は多結晶Ｓｉからなる
ゲート電極、９〜１２はＰチャネルＭＯＳトランジスタ
のソース・ドレインとなるＰ膨拡散層、１３〜１６はＮ
チャネルＭｏＳトランジスタのソース・トレインとなる
Ｎ膨拡散層である。通常、このＰチャネルＭｏＳトラン
ジスタのＮ形基板電位はＮ形Ｓｉ基板ｌの裏面から金−
８ｉ合金層１７を介して、端子１８より取り出すが、Ｎ
チャネルＭＯ８）ランジスタの基板であるＰ形つェル拡
散層４の電位は表面より、高濃度Ｐ形層１９を介し、端
子２０に取り出している。このＣＭＯ８素子動作におい
て、ＮチャネルＭＯＳトランジスタ（例えばトランジス
タ２１）のソース１４の電位変動は１４−４間の結合容
量２２とＰ形つェル拡散層４の抵抗２３とで決まる時定
数により吸収される。そのため、素子の高速化、高集積
化に伴ない、この抵抗２３が高速化、高集積化時の問題
となり、この抵抗２３の低減が大きな課題となってきて
いる。The conventional problems will be explained using FIG. Figure 1 is 0M
This figure shows a cross section of an O8 element. 1 For example, 1 is an N-type St substrate, 2 is a P-channel MO transistor group, and 3 is an N-channel MO formed in a P-type well diffusion layer 4.
This is a group of S transistors. 5 to 8 are gate electrodes made of polycrystalline Si, 9 to 12 are P swelling diffusion layers that become the source and drain of the P channel MOS transistor, and 13 to 16 are N gate electrodes.
This is an N-swelled diffusion layer that becomes the source/train of a channel MoS transistor. Normally, the N-type substrate potential of this P-channel MoS transistor is from the back surface of the N-type Si substrate 1 to the gold layer.
It is taken out from the terminal 18 through the 8i alloy layer 17, but the N
The potential of the P-type well diffusion layer 4, which is the substrate of the channel MO8) transistor, is taken out from the surface to the terminal 20 via the high concentration P-type layer 19. In this CMO8 element operation, potential fluctuations at the source 14 of the N-channel MOS transistor (for example, transistor 21) are absorbed by the time constant determined by the coupling capacitance 22 between 14-4 and the resistance 23 of the P-type well diffusion layer 4. Ru. Therefore, as devices become faster and more highly integrated, this resistance 23 becomes a problem when the speed increases and the integration becomes higher, and reducing this resistance 23 has become a major issue.
一方、Ｐ形つェル拡散層は一般にＰ形不純物であるボロ
ンのＮ形基板１へのイオン打ち込み技術により形成され
ており、ボロン打ち込み量ＮＩＩを大きくする事により
、ウェル拡散層抵抗Ｒｗを小さくできる。第２図はこの
ＮＩＩとＲｗの関係を示すデータである。しかしながら
従来工程通りに打ち込み量を増加すると打ち込み時のＳ
ｉ基板表面の損傷により、結晶欠陥が発生し、低抵抗化
を制限する。第３図はボロン打ち込み量ＮＧに対し、結
晶欠陥りを調べたものである。曲線Ａは打ち込み後、非
酸化性雰囲気で熱処理（例えば、窒素、１０００℃、６
０分）を行なわないでＣＭＱＳ素子を形成した時のもの
であり、曲線Ｂは熱処理を行なった時のものである。こ
のデータかられかるように従来プロセス工程では約２Ｘ
１０ｃｍ（約ＩＸ１ｌＸ１０ｌ４”以下ではほぼ完全に
結晶欠陥が発生せず、約２Ｘ１０ ｃｍ−”以下でも実
用（１０３個／ｄ程度）に耐えるものである。）の打ち
込みが限度であり、抵抗としては約０．２Ω・ｌ（第２
図のＥ点）が限度であった。On the other hand, the P-type well diffusion layer is generally formed by ion implantation technology of boron, which is a P-type impurity, into the N-type substrate 1, and by increasing the boron implantation amount NII, the well diffusion layer resistance Rw is reduced. can. FIG. 2 shows data showing the relationship between NII and Rw. However, if the driving amount is increased as per the conventional process, S at the time of driving
Damage to the i-substrate surface causes crystal defects, which limits the ability to lower the resistance. FIG. 3 shows an investigation of crystal defects with respect to boron implantation amount NG. Curve A shows heat treatment in a non-oxidizing atmosphere (e.g., nitrogen, 1000°C, 6°C) after implantation.
Curve B is the result when the CMQS element was formed without heat treatment. As can be seen from this data, the conventional process process is approximately 2X
The maximum implantation is 10cm (less than about IX11X10l4", crystal defects are almost completely free, and even less than about 2X10 cm-" can withstand practical use (approximately 103 defects/d)), and the resistance is about 0.2Ω・l (second
Point E in the figure) was the limit.
本発明の目的は０．２Ω・口以下の低抵抗のウェル拡散
層を、結晶欠陥の発生なく、実現する製造方法を提供す
ることにある。An object of the present invention is to provide a manufacturing method that realizes a well diffusion layer with a low resistance of 0.2 Ω or less without generating crystal defects.
第３図の８曲線に着目して説明する。この曲線の示す新
たな発見は以下の２点である。The explanation will be given by focusing on the 8th curve in FIG. This curve shows two new discoveries:
■ 打ち込み時にＳｉ表面がうける損傷が結晶欠陥とな
る場合、打ち込み量にあるしきい値（ここでは約２Ｘ１
０１４ｃＩｎ−”）があり、これを超えると欠陥は急激
に発生する。■ If the damage to the Si surface during implantation becomes a crystal defect, a threshold value (approximately 2×1
014cIn-''), and beyond this, defects occur rapidly.
■ このしきい値以下の打ち込みによる損傷は非酸化性
雰囲気の熱処理で完全に回復できる。■ Damage caused by implantation below this threshold can be completely recovered by heat treatment in a non-oxidizing atmosphere.
この２点に着目し、２Ｘ１０ ａｍ−”以上の打ち込み
を可能とする新しい製造方法を考案した。Focusing on these two points, we devised a new manufacturing method that enables implantation of 2x10 am-'' or more.
以下、本発明の一実施例を第４図（、）〜（ｄ）により
説明する。第４図（ａ）〜（ｄ）はＣＭＯ５素子のウェ
ル拡散層部分について製造方法を示したものである。第
４図（ａ）〜（ｄ）は本発明を構成する単位工程のみに
よる場合を示したものである。まず、Ｎ形Ｓｔ基板４１
を酸化し、表面に酸化膜４２を形成する（第４図（ａ）
）。この酸化膜を介し表面よりボロン打ち込みを行ない
、高濃度Ｐ形層４３を形成する。この時のボロン打ち込
み量は約２×１０ （２）−２以下に制限される（第４
図（ｂ））。続いて、非酸化性雰囲気で熱処理（例えば
、窒素、１１００℃、４時間）を行ない、Ｐ形つェル拡
散層４４を形成する。この熱処理は１０００℃以上、３
０分以上であればよく、これにより、打ち込み時の損傷
は回復し、結晶欠陥を抑圧できる（第４図（Ｃ））。以
後、通常のプロセスにより、Ｐ形つェル拡散層４４内に
ＮチャネルＭＯＳトランジスタ４５を形成し、０ＭＯ８
素子を完成する（第４図（ｄ））。この場合はボロン打
ち込み量が限定され、Ｐ形つェル拡散層の低抵抗化が制
限されている。An embodiment of the present invention will be described below with reference to FIGS. 4(,) to (d). FIGS. 4(a) to 4(d) show a manufacturing method for the well diffusion layer portion of a CMO5 element. FIGS. 4(a) to 4(d) show a case in which only the unit steps constituting the present invention are used. First, N type St substrate 41
is oxidized to form an oxide film 42 on the surface (Fig. 4(a)
). Boron is implanted from the surface through this oxide film to form a high concentration P type layer 43. The amount of boron implanted at this time is limited to approximately 2×10 (2)-2 or less (fourth
Figure (b)). Subsequently, a heat treatment (for example, nitrogen, 1100° C., 4 hours) is performed in a non-oxidizing atmosphere to form a P-type well diffusion layer 44. This heat treatment is carried out at temperatures of 1000°C or higher.
It is sufficient that the time is 0 minutes or more, and as a result, damage caused during implantation can be recovered and crystal defects can be suppressed (FIG. 4(C)). Thereafter, an N-channel MOS transistor 45 is formed in the P-type well diffusion layer 44 by a normal process, and an 0MO8
The device is completed (FIG. 4(d)). In this case, the amount of boron implanted is limited, and the reduction in resistance of the P-type well diffusion layer is limited.
第５図（ａ）〜（ｄ）は本発明の製造方法を示す断面図
である。まずＮ形Ｓｔ基板４１を酸化し。FIGS. 5(a) to 5(d) are cross-sectional views showing the manufacturing method of the present invention. First, the N-type St substrate 41 is oxidized.
表面に酸化膜４２を形成する（第５図（ａ））。An oxide film 42 is formed on the surface (FIG. 5(a)).
この酸化膜を介し、表面よりボロン打ち込みを行ないＰ
形層４６１を形成する。この時のボロン打ち込み量は約
２Ｘ１０”ｃｍ−”以下である（第５図（ｂ））。続い
て非酸化性雰囲気で熱処理（例えば、窒素、１１００℃
、１時間）を行ないＰ形つェル拡散層４７１を形成する
（第５図（Ｃ））。続いて、第５図（ｂ）と同様にボロ
ン打ち込みを行ない、高濃度Ｐ形層４６２を形成する。Boron is implanted from the surface through this oxide film, and P
A shape layer 461 is formed. The amount of boron implanted at this time is approximately 2.times.10"cm" or less (FIG. 5(b)). Subsequently, heat treatment in a non-oxidizing atmosphere (e.g. nitrogen, 1100°C
, 1 hour) to form a P-type well diffusion layer 471 (FIG. 5(C)). Subsequently, boron implantation is performed in the same manner as in FIG. 5(b) to form a heavily doped P-type layer 462.
この時のボロン打ち込み量も約２Ｘ１０ ａｍ−”以下
である（第５図（ｂ２））。続いて、第５図（ｃ）と同
じく熱処理（例えば、窒素、１１００℃、１時間）を行
ないＰ形つェル拡散層４７２を形成する（第５図（ｅ
２） ） 、続いて第５図（ｂ）、（Ｃ）をペアとして
ｎ回（複数回）工程を行ない、第５図（ｂ）、（ｅ）の
工程のｎ回目を行なった後に最終的なＰ形つェル拡散層
４７ｎが形成される（第５図（ｃ ｎ）。以後、従来工
程、第４図（ｄ）の工程を行ない、ＣＭＯ５素子を完成
する（第５図（ｄ））。この本発明の製造方法によれば
、約２Ｘ １０１４ａｓ −”以下の打ち込み量のｎ倍
の打ち込みを、結晶欠陥を発生させる事なく製造できる
。例えば第５図（ｂ）、（ｃ）の工程を３回（ｎ＝３）
くり返して行なう事により、結晶欠陥を・はぼ完全に抑
圧できる最大ボロン打ち込み量を従来の３倍の約６ Ｘ
１０” ｃｍ−・２とする事ができ、Ｐ形つェル拡散
層抵抗を約０．０７Ω・ｌまで低抵抗化できる（第２図
より）。第３図の曲線Ｃは３回の場合のデータであり、
結晶欠陥をほぼ完全に抑圧できる打ち込み限度を従来（
曲線Ｂ）の３倍の約３×１０”Ｃｌ１１−”とできてい
る。また、Ｃ′曲線は熱処理条件を１０００℃、６０分
、窒素とした時の予想曲線であるが、実用に耐える打ち
込み限度を従来（曲線Ｂ）の３倍の約６Ｘ１０ｃｎ−”
とできている。なお、曲線Ｃは熱処理を高温（１１００
℃）で行なっているため、欠陥回復効果が強く、傾きが
小さくなっている。The amount of boron implanted at this time is also about 2×10 am-” or less (Fig. 5 (b2)).Subsequently, heat treatment (e.g., nitrogen, 1100°C, 1 hour) is performed in the same manner as in Fig. 5 (c). Form a well-shaped diffusion layer 472 (see FIG. 5(e)
2) ), then perform the process n times (multiple times) with Figure 5 (b) and (C) as a pair, and after performing the nth process of Figure 5 (b) and (e), the final A P-type well diffusion layer 47n is formed (FIG. 5(c)). Thereafter, the conventional process and the process shown in FIG. 4(d) are performed to complete the CMO5 element (FIG. 5(d)). ). According to the manufacturing method of the present invention, it is possible to manufacture n times the implantation amount of approximately 2X 1014 as -" or less without generating crystal defects. For example, the manufacturing method shown in FIGS. 5(b) and (c) Repeat the process 3 times (n=3)
By repeating this process, the maximum amount of boron implanted that can almost completely suppress crystal defects can be increased to approximately 6X, three times the conventional amount.
10" cm-・2, and the resistance of the P-type well diffusion layer can be lowered to about 0.07Ω・l (from Figure 2). Curve C in Figure 3 shows the case of 3 times. The data is
Conventionally, the implantation limit that can almost completely suppress crystal defects was set (
It is approximately 3×10"Cl11-" which is three times that of curve B). Curve C' is an expected curve when the heat treatment conditions are 1000℃, 60 minutes, and nitrogen, but the practical implantation limit is about 6X10cn-" which is three times the conventional (curve B).
It is made with. Curve C shows heat treatment at high temperature (1100
℃), the defect recovery effect is strong and the slope is small.
本発明は０ＭＯ８素子でも、とくにウェル拡散層内にホ
トダイオードアレーを形成する固体撮像素子において、
最大の効果を発揮できるものである。即ち、０ＭＯ８構
造の撮像素子では光を入力とするため、ホトダイオード
アレー内部ではウェル拡散層の電位を取り出す事が不可
能であり、アレー周辺からしか電位を取り出せない。そ
の結果、ウェル拡散層の電位変動を小さくするため、ウ
ェル拡散層の低抵抗化が必須の技術となるからである。The present invention applies even to 0MO8 elements, particularly to solid-state imaging elements in which a photodiode array is formed in a well diffusion layer.
It is the one that can have the greatest effect. That is, since the image sensor with the 0MO8 structure receives light as input, it is impossible to extract the potential of the well diffusion layer inside the photodiode array, and the potential can only be extracted from the periphery of the array. As a result, in order to reduce potential fluctuations in the well diffusion layer, lowering the resistance of the well diffusion layer becomes an essential technique.
本発明によれば、ボロン打ち込み工程と熱処理工程とを
ペアとして、複数回行なう事により、打ち込み量の限度
を複数回倍にする事ができ、所望の低抵抗ウェル拡散層
を結晶欠陥の発生なく実現できる。その結果、０ＭＯ８
素子の高速化、高集積化を実施しても、ウェル層の電位
変動に伴なう素子の誤動作を抑圧することができる。従
来の高速化、高集積化時の制限要因の１つをなくすこと
ができる。According to the present invention, by performing the boron implantation process and the heat treatment process as a pair multiple times, the limit of the implantation amount can be doubled multiple times, and the desired low resistance well diffusion layer can be formed without generating crystal defects. realizable. As a result, 0MO8
Even if devices are made faster and more highly integrated, malfunctions of the devices due to potential fluctuations in the well layer can be suppressed. It is possible to eliminate one of the limiting factors when increasing speed and integration in the past.
第１図は、従来の０ＭＯ８素子の断面図、第２図は、ウ
ェル領域抵抗と、不純物打込み量の関係を示す図、第３
図は、不純物打込み量と、結晶欠陥の関係を示す図、第
４図（ａ）〜（ｄ）は、本発明の単位工程によるウェル
拡散層形成法を工程順に示す断面図、第５図（ａ）〜（
ｄ）は、本発明による製造工程を工程順に示す断面図で
ある。
１．４１・・・基板、４２・・・酸化膜、４３・・・高
濃度Ｐ型層、４４・・・Ｐ型ウェル拡散層、４６１，４
６２゜−、４６ｎ＝１’型打人層、４７１，４７２．−
。
４７ｎ・・・Ｐ型ウェル拡散層。
第 ｌ 図
第２圀
手 続 補 正 書 （方 式）
事件の表示
昭和５９年 特 許 願 第９０９５３ 号発明の名称
半導体装置の製造方法
補正をする者
事件との関係 特許出願人
名称（５１０） 株式会社 日 立 製 作 所代 理
人
居所〒１００ 東京都千代田区丸の内−丁目５番１号株
式会社 日 立 製 作 所 内
型 話 東 京２１２−１１１１（大代表）補正の対象
明細書のｒｗな説明」の欄。
図面の簡単
補正の内容
１、 明細書第９頁第７行記載の［第５図（ａ）〜（ｄ
）は、」を「第５図は、」と訂正する。Figure 1 is a cross-sectional view of a conventional 0MO8 element, Figure 2 is a diagram showing the relationship between well region resistance and impurity implantation amount, and Figure 3 is a diagram showing the relationship between well region resistance and impurity implantation amount.
The figure shows the relationship between the amount of impurity implantation and crystal defects, FIGS. a)～(
d) is a sectional view showing the manufacturing process according to the present invention in order of process. 1.41...Substrate, 42...Oxide film, 43...High concentration P type layer, 44...P type well diffusion layer, 461,4
62°-, 46n=1' batting layer, 471,472. −
. 47n...P-type well diffusion layer. Figure 1. Proceedings in Section 2 Amendment (Format) Indication of the case 1982 Patent Application No. 90953 Title of the invention Relationship to the case of person amending the manufacturing method of a semiconductor device Name of the patent applicant (510) Hitachi Co., Ltd. Manufacturing Co., Ltd. Principal Residence Address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo 100 Hitachi Co., Ltd. Manufacturing Co., Ltd. Internal model Tokyo 212-1111 (main representative) Subject of amendment RW of specification "Explanation" column. Contents of simple amendment to drawings 1, [Figures 5 (a) to (d) described in page 9, line 7 of the specification]
) is corrected to ``Figure 5 is''.
Claims (1)
ち込み、非酸化性雰囲気中で熱処理を行ない、少なくと
もこれを２回以上連続して行なう工程を含む事を特徴と
する半導体装置の製造方法。 ２、特許請求の範囲第１項記載の半導体装置の製造方法
において、１回の不純物イオン打ち込み量が２Ｘ１０”
ｅｌｌ−”以下である事を特徴とする半導体装置の製造
方法。[Claims] 1. The method is characterized by including a step of implanting impurity ions of the same type onto the main surface of a semiconductor substrate, performing heat treatment in a non-oxidizing atmosphere, and performing this process at least twice or more consecutively. A method for manufacturing a semiconductor device. 2. In the method for manufacturing a semiconductor device according to claim 1, the amount of impurity ions implanted at one time is 2×10"
1. A method for manufacturing a semiconductor device, characterized in that it is less than or equal to ``ell-''.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090953A JPH0622279B2 (en) | 1984-05-09 | 1984-05-09 | Method of manufacturing solid-state image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59090953A JPH0622279B2 (en) | 1984-05-09 | 1984-05-09 | Method of manufacturing solid-state image sensor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60235453A true JPS60235453A (en) | 1985-11-22 |
| JPH0622279B2 JPH0622279B2 (en) | 1994-03-23 |
Family
ID=14012845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59090953A Expired - Lifetime JPH0622279B2 (en) | 1984-05-09 | 1984-05-09 | Method of manufacturing solid-state image sensor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0622279B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0276224A (en) * | 1988-09-10 | 1990-03-15 | Fujitsu Ltd | Manufacture of compound semiconductor device |
| JPH03278430A (en) * | 1990-03-28 | 1991-12-10 | Kawasaki Steel Corp | Manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5447473A (en) * | 1977-09-21 | 1979-04-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of implanting ion to semiconductor |
-
1984
- 1984-05-09 JP JP59090953A patent/JPH0622279B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5447473A (en) * | 1977-09-21 | 1979-04-14 | Cho Lsi Gijutsu Kenkyu Kumiai | Method of implanting ion to semiconductor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0276224A (en) * | 1988-09-10 | 1990-03-15 | Fujitsu Ltd | Manufacture of compound semiconductor device |
| JPH03278430A (en) * | 1990-03-28 | 1991-12-10 | Kawasaki Steel Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0622279B2 (en) | 1994-03-23 |
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