JPS6023505B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an insulated gate field effect transistor and a capacitor serving as an information storage section.

[Background of the Invention] As is well known, semiconductor memory devices equipped with an insulated gate field effect transistor and a capacitor serving as an information storage section are widely used, but with the remarkable increase in integration density in recent years, the required area has There is a strong demand for a reduction in

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device with a significantly smaller desired area and with a much higher integration density than conventional ones.

[Summary of the invention]

In order to achieve the above object, the present invention utilizes pongee pores formed inward from the main surface of a semiconductor substrate as a capacitor, and forms one electrode on the surface of the pore with an insulating film interposed therebetween. At the same time, the other electrode is formed along the surface of the pore.

[Embodiments of the Invention] Figures 1a and 1b also show conceptual diagrams of the present invention.

The case of drain capacitance is shown in a, and the case of inversion capacitance is shown in b. The gist of the present invention is to drill pores 16 in the semiconductor substrate 4,
The purpose is to use the surface of the inner wall of this pore as a capacitor.
It is characterized in that the area of the inner wall of the pore can be significantly expanded relative to the area of the entrance part on the substrate surface. In this way, the storage capacity can be expanded without increasing the planar area, and the disadvantages of multi-stage connection, which were the disadvantages of the conventional method, can be dramatically reduced. According to the related example, the capacitance of 100 mm is about 1 pF, but the pore in Figure 1 has an opening of 2 mm x 100 mm.
Since a depth of 50 mm can be easily formed in rm, the area of the substrate surface can be reduced to 1/50 while the area of the capacitor remains the same.

In this example, an integration degree of at least 5 tones is achieved with the same board area as in the prior art. Moreover, if the scale is the same, the area can be reduced to 1/50, and the effects of the embodiment of the present invention are immeasurable. Next, the method for forming the pongee hole will be described.

An etching method using this solution of KOH has been known for a long time, and the etching rate of the {111} plane of silicon is particularly slow. It is also possible to increase the speed. In other words, orientation-dependent etching (mien side ion depend
The {111} plane, which has the slowest etching rate, can be formed with high precision using the etching method. This explanation is shown in FIG. Because the purpose of the present invention is to form pores deep in the vertical direction, the surface of the substrate is in the {110} plane or its vicinity (hereinafter, when the {110} plane is referred to as the {110} plane, unless otherwise specified, the vicinity thereof is also included. is {110}
In the case of a {110} plane, there must be no other low index plane within 20o. As shown in FIG. 2, etching mask hole side lines 17 are formed on the {110} plane.

As an etching mask, any material can be used as long as it is sufficiently slower than the etching rate of silicon;
2 is used. A wide etching mask hole is formed in this Si02 film, and then etched with a KOH aqueous solution. FIG. 3 shows the measured values of the etching rate and KOH concentration of the {110} plane. The dependence of the etching rate on the KOH concentration is 4.0%, but in consideration of the smoothness of the etched surface, a concentration of 20% or more is appropriate. For example, liquid temperature 80q
If a solution with an OKOH concentration of 40% is used, the etching rate is 1.
．． The speed is 25 m/min. For example, 6
When etched for 0 minutes, the depth D of the etching hole is 75A.
m.

As shown in FIG. 2, the inner wall surface 18 of the etching hole is {1
11} plane, and the etching mask hole side line 17 is {
111} plane and the {110) plane from the [112] direction, the larger 0 is, the more minute {111} planes will be on the inner wall surface. The figure depicts a surface with many steps and concave and convex portions, but this is an atomically enlarged version, and the actual inner wall surface is a mirror surface, so the schematic concave and convex surface shown in the figure cannot be seen. Furthermore, the final width LF of the etching hole is generally expanded compared to the width peak of the etching mask hole, and the amount of expansion strongly depends on 8'.

Let the amount of enlargement be m and define it by the following equation. m: three; three
---... [1' This m is the distance from the side line of the etching mask to the inner wall surface of the etching hole.

The relationship between m and the value 0 normalized by the etching hole depth D is shown in FIG. Human m/D shows a nearly linear relationship, and m is expected to be very small when 8=0. In other words, it is shown that if the side line of the etching mask hole is exactly in the [112] direction, an etching hole with almost the same width as the etching mask hole width can be formed. In reality a
=0 cannot be used. For example 8:
In the case of No. 10, if an etching hole with a depth of 7.5 meters is formed as described above, m=2.6 meters. In other words, even if the width Lo of the etching mask hole is 1 m, there are 2
．． The width of the etching hole is increased by 6 meters, and the final etching hole width is 6.6 meters. Although the pore-forming etching method used to carry out the present invention has been described above, the present invention does not limit the etching method and does not limit the type of etching method.

The present invention will be explained below using detailed examples.

In addition, in the description of the present invention, the above-mentioned pongee hole forming etching is
DE(OrientationDependentEt
The detailed etching conditions will not be specified each time. In addition, the structure of the present invention is a drain capacitor (Fig. 1a) or an inversion capacitor (Fig. 1b).
An example of the drain capacitance will be described first. FIG. 5 shows an embodiment of the present invention.

First, as shown in a, an etching hole 19 is formed on the substrate 4 in an insulating film (often made of SiO2) by photo-etching. After that, OD
A pore 16 is formed by E, and as shown in b, a substrate of the first conductivity type and a second conductivity type opposite to that of the first conductivity type substrate are removed by a known thermal diffusion or ion implantation method, except for the insulating film in the source region and the hole area. A mold region 5 is formed.As shown in c, an insulating film 6 is then deposited by a thermal oxidation method or the like, an electrode connection hole 20 is formed by a photoetching method or the like, and then a gate electrode 8 is formed as shown in d. , a source electrode 7 is formed.By doing this, the structure of the present invention shown in FIG. 1a can be realized.Another embodiment of the present invention is shown in FIG.

The process up to step a is the same as the method shown in FIG. After that b
As shown in FIG. 2, a self-aligned electrode 21 is formed on a predetermined insulating film 6, and using this as a mask, a second conductivity type region 5 is formed by known ion implantation or thermal diffusion method as shown in c. The self-aligned electrode 21 may be made of a material that can withstand ion implantation or thermal diffusion.
High melting point metals such as O, W, etc. are often used. Furthermore, on top of that, CVD (Chemical Vapor Depo)
PSG (Phospho-silica Glass) and BSG (Boro-silica G
A source electrode 7 which is connected to the source region and the self-aligned electrode 21 is coated with a second layer insulating film 22 typified by
and the gate electrode 8 are connected. In this embodiment, the source region, the drain region, and the gate are formed in self-alignment, so that miniaturization of the device can be achieved. FIG. 7 shows another embodiment of the present invention.

As shown in a, an insulating film 6 is formed, and self-aligned electrodes 21 are formed in predetermined portions. Since this electrode is used as a mask for ODE etching, it needs to be dissolved in a KOH aqueous solution, but the aforementioned polycrystalline silicon, Mo, W, etc. are easily soluble. Therefore, it is also necessary to deposit the insulating film 6 on the electrode 21 as well. Next, as shown in b, a hole 16 is formed by ODE, and then the insulating film 6 in the source portion is removed using the electrode 21 as a mask. Thereafter, as shown in c, a second conductivity type region 5 is formed by known ion implantation or thermal diffusion method, and a second layer insulating film 22 is deposited. Further, as shown in d, an electrode connection hole 20 is formed by photoetching, and a source electrode 7 and a gate electrode 8 are formed. In this embodiment, since the pore, drain, source, and gate are self-aligned, the device can be made even smaller than the embodiments shown in FIGS. 5 and 6. At this time, the self-type electrode 21 is formed so as to surround the pore 16, as shown in the plan view e. The three embodiments of the present invention have been described above, and in the case of FIGS. 5 and 6, an example was used in which the drain and the gate are lined up in one direction.

As shown in FIG. 8, a second conductivity type region 5 that becomes a gate electrode and a source can be formed to surround the pongee hole 16. Furthermore, although all of the above three embodiments of the present invention have been explained using one element, the data line 13, which is the connection of the source region arranged in a matrix, and the word line 13, which is the connection of the gate, intersect with each other. .

At this time, in the above three embodiments, the gate electrode 8 and the source electrode 7 cannot be separated within the same plane. To solve this problem, from the second conductive region 5 of the source to the source electrode 7.
It is sufficient to align it on the surface of the substrate 4 without connecting it.
However, in this case, the region 5 cannot be formed directly under the self-aligned electrode 21 that becomes the gate, so in the case of FIGS. need to be formed. For this purpose, a part of the insulating film mask 6 is removed and a region 5 of the second conductivity type is formed by known ion implantation or thermal diffusion method, as shown in FIG. 9a, or the entire surface of the substrate is formed as shown in FIG. A method can be used in which after forming the region 5, the region 5 that will become the source region is left and the rest are removed.

FIG. 10 shows an embodiment of the present invention arranged in a matrix.

A is a case in which the source and gate are arranged in one direction, and b is a case in which the source is formed to surround the gate. Using the method described above, the second conductivity type region 5 serving as the source is used as a data line, and the self-aligned electrode 21 serving as the gate is used as a word line. At this time, it is necessary to electrically isolate the sources arranged in parallel, and a separation band 23 is formed between them. This separation band can be formed by increasing the thickness of the insulating film above it to 5000A or more, by adding impurities that have the same conductivity type as the substrate, or by connecting the third electrode to the electrode 2 through the insulating film 6.
Several methods are known, such as forming a channel under the substrate and applying a voltage to prevent it from forming a channel on the substrate and becoming conductive, but the present invention is not limited to these methods. . FIG. 11 shows another embodiment of the present invention. This uses the inverting capacitance b in Figures 1, 2, and 5.
As shown in FIG. 1, a region 5 of the second conductivity type that becomes a source
Then, as shown in b, pores 16 are formed in predetermined portions by ODE. Furthermore, after forming the insulating film 6 as shown in c, electrode connection holes 20 are formed on the source, and as shown in d, the source electrode 7, the gate electrode 8,
A capacitor electrode 9 is formed and the inner wall of the pore is used as a capacitor. Another embodiment of the invention is shown in FIG.

In this method, the gate and source are formed by self-alignment. After forming the pongee hole 16 by ODE as shown in a, an insulating film 6 covering the entire surface is formed, and a self-aligned electrode 21 is formed in a predetermined position as shown in b. After forming the second conductivity type region 5 in the position, the second conductivity type region 5 is formed by using this as a mask by known ion implantation or thermal diffusion method. Thereafter, a second layer insulating film 22 is formed as shown in c, and a source electrode 7 is formed as shown in d.
, the gate electrode 8 and the capacitor electrode 9 are connected through the electrode connection hole. By doing so, the source, gate, and capacitor electrode can be formed by self-alignment, which is effective for miniaturization. Another embodiment of the invention is shown in FIG.

In this method, the gate, source, capacitor electrode, and pore are formed by self-alignment.As shown in a, after forming the self-aligned electrode 21 by the method described above, this is used as a mask during ODE etching. An insulating film 6 is deposited and ODE is applied as shown in b using this as a mask.
After forming the pores 16 by etching, the inner walls of the pores are covered with an insulating film 6. Thereafter, as shown in c, the second self-aligned electrode 24 is inspected and a predetermined portion is left. Thereafter, a second conductivity type region 5 which becomes a soot is formed by known ion implantation or diffusion. Further, this region 5 may be formed before the second self-aligned electrode 24 is formed. Thereafter, as shown in d, a second layer insulating film 22 is formed and an electrode connection hole 20 is formed, after which the source electrode 7, gate electrode 8, and capacitor electrode 9 are connected. This allows the electrodes to be formed in self-alignment with each other, which is advantageous for further miniaturization. FIG. 14 shows another embodiment of the present invention in which source and gate capacitor electrodes are formed by self-alignment in a different arrangement from that in FIG. 13.

In addition to the method of arranging the capacitor electrode, source, and gate in one direction as shown in FIGS. 15, 16, 17, and 18, there is also a method of arranging the capacitor electrode, source, and gate in one direction as shown in FIG. Can be arrayed.

Further, when a large number of elements are arranged in a matrix and a common source is to be used, the common source shown in FIG. 13 may be formed in advance as described above. The elements having this capacitive electrode can be arranged in a matrix as shown in FIG. This is a structure in which a capacitor electrode is added when using the tenth drain junction capacitor, and the gate electrode and the capacitor heavy electrode may be arranged alternately as shown in the figure.
In this way, the matrix can be constructed without forming electrode connection holes, so miniaturization can be achieved. In the description of the present invention, for convenience, the insulating film 6 is formed on the substrate surface and on the self-aligned electrode in the same way, but a different insulating film may be used on each substrate.

Further, in the present invention, a {110}-plane silicon substrate is used,
For other low-index planes, such as {111} and {100}, it is impossible to form pongee holes that are almost perpendicular to the surface, so there is little effect of the embodiment of the present invention. preferable.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the required area can be significantly reduced, and it is extremely effective in improving the integration density.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing the concept of the present invention, Fig. 2, Fig. 3,
Figure 4 is a diagram explaining the method of forming pores, Figures 5 to 15
The figures up to the figures are diagrams showing embodiments of the present invention. Figure 2, figure 3, figure 4, figure 5, figure 7, figure 7, figure 8? Four brothers /0 Two brothers ′′ Two brothers ’2 Two brothers /3 Four brothers /4 Two brothers ’5 Pictures

Claims (1)

[Claims] 1. In a semiconductor memory device including a capacitor serving as an information storage portion and an insulated gate field effect transistor, the capacitor is laminated on the surface of a pore formed from the main surface of the semiconductor substrate toward the inside of the substrate. What is claimed is: 1. A semiconductor memory device comprising at least an insulating film and a capacitor electrode formed as a semiconductor memory device, the other electrode of the capacitor being formed in the substrate along the surface of the pore.