JPS6023436B2 - Non-volatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable, high-density, large-scale insulated gate field-effect nonvolatile semiconductor memory device.

Currently, semiconductor memory devices require about six transistors for one bit.

There are so-called static operation types based on flip-flops, and dynamic operation types that use 1 to 3 insulated gate field effect transistors (IGFETs) for each bit and store information while constantly refreshing.
is widely used. On the other hand, as a semiconductor memory device that utilizes the threshold change caused by trapping charges in the trap level in the gate insulating film on the channel of the IGFET,
MAOS (Metal. AI skin mi cape. Si1icon
Oxide. Si1icon) or MN〇S (Met
Al-Silicon Ni-de-Silicon
A device with a two-layer insulating film called Oxide-Silicon is well known.

In addition, the gate insulating film is made of a strong electrolyte, and a charge commensurate with the spontaneous polarization of the strong electrolyte is generated on the silicon surface at the interface with the silicon ferroelectric. Non-volatile semiconductor memories that use the memory function of By applying a voltage between the gate electrode and the substrate or between the gate electrode and the channel, these can change the conductivity between the source and drain, or completely eliminate the conductivity.
Furthermore, the conductivity can be maintained for a long time due to the memory effect of the gate insulating film.

In addition, a floating gate is provided in the gate insulating film, and by injecting a charge into the floating gate by some means and inducing a charge of the opposite polarity on the silicon surface, conduction between the source and drain can be improved. There are also ways to change the degree.

Charge can be injected into the floating gate from the silicon substrate or electrode side using tunneling or Schottky effects, or by creating an appropriate p-n junction on the substrate side, an avalanche phenomenon can be caused. It is also possible to create so-called hot electrons and hot holes with high energy and inject them by overcoming the energy barrier at the interface between silicon and silicon oxide films.

Although the present invention relates to a so-called non-volatile semiconductor memory that accumulates charges in a trap level or a floating gate in an insulating film or uses a strong gate as described above, it does not require a special structure. Without limitation, non-volatile memory has a gate structure in which the direction of the trap or spontaneous polarization of the captured charge can be changed by applying a voltage between the gate electrode and the substrate or between the gate electrode and the channel. The substrate is an insulated gate field effect transistor.

Conventionally, when this type of non-volatile memory is arranged in a matrix on a single semiconductor substrate, the purpose of this is to prevent the memory transistors from becoming normally-on and making it impossible to select bits during reading. , normally off (n
A commonly used method is to connect transistors with a fixed gate threshold voltage (onnaily-oH). However, this configuration is disadvantageous for high-density integration, and has the drawback that the number of memory transistors that can be fabricated on one chip must be halved.

Furthermore, even if a non-volatile insulated gate field effect transistor with characteristics that would enable the simplest configuration of one transistor per bit could be obtained,
When arranging them in parallel in a matrix to form a memory device, source and drain wiring is inevitably required for each bit transistor. In a memory device that is integrated by wiring transistors in parallel, the wiring occupies a very large area, and is one of the major factors preventing higher density. Yet another factor hindering high density, which can be a problem especially in the case of n-channel devices capable of high-speed operation, is the need for electrical isolation between wires or devices. .

Therefore, a highly concentrated impurity layer having the same conductivity type as the substrate must be formed on the surface of the substrate where electrical isolation is required between wirings, between elements, or between wirings and elements. Furthermore, in order to maintain the electrical breakdown voltage between the wiring layer and the fin gas isolation layer, it is necessary to provide a sufficient distance between the wiring layer and the electrical isolation layer.
That is, it can be seen that if these measures are taken and the memory transistors are arranged in parallel as in the past, a large area will be taken up in areas other than the memory transistors, making it impossible to achieve high density and high integration. One object of the invention is to provide a storage device of simple construction that can increase the density of monolithic integrated circuit storage arrays.

Still another object of the present invention is to provide a storage device that can store given information semi-permanently or for a desired fixed period of time without being supplied with power.

Still another object of the present invention is to provide a unique driving method that is only possible with this storage device.

In this invention, an insulating film having a charge storage mechanism is provided on the semiconductor substrate surface so-called field effect channel region between a source region and a drain region having a conductivity type opposite to that of the substrate, and a source region is provided on the insulating film. It has a plurality of gate electrodes extending from the source to the drain direction (or the same goes from the drain to the source direction), and the surface of the semiconductor substrate between these electrodes is provided with a region having the same conductivity type as the source and drain regions, or The gate electrodes are so close that even if there is no region between the gate electrodes having the same conductivity type as the source and drain regions, the channel regions under each gate electrode can be connected by simply applying an appropriate voltage to the gate electrodes. A memory device (hereinafter abbreviated as a memory transistor having a plurality of gate electrodes), which is characterized by a plurality of gate electrodes, is first produced.

Here, the insulating film under the gate can be easily obtained using a material such as the above-mentioned MNOS, and the gate dark voltage can be varied by applying a voltage between the gate electrode and the semiconductor substrate or between the gate electrode and the channel part. The threshold voltage can be maintained within a certain tolerance range for a long time.

Furthermore, according to the present invention, in arranging a plurality of memory transistors having several gates after overreading, the gates at the same positions of the plurality of memory transistors having a plurality of gates are commonly connected, and each The drains of one insulated gate field effect transistor for switching are connected to the sources of the memory transistors each having a plurality of gates, the sources of the switching transistors are commonly connected to the gates of the insulated gate field effect transistors for reading, and An insulated gate field effect transistor for charging and discharging is connected to the gate of the insulated gate field effect transistor for reading, and the drain of the memory transistor having a plurality of gates and the gate of the switching transistor are commonly connected. A nonvolatile semiconductor memory device including at least one memory block is obtained.

Next, the operation of the nonvolatile semiconductor memory device according to the present invention will be explained using the drawings.

Prior to that, we will first briefly explain the basics of the insulated gate field effect non-rigid transistor having a plurality of gates, which is the basis of the present invention. FIG. 1 shows a typical example of a memory transistor having characteristics suitable for use in the present invention.

First, a p-type source region 2 and a p-type drain region 3 are formed separately on an n-type silicon substrate 1, and a source electrode 4 and a drain electrode 5 are attached to each. Typically, a silicon oxide film 6 and a relatively thick silicon nitride film 7 are present on the silicon substrate surface of the source region 2 and drain region 3, and between the silicon oxide film 6 and the silicon nitride film 7, tungsten, etc. microparticles may be inserted. Near the interface between the silicon oxide film and the silicon nitride pus, a charge accumulation layer is formed. On the silicon nitride film 7, n gate electrodes 8 (G., G2, . . . Gn) are provided which are electrically isolated from each other and are as close to each other as possible. is provided with a substrate electrode 9, and the surface of the substrate other than between the source and drain is covered with an insulating film 1.
Protected by 0. Further, a p-type layer 11 is provided on the surface of the substrate directly under the gap between the gate electrodes. By providing such a p-type layer 11, it is possible to prevent channel formation from being interrupted directly under the gap between the gate electrodes. The typical two-layer structure of a silicon oxide film and a silicon oxide film, which is used here and plays an important role as a rewritable memory element, will be explained in more detail with reference to numerical values in typical examples.

For example, a typical MNOS body uses low-resistance polysilicon containing aluminum or impurities for the gate electrode metal, the silicon nitride film is 450A thick, the silicon oxide film is 90A thick, and the silicon nitride film is 450A thick, the silicon oxide film is 90A thick, and An example of implementation in which 1.5×1 and 5 atoms of tungsten or the like are inserted at the interface between the film and the silicon oxide film exhibits extremely favorable characteristics.

Such an MNOS device has a relatively thick silicon oxide film, so when a pulse of about 100 microseconds at 13 W is applied to the gate electrode of the substrate, only electrons are injected from the silicon substrate, and silicon nitride is It is trapped near the interface between the pus and the silicon oxide film, making it possible to increase the gate threshold voltage of the MNOS structure to 13V or more.

These captured electrons are no longer able to move easily under the weak electric field that is applied to the insulating film during readout and memory retention, and at room temperature, they can be captured for a long time. You can keep it as it is.

These captured electrons induce holes, which are sacrificial charges opposite to electrons, on the surface of the silicon substrate, forming a p-type channel in the case of an n-type substrate.

When a pulse of about 100 microseconds at -3W is applied to the gate electrode of the substrate, electrons can be easily transferred to the silicon nitride film and the silicon oxide film through particles such as tungsten at the interface between the silicon nitride film and the silicon oxide film. It is emitted from near the interface with.

If particles such as tungsten are not inserted, it is difficult to completely restore the gate function to the value before writing, and even if a high voltage is applied forcibly, the insulating film will only be destroyed and it will not be possible to rewrite by emitting electrons. difficult. If the silicon oxide film is as thick as about 90A, holes will not be injected from the silicon side simultaneously during electron emission, and if tungsten or the like is inserted, the gate threshold voltage will be 12V.
Saturation occurs at a certain level.

This saturated property is very beneficial to the present invention. In order to know the conductivity state (conducting or non-conducting) under the gate that an insulated gate field effect memory transistor with multiple gates wants to read, it is necessary to make all other channels under the gate conductive. On the other hand, the voltages applied to all other gates required for this purpose are smaller than the 35V voltage used for writing and erasing, and are also small enough not to affect the memory retention characteristics, such as for p-channel. Therefore, if the gate threshold voltage is saturated at -2V as mentioned above, the conductive state can be maintained at about -5V at most without leaving any problems in memory retention. This is because it can be ensured by bias. FIG. 2 shows an example of a memory block in which n p-channel memory transistors each having m gates are arranged in parallel in one column, which is an example of an embodiment of the present invention.

As mentioned above, the sources of n memory transistors 101 each having m gates are normally off (
It is connected to the gate of a read transistor 103 via a normally-off type switching transistor 102 .

Further, a charge/discharge transistor 104 is connected to the gate of the read transistor 103 to perform dynamic read.

This charging/discharging transistor 104' Well, if this memory block, which was adopted for the first time in this invention, does not need to operate at such a high speed, it can be replaced with an external load transistor and operated statically. In the following, a case of dynamic operation capable of high-speed operation will be exemplified.

Note that the transistor 105 in the figure is a load for the readout transistor, but unlike the figure, it may be a depletion load, and by replacing it with another switching transistor, the readout sense and buffer circuit itself can be operated dynamically. is also possible.

An important feature of this invention is that each drain Yi of each memory transistor 101 having a plurality of gates is connected to the gate of each switching transistor Sj.

Therefore, as an example of a typical implementation of the present invention, when a plurality of memory blocks shown in FIG. This can be done with just one piece.

Therefore, when the drain wiring of each memory transistor 101 having a plurality of gates and the gate wiring of each switching transistor Sn (102) are run in parallel, the degree of integration can be improved by approximately twice. It will be done.

Further, in this embodiment, the memory transistor section 106
and the peripheral circuit section are, for example, SOS (Sili-cono
Substrate separation is performed by a method such as diffusion separation using an epitaxial substrate or an epitaxial substrate, and an erase voltage of about -35 V is applied to the memory section from the substrate side.

Next, the read operation of this embodiment will be described with reference to FIG.

First, writing has already been performed on each gate portion of each memory transistor having a plurality of gates, and the threshold voltages of the gate portions at all addresses are “0” written, that is, +
It is assumed that the voltage is either 2V or more or "1" writing, that is, a voltage in the vicinity of -2V from OV.

It is also assumed that the transistors in the peripheral circuit have a dark value voltage of -IV. Here, first, the selected Xi terminal Xk(k
is an integer from 1 to m), OV is applied, and -5V is applied to unselected Xi terminals. Furthermore, if -5 V is applied to the selected terminal Y1 (1 is an integer from 1 to n) of the Yi terminal, and OV is applied to the unselected terminal, if it is under the k-th gate electrode and the first plural gates If the threshold voltage of the gate of the memory transistor with the
The read transistor is turned on. Furthermore, if the function voltage of the gate part of the memory transistor with the first plurality of gates located below the k-th gate electrode is around -2V from OV, then the voltage of the gate part of the memory transistor with the first plurality of gates The source and drain are in an OFF state. Therefore, as shown in FIG. 3, if the charging/discharging transistor 104 is temporarily turned on and the gate potential of the read transistor 103 is set to a drop potential, the read transistor 103 remains in the oH state for a long time. Moreover, in this embodiment, since there is no leakage path that would lower the gate potential of the memory transistor to below -IV, it is actually possible to read data completely statically after discharge. Next, the erasing operation of this embodiment will be explained with reference to FIG.

Erasing can be performed for each gate electrode by applying a negative voltage pulse of about -35 VIOO microseconds from the substrate side.

At this time, the wiring connected to each source and drain of each memory transistor having a plurality of gates is
It is designed to have high impedance.

Sail for the gate you want to erase, - for the gate you don't want to erase.
By applying a half-select voltage of about 15 V, so-called block erasure in gate units is possible.

Due to the erase operation, electrons are injected into the trap atoms in the gate insulator, and a channel is formed under the erased gate.

Next, the write operation will be explained with reference to FIG.

Writing is performed by applying a write voltage pulse of about 135 VIOO microseconds to the gate to which writing is desired, but at this time, -1 is applied to the drain of each memory IJ transistor having a plurality of gates to which writing is not desired.
If a half selection voltage of about 5V is applied in advance, no writing will occur.

There are two possible methods for inputting data to determine whether to write or not write: one is to input from the gate electrode side of the memory transistor, and the other is to input from the drain or source side. Either is possible. In this embodiment, the erase operation is block erase for each gate wiring, but the number of gates belonging to each block can be easily made up to about 100.
When actually integrated, it can be divided into a large number of blocks, so it can actually be used as an excellent random access nonvolatile semiconductor memory device.

So far, in describing the embodiments of the present invention, p-channel type elements have been described in detail, but it goes without saying that the present invention can also be applied to n-channel type elements.

Moreover, although only an example of operation in enhancement mode has been shown, it is natural that the present invention can also be applied to a depletion mode element by applying an appropriate electrical bias. Of course, it is also possible to create an integrated circuit that includes a mixture of transistors that operate in both enhancement and depletion modes.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an MNOS body for explaining an example of a memory transistor having a plurality of gates, which is the basis of the present invention. 1 is an n-type silicon substrate, 2 and 3 are p-type source and drain regions, 4 and 5 are source and drain electrodes, respectively, 6 is a silicon oxide film, 7 is a silicon nitride film, 8 is a gate electrode, 9 is the substrate electrode, 10
11 indicates a protective insulating film, and 11 indicates a p-type impurity layer formed on the silicon surface under the gate gap. FIG. 2 is a diagram for explaining the concept of a memory block that is employed for the first time in this invention, which is an example of the implementation of this invention. 101 is a memory transistor having a plurality of gates;
02 is a switching transistor for selecting each memory transistor 101, 103 is a readout transistor, 104 is a charge/discharge transistor provided for readout, 105 is a load transistor for the readout transistor, and 106 is between the memory section and the peripheral circuit. The substrate isolation regions of FIG. FIG. 3 is an explanatory diagram showing an example of how to apply the voltage necessary for the basic operation of the embodiment of FIG. 2. Tsutomu' figure Otsu figure Murasaki figure 3

Claims (1)

[Claims] 1 It has a plurality of gates, and its gate threshold voltage can be varied by applying a voltage between the gate electrode and the channel or between the gate electrode and the substrate, and the threshold voltage can be maintained within a certain tolerance range for a long time. In arranging a plurality of insulated gate field effect nonvolatile memory transistors, the gates at the same positions of the plurality of memory transistors having a plurality of gates are commonly connected,
Furthermore, the drain of one insulated gate field effect transistor for switching is connected to the source of each memory transistor having a plurality of gates, and the source of this switching transistor is commonly connected to the gate of the insulated gate field effect transistor for reading. Further, an insulated gate field effect transistor for charging and discharging is connected to the gate of the insulated gate field effect transistor for reading, and the drain of the memory transistor having a plurality of gates and the gate of the switching transistor are connected in common. Constructs a memory block characterized by connecting,
A nonvolatile semiconductor memory device including at least one such memory block.