JPS60234347A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve secure interlayer connection within fine interlayer connecting resin by a method wherein a projecting layer as an interlayer connecting part is provided from lower wiring side while the connecting part only is selectively exposed by means of coating an electric insulating film and anisotropic etching such as sputter etching to form an upper wiring connected to the exposed surface. CONSTITUTION:A specified P-N junction is formed on the main surface of a silicon substrate 201 and then the surface of silicon substrate 201 excluding a partial electrode opening is coated with an electric insulating film such as silicon oxide film 202. Firstly the first wiring 204 connected to the silicon substrate 201 through the electrode opening and extending on the silicon oxide film 202 as well as an interlayer connecting part 205 on the first wiring 204 are simultaneously formed. Secondly the surface of silicon substrate 201 including the first wiring 204 and the interlayer connecting part 205 is coated with another silicon oxide 206. Finally a two-layer wiring structered semiconductor device may be produced by means of forming the second wiring 207 connecting to the exposed interlayer connecting part 205 and extending on the silicon oxide film 206.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a t-pole wiring of a semiconductor device, and particularly to an electrode wiring with a hyperactive structure.

(Prior Art) FIG. 1 shows a general method as a conventional multilayer wiring technology for semiconductor devices.

FIG. 1A2 The whole surface of the semiconductor substrate 101 is covered with an electrical insulating film 102 except for some openings, and a first wiring 103 is formed to connect to the semiconductor substrate 101 through the openings. ing.

FIG. 1B: Next, an interlayer insulating film 104 is deposited on the semiconductor substrate 101 including the first wiring 103, and desired interlayer connection holes 105 are formed.

FIG. 1C: Next, a second wiring 106 is formed to connect to the first wiring 103 through the interlayer connection hole 105.

In the above conventional method, the second
Since the wiring 106 is partially extremely thin, the interlayer connection resistance is high, making it unstable and inevitable, and in extreme cases, it will break. Furthermore, due to electromigration during energization, there is a high possibility that the ultra-thin portion will break during use, and there is also a drawback in terms of reliability. The above-mentioned drawbacks of the conventional method will become fatal if the electrode wiring of semiconductor devices becomes finer in the future and, for example, the interlayer connection opening becomes about 1.5 μm or less.

(Objective of the Invention) The object of the present invention is to eliminate the drawbacks of the above-mentioned conventional methods, achieve stable interlayer connectivity in a minute interlayer connection area, and obtain a highly reliable semiconductor device. .

(Structure of the Invention) The present invention involves forming a protrusion using the lower layer wiring itself on a semiconductor substrate or a conductive material connected to the lower layer wiring, depositing an electrical insulating film, and anisotropic etching of the electrical insulating film. An interlayer insulating film is formed in this process. According to this method, only the upper plane or the periphery of the upper plane of the protrusion can be selectively exposed, and the conductive material forming the interlayer connection part can be flattened so that the interlayer insulating film is practically on the same half surface. be converted into Therefore, the upper wiring formed on the semiconductor substrate having such an interlayer connection portion can be extremely stably connected to the lower wiring without any problem.

Furthermore, even if such an interlayer connection portion is miniaturized to the limit, there is no problem in interlayer connectivity, and a high-density interconnection with a multilayer structure can be obtained, thereby providing a semiconductor device with high performance and high reliability.

(Example) In order to better understand the present invention, an example will be described using the drawings.

FIG. 2A: A desired PN junction is formed on one main surface of a semiconductor, for example, a silicon substrate 201, using conventional techniques (not shown). Next, except for some electrode openings 202, the surface of the silicon substrate 2010 is covered with an electrically insulating film such as a silicon oxide film 2.
Coat with 03. Next, the silicon oxide film 203 is connected to the silicon substrate 201 through the electrode opening 202.
A first wiring 204 extending therein and an interlayer connection portion 205 are formed on the first wiring 204.

The first wiring 204 and the interlayer connection portion 205 are made of aluminum, silicon, or tungsten.

A conductive material such as molybdenum can be used, and even if the first wiring 204 and the interlayer connection part 205 are made of the same material,
Different materials may also be used.

FIG. 2B Second, the first arrangement lIi! An interlayer insulating film, for example, a silicon oxide film 2, is formed on the surface of the silicon substrate 2010 including the interlayer connection portions 204 and 205 by bias sputtering.
06 is applied. The bias sputtering method simultaneously performs film deposition by sputtering and etching, and by appropriately selecting bias conditions, it is possible to remove the surface of the interlayer connection portion 2050, the first wiring 204, and other parts of the silicon substrate 2010. Silicon oxide film 2 on the surface
It can be coated with 06.

Regarding the bias sputtering method, see IEICE Technical Report 58D83.
I am familiar with -50.

FIG. 2C: A second wiring 20 connected to the exposed interlayer connection portion 205 and extending on the silicon oxide film 206.
7 is formed to obtain a semiconductor device with a 2/it wiring structure.

As shown in this embodiment, in the present invention, the first wiring 204 and the second wiring 1! 1liI207 is connected through the interlayer connection part 205, and the surfaces of the intercostal insulating film 206 and the interlayer connection part 205 are on the same plane. Therefore, the second wiring 207 is
A stable layer 1 connection can be obtained without becoming thinner at the interlayer connection portion. Furthermore, the structure is desirable in terms of reliability, since the factors that cause disconnection (when electricity is applied) and failures are eliminated.

In the present invention, reliable interlayer connectivity can be obtained even when the interlayer connection portions are miniaturized to the maximum extent, so it is an extremely effective technique for realizing future highly transparent multilayer wiring.

In the actual jM row described above, the interlayer connection part 205 is formed on the first wiring, but as shown in FIG. You can also do that. Furthermore, a raised ridge 208 made of a conductive material or an electrically insulating material may be provided below the first wiring 204, so that the first wiring 204 itself can be used as an interlayer connection part.

Figure 4 is! ! The film thickness of the j-tube connection part 205 is equal to the interlayer insulation ratio 2.
This is an example where the film thickness is thinner than that of 06.

A part of the surface end of the interlayer connection part 205 may be exposed as shown in FIG.

The above state can be arbitrarily formed by selecting the reliability of bias sputtering and changing the sputtering time.

The method for forming the interlayer insulating film is not based on the bias sputtering method described above, but may also use a sputter etching method such as ion milling after depositing the electrical insulating film.

(Summary of the Invention) The present invention has been described above using examples, but the essential part of the present invention is to provide a protruding layer as an interlayer connection from the lower wiring side in a multilayer wiring structure of a semiconductor device. By depositing an electrical insulating film and anisotropic etching such as sputter etching, only the interlayer connection portion is selectively exposed without using a mask, and an upper wiring connected to the exposed surface is formed.

The major effects of the present invention are that in a multilayer wiring structure, it is possible to stabilize the interlayer connectivity of upper and lower wirings, to improve the reliability of the interlayer connections, and to maintain the above two items.
If the connecting portion between the two sides can be miniaturized, a highly integrated high-performance semiconductor device can be obtained.

[Brief explanation of the drawing]

1A to 1C are sectional views of the main steps of the conventional method, and FIGS. 2A, C1, 3, and 4A and 4B are sectional views of the embodiment according to the present invention. In the figure, 101.102... Semiconductor substrate, 1
02゜202... Electrical insulating film, 103,204
...First wiring, 104,206...Interlayer insulating film, 205...Interlayer connection portion, 106,2
07...Second wiring, 0 agent patent attorney
Susumu Uchihara ρ-・'Hamata 3.・ Line 1 Figure A M7 Figure 7 C Figure Z C Figure Z β 2nd flash C

Claims (1)

[Scope of Claims] (11) A step of forming a lower wiring, a part of the lower wiring, or a protrusion of a conductive material connected to the lower wiring on the whole surface of the semiconductor substrate; depositing an electrical insulating film on the semiconductor substrate including the part, forming an interlayer insulating film by a process including sputter etching and simultaneously exposing a part of the protruding part, and connecting to the protruding part through the exposed part; (2) The process including the deposition of the electrical insulating film and the slat etching is a bias sputtering method. A method for manufacturing a semiconductor device according to claim (1).