JPS60233704A - Digital servo control circuit - Google Patents

Abstract

PURPOSE:To attain the accurate and stable servo control by measuring the width of a signal to be measured of a part to be controlled by calculating the front and rear edges of a clock pulse contained in said signal to be measured and using an obtained control signal to control the part to be controlled. CONSTITUTION:Signals Sa and Sb are supplied to a generating circuit 6 for signals to be measured from magnetic pickups 5a and 5b. Thus a signal Sx to be measured is obtained. For a clock pulse signal P supplied from a clock input terminal 7, a counter 14 counts pulses including that reaching first the back of the front edge of the signal Sx and that reaching first the back of the rear edge of the signal Sx. Then an analog output Vn is obtained in response to the count result of the counter 14. In addition, correcting analog outputs Vf and -Vr having the same and adverse polarities to the output Vn are obtained through LPFs 17 and 18 and then added together by an adder circuit 22. Thus a control signal Vx=Vn+Vf-Vr is obtained. This signal Vx is supplied to a motor 3 to keep the width of the signal Sx at the normal value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates a pulse to be measured having a width corresponding to the length of time that determines the operating state such as the rotational speed of a controlled part such as a rotating body, and The present invention relates to a digital servo control circuit that digitally measures the width of a measurement pulse to form a control signal, and controls a controlled section based on the obtained control signal.

Background Art and its Problems For example, in controlling the rotation of a rotating head of a video tape recorder, a pulse to be measured whose width changes depending on the rotational speed of a rotating head is formed, and the width of this pulse to be measured is measured digitally. , form an analog control signal by converting the obtained measurement value from digital to analog,
A digital servo control system that controls the rotational speed of the rotary head based on this analog control signal has been proposed as a system capable of performing stable servo control. In such a digital servo control system, digital measurement of the width of the pulse to be measured is performed by preparing a clock pulse signal of a constant frequency and measuring each pulse of the clock pulse signal that falls within the width of the pulse to be measured, or its leading edge. Alternatively, this can be done by counting with a counter on the trailing edge. In such a case, the count value of the counter takes only integer values, but there is an inconvenience that a counting error occurs due to this.

For example, by a counter, the leading edge (indicated by an arrow) of each pulse of the clock pulse signal Pc as shown in FIG. 3B with respect to the measured pulse Pm as shown in FIG. 3A. When the number of stitches is calculated by , the count value of the counter becomes "3" with respect to the width of the pulse to be measured Pm.

However, in this case, the actual width of the measured pulse Pm should be "3.3", and a measurement error of 0.3 will occur.

Such measurement errors cause errors in analog control signals, leading to a decrease in precision in servo control, and in the case of rotational speed control for a rotating head of a video tape recorder, causing disturbances in the rotation of the rotating head, resulting in Even though the reproduced image based on the reproduced video signal obtained from the tape recorder is accompanied by jitter, there is a certain amount of tremor. It is possible to reduce this counting error by performing counting using an extremely high frequency clock pulse signal, but increasing the frequency of the clock pulse signal requires This may result in inconveniences such as an increased burden.

OBJECTS OF THE INVENTION In view of the above, the present invention provides a method for determining the width of a signal to be measured, which has a width corresponding to the operating state of a controlled section, by changing the width of each leading edge or trailing edge of a clock pulse signal included therein. In this method, the controlled part is controlled by a control signal obtained by converting the counted value of the counter from digital to analog, and the measured value caused by the counting of the counter is measured by counting with a counter. It is an object of the present invention to provide a digital servo control circuit in which errors caused in control signals due to measurement errors with respect to signal widths are reduced by correction, and control accuracy is improved.

Summary of the Invention The digital servo control circuit according to the present invention includes:
A signal to be measured having a width corresponding to the length of time that indicates the operating state of the controlled part is formed, and a counter generates a signal after the leading edge of each leading edge or trailing edge of the clock pulse signal of a predetermined frequency. Counting is performed from the first arriving signal to the first arriving after the trailing edge of the measured signal, and an analog output corresponding to the counting result obtained by this counter is obtained. A first corrected analog output having the same polarity as the above-mentioned analog output according to the time length until the leading edge or trailing edge of the clock pulse signal arriving at the clock pulse signal arriving first after the trailing edge of the measured signal. A second output of opposite polarity to the analog output described above, depending on the time length to the leading or trailing edge of
A composite analog output obtained by adding the first and second corrected analog outputs to the above-mentioned analog output is supplied to the controlled unit as a control signal to control the controlled unit. be made into

By doing this, the error included in the analog output corresponding to the measurement result of the counter is corrected based on the measurement error for the width of the signal under measurement that occurs in the counter as a result, and the error is converted into an analog control signal. As a result, accurate and stable servo control can be performed.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of a digital servo control circuit according to the present invention, and this example is applied to a rotation control system of a rotary head of a video tape recorder. Here, a head disk 2 on which a rotating magnetic head 1 is attached is rotated by a motor 3, and control is performed so that the rotational speed of the rotating magnetic head 1 is at a predetermined speed. A small magnet 4 is fixed to the head disk 2, and the head disk 20 is placed at a position corresponding to the rotation bus of the magnet 4 as the head disk 2 rotates.
Two magnetic pickups 5a and 5b are fixed facing each other with an angular interval of 180 degrees between them with the rotation axis in between. Magnetic Pisoqua 1. From steps 5a and 5b, respectively,
The rotating magnet 4 is the magnetic pickup 5a and 5b.
Each time the signal S passes through the position, it has zero crossing points from positive to negative as shown in FIG. 2A and B.
a and a signal sb having a zero crossing point from negative to positive. Therefore, every time the head disk 2 rotates 1/2, the signals Sa and sb are obtained alternately.

Signals Sa and sb from magnetic pickups 5a and 5b
is supplied to the signal-to-be-measured generation circuit 6, where, for example, it rises at the zero-crossing point from positive to negative of the signal Sa, and at the zero-crossing point from negative to positive of the next arriving signal sb. A pulse signal Sx, which falls at the point in time and has a width T corresponding to the time from the zero-crossing point of the signal Sa to the zero-crossing point of the next signal sb, as shown in FIG. 2C,
It is formed as a signal to be measured. Therefore, this pulse signal SxO width T corresponds to the time required for 1/2 rotation of the head disk 2, and corresponds to the rotational speed of the rotary magnetic head 1.

Further, from the clock input terminal 7, a clock pulse signal P having a constant period as shown in the second diagram is supplied, and here, each leading edge of the clock pulse signal P indicated by an arrow in the second diagram corresponds to the clock timing. used as.

The above-mentioned pulse signal Sx and clock pulse signal P are
-Flip-flop circuit (hereinafter referred to as D-FF) 8 is supplied to the data terminal and clock terminal C, respectively.
At the inverted output terminal d of FF8, as shown in FIG. 2E,
From the leading edge U0 of the clock pulse signal P that arrives first after the leading edge of the pulse signal Sx, to the leading edge Un of the clock pulse signal P that arrives first after the trailing edge of the pulse signal Sx, (in the case of FIG. 2, the leading edge U0 (4th leading edge counting from the next leading edge U)
An output P1 is obtained which takes a low level l during the period up to and a high level h elsewhere, and an output PI' corresponding to the level inverted output P1 is obtained at the output terminal Q of the D-FF8. . Also, the output PI obtained at the output terminal Q of D-FF8
' and the clock pulse signal P are supplied to the data terminal and clock terminal C of the D-FF9, respectively, and the D-FF9
At the output terminal Q of , there is an output P1" as shown in FIG.
The leading edge of the clock pulse signal P that arrives first after the rising time from the low level l to the high level h and the falling time from the high level h to the low level l, that is, the next leading edge U of the leading edge Un. An output P2 is obtained which takes a high level h until n + 1 and takes a low level l at other times. And D-
The output P1 from the FF8 and the output P2 from the D-FF9 are supplied to both input terminals of the AND gate circuit 10, and from the output terminal of the AND gate circuit 1, the output P1 is output as shown in FIG. 2G. The period from when the output P2 rises from the low level l to the high level h to when the output P2 falls from the high level h to the low level l, during which both the outputs P1 and P2 are at the high level h, that is, the clock pulse signal P A pulse signal P3 is obtained which takes a high level h during the period from the leading edge Un to the leading edge U n 41.

Further, a pulse signal Sx and a clock pulse signal P from the signal generation circuit under measurement 6 are supplied to a set terminal S and a reset terminal R of a reset flip-flop circuit (hereinafter referred to as R-5FF) 11, respectively. and R-S
As shown in FIG. A pulse signal P4 having a value of +r is obtained. Further, the pulse signal Sx'' whose level is inverted by the inverter 12 and the clock pulse signal P are connected to the set terminal S and the reset terminal R of the R-S FFI 3.
from the inverted output terminal δ of the R-8FF 13 to the trailing edge of the pulse signal Sx to the leading edge Un of the clock pulse signal P that first arrives thereafter, as shown in FIG. A pulse signal P5 having a width corresponding to , and taking a negative level -r is obtained.

On the other hand, the clock pulse signal P from the clock input terminal 7
is supplied to the clock terminal C of the counter 14,
The counter 14 counts each leading edge of the clock pulse signal P, and its reset terminal R is supplied with the pulse signal P4 from the R-5FFI 1.
It is reset at the trailing edge of . Therefore, the counter 14 is reset at the leading edge U0 of the clock pulse signal P that first arrives after the leading edge of the pulse signal SxO from the signal generating circuit 6 to be measured, and the counted value is returned to zero, The leading edge of the signal P is counted sequentially from the leading edge U. The count value of this counter 14 is the latch circuit 1
5. The pulse signal P3 obtained by the AND gate circuit 10 described above is supplied to the latch circuit 15 as a launch signal, so that the count value of the counter 14 is latched at the timing of the pulse signal P3. Since the pulse signal P3 has a width corresponding to the period from the leading edge Un of the clock pulse signal P that arrives first after the trailing edge of the pulse signal SxO to the next leading edge U+n+1, the latch circuit 15
Now, the leading edge Un of the clock pulse signal P that arrives first after the trailing edge of the pulse signal Px after the counter 14 is reset.
The count value up to, ie, "n" is latched. The count value rnJ of the counter 14 latched by this latch circuit 15
is the clock pulse signal P that falls within the width of the pulse signal Sx
The period Tn from the leading edge U0 to the leading edge Un of the clock pulse signal P (Fig. 2D)
The value corresponds to

The count value of the counter 14 latched by the latch circuit 15 is supplied to the digital-analog conversion circuit 16 and converted into an analog signal, and from the digital-analog conversion circuit 16, the count value rn of the counter 14 latched is
A positive voltage Vn corresponding to J is obtained.

Further, the pulse signal P4 obtained from the output terminal Q of the above-mentioned R-3FFI 1 is supplied to the low-pass filter 17, and from the low-pass filter The period Tf until the leading edge U0 of the clock pulse signal (Fig. 2D)
A positive voltage Vf corresponding to is obtained. Furthermore, the above R
-3Fl? The pulse signal P5 obtained from the inverted output terminal δ of 13 is passed through the low-pass filter 18. and from the low-pass filter 18, the pulse signal P5 is supplied with a signal corresponding to the width of the pulse signal P5, that is, the period Tr from the trailing edge of the pulse signal SxO to the leading edge Un of the clock pulse signal P that first arrives thereafter (FIG. 2D). A negative voltage -Vr is obtained.

Then, a positive voltage Vn obtained by the digital-to-analog conversion circuit 16, a positive voltage Vf obtained by the low-pass filter F, and a negative voltage - obtained by the low-pass filter 18.
Vr is supplied to the input end of an adder circuit 22 via resistors 19, 20 and 21, respectively, and added. That is, a positive voltage Vf and a negative voltage -V are added to the positive voltage Vn, which is an analog output obtained based on the counting result of the counter 14.
Correction is applied using r as a correction analog output. As a result, an output voltage Vx is obtained at the output end of the adder circuit 22. This output voltage Vx is Vx=Vn
+Vf-Vr, and the pulse signal Sx is generated during the period Tn from the leading edge U0 to the leading edge Un of the clock pulse signal P.
The period obtained by subtracting the period Tr from the trailing edge of the pulse signal SxO to the leading edge Un of the clock pulse signal P from the period Tf from the leading edge of the clock pulse signal P to the leading edge U of the clock pulse signal P, that is, the pulse signal The period from the leading edge to the trailing edge of SxO,
Therefore, the voltage corresponds to the width T of the pulse signal Sx.

The voltage Vx corresponding to the pulse signal SxO width T obtained in this way is supplied to the motor 3 as an analog control signal via the amplifier circuit 23, and is controlled by the voltage Vx of the motor 3, whereby the rotating magnetic head The rotation speed of 1 is the pulse signal Sx obtained from the measured signal generation circuit 6.
Control is performed to maintain the congestion T at a normal value.

As described above, voltages Vf and -Vr, which are corrected analog outputs, are added to the voltage Vn, which is an analog output obtained based on the measurement value of the counter 14, which measures the width T of the pulse signal Sx, which is the signal to be measured. A voltage Vr, which is an analog control output that accurately corresponds to the pulse signal SxO width T, is obtained, and servo control of the rotational speed of the rotating magnetic heald l is performed based on this voltage Vx. It will be destroyed.

In the above example, the digital servo control circuit according to the present invention is applied to a servo control system of a rotating magnetic head of a video tape recorder.
The digital servo control circuit according to the present invention includes:
The present invention is not limited to this, and can be applied to a servo control system related to the rotation of a capstan of a video tape recorder and other various servo control systems.

Effects of the Invention As is clear from the above description, the digital servo control circuit according to the present invention digitally measures the width of the signal to be measured whose width corresponds to the operating state of the controlled section, In order to obtain a control signal for the controlled part based on the measurement result, a counter using a predetermined clock pulse signal in relation to the width of the controlled signal is used, and the counting result of this counter is also A correction corresponding to the difference between the width of the measured signal and the measurement result obtained from the counter is added to the analog output obtained by As a result,
Without increasing the frequency of the clock pulse signal used for the counting operation of the counter, the analog output corresponding to the measurement result of the counter can be included to account for the measurement error in the width of the measured signal that inevitably occurs in the counter. This error is corrected and an analog control signal is obtained. Therefore, it is possible to always obtain the correct control signal for the controlled part, and to perform accurate and stable servo control. When applied to head rotational speed control, jitter on a reproduced image can be significantly reduced in a reproduced video signal obtained from a video tape recorder.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing an example of a digital servo control circuit according to the present invention, FIG. 2 is a waveform diagram used to explain the operation of the example shown in FIG. FIG. 3 is a waveform diagram used to explain errors. In the figure, 3 is a motor, 6 is a signal generation circuit to be measured, 8 and 9
is a D-FF, 10 is an AND gate circuit, and 11 and 13 are I? -3FF, 14 is a counter, 15 is a latch circuit,
16 is a digital-to-analog conversion circuit, 17 and 18 are low-pass filters, and 22 is an adder circuit.

Claims (1)

[Claims] a signal-to-be-measured generating section that forms a signal to be measured having a width corresponding to a length of time for determining the operating state of the controlled section; a clock generating section that supplies a clock pulse signal of a predetermined frequency;
a counter that counts the leading edge or trailing edge of the clock pulse signal from the leading edge of the clock pulse signal that arrives first after the leading edge of the signal to be measured to the leading edge of the clock pulse signal that arrives first after the trailing edge of the signal to be measured; a digital-to-analog converter that generates an analog output corresponding to the counting result obtained by the counter, and from the leading edge of the signal to be measured to the leading edge or trailing edge of the clock pulse signal that arrives first after the leading edge; a first analog signal generating section that obtains a first corrected analog output having the same polarity as the analog output obtained from the digital-to-analog converting section, and which arrives first after the trailing edge of the signal under measurement; a second analog signal generating section that obtains a second corrected analog output having a polarity opposite to that of the analog output obtained from the digital-to-analog converting section, depending on the time length until the leading edge or the trailing edge of the clock pulse signal; and an analog adder that adds the first and second corrected analog outputs to the analog output obtained from the digital-to-analog converter to obtain a composite analog output;
A digital servo control circuit comprising: a control output section that supplies the synthesized analog output as a control signal to the controlled section.