JPS60232137A - Scanning converter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 1 Senboku Δ Scale Hogai! TECHNICAL FIELD This invention relates to ultrasonic scanning and, more particularly, to a digital scan conversion device for ultrasonic scanning and its interpolation method and use.

BACKGROUND OF THE INVENTION When displaying echo signals representing the amplitude of ultrasound energy returning from spaced apart paths distributed in image space on a conventional rask-scanning display, it is common to There are more pixels than image samples can be obtained. This phenomenon originates from the fundamental limitations of the speed of sound within the aircraft, as well as from the distance and time resolution of the transmitted ultrasound pulses. As a result, the image space must be reconstructed by interpolating or altering between the two image samples, ie by assigning a gray scale to the interpolated pixels.

This problem is exacerbated when using sector scanning, which increases the field of view as the ultrasound penetration depth increases. Near the crux of the sector, more image data is available for interpolation and display, while less data is available near the edges of the sector. Interpolation along a one-dimensional raster (AT R: along the
(abbreviation for raster) is one commonly used form of scan converter. The advantage of this method is low cost, but the image resolution is usually low, artifacts occur, and the images are of poor quality. UK patent application 2089537
At least four data samples along a diametrical line in A are used to interpolate the data displayed along display points located along perpendicular rows and columns. By using four data samples, the problems described above that occur in interpolation along a one-dimensional raster can be alleviated.

However, the use of digital scan converters not only allows for more accurate interpolation resulting in better resolution, but is also relatively inexpensive and simple to construct, and provides improved interpolation that is not readily available with non-digital converters. You will also get other necessary content such as: For example, digital scan converters can be used for linear or sector scanning, and can create sector image spaces of various sizes;
You can also display a portion of the image space on the entire display surface,
Scaling between the image space and the display space may also be performed, such as displaying all of the image space on a portion of the display surface. Besides interpolation errors, other deterministic errors can also be corrected, such as correction of errors related to wobbler scan heads.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an improved digital scan converter, particularly for use in ultrasound scanning systems.

The present invention also provides an improved method and apparatus for performing interpolation when displaying ultrasound images in a Lascous scanning display with improved resolution and without artifacts. The aim is to obtain images of reduced and improved quality.

The digital scan converter described above is relatively simple and inexpensive, and is capable of linear or fan scanning.

In particular, with the present invention, a direct digital conversion from rectangular to polar coordinates of each display pixel successively selected from each of the rasters of scan lines is possible, as well as their interpolation, as well as 90° or 180°. A scan conversion device can be provided for operation in a fan-shaped image space of °.

Furthermore, the device of the invention allows scale conversion between image space and display space.

Additionally, the present invention allows correction of wobbler errors when the transmit transducer is used with an ultrasound scanning system.

The present invention collects echo signals representing the amplitude of ultrasound energy returning from sampled points along a plurality of spaced paths distributed in image space to display pixels in a scanning display system. It includes an improved scan converter to convert the signal used for display as . The scan converter includes a scan data memory for storing received echo signals in a quadrant within the scan data memory, each quadrant being associated with an odd and even path and also with a combination of sample sequences. , this sample sequence is associated with sample points along the path that are spaced apart by a predetermined interval, and further includes a selected sample sequence obtained from a predetermined combination of four received signals selected from each quadrant of the scanning data memory. A circuit is included for determining a gray scale value to be assigned to a display pixel.

In a preferred embodiment, at least one pair of scan data memories is used. The received echo signals from the current scan of the image space are stored in one of the scan data memories, while the received echo signals obtained from the previous scan are stored in the other scan data memory and from the current scan. combined to determine a value for interpolating the asynchronous gray scale value from the stored value of the received echo signal.

The circuit described above includes a signal generation circuit that generates a pair of mixed signals associated with a selected display pixel. A memory address circuit responsive to the integer portion of the mixed signal generates an address for each quadrant of the four received echo signals to be combined.

The initially mentioned circuit for determining the gray scale value includes a filter circuit for combining the four received echo signals addressed by the address circuit and the fractional part of the mixed number pair.

The filter circuit comprises a first intermediate fraction of a mixed signal of a pair of received echo signals present on a first side of a selected display pixel; producing a second intermediate gray scale value from the received pair of echo signals on a second side opposite the first side of said selected display pixel and said first fractional portion; It includes circuitry for creating a scale value and creating a final gray scale value from the second and second intermediate gray scale values and the remaining fractional portion.

The scan converter of the present invention can operate in either linear scan mode or sector scan mode.

A circuit that generates a pair of mixed numbers in association with a selected display pixel, a circuit that generates a mixed rectangular matrix for linear scan mode, and a mixed polar format signal for fan scan mode. Contains circuits. A switching circuit selects either a mixed rectangular signal or a mixed polar signal to determine which display pixel is selected and which gray scale value is assigned, depending on which scan mode is being used. Output.

This scan converter also provides a hose error (hos) error when an ultrasound device and an emitting transducer scan head are used.
e error).

Additionally, the scan converter includes circuitry for converting scale between image space and display space, allowing operation in either a 90 DEG range or a 180 DEG range sector.

The coordinate transformation circuit used as a scan conversion device when used in fan scan mode includes circuitry that generates Cartesian coordinate X and y signals associated with the position of a display pixel in the display space, and and circuitry for converting the X and Y signals into polar coordinate signals associated with the position of the display pixel at.

The conversion circuitry further comprises a circuitry for folding the sector image space into one smaller subsection, a circuitry for determining the angular displacement of a display pixel within this subsection, and a polar signal pair angular signal associated with the display pixel. and a circuit that expands the sector image space to determine .

In a preferred embodiment, the conversion circuit includes circuitry for generating a blind signal equal to the value of the greater portion of the absolute values of the X and y signals.

In determining the diametrical and angular signals of the polar signal pair, this conversion circuit uses a circuit that produces an output signal proportional to wlv. W is a multi-bit number that has more bits than the signal 1/v if the circuit creating l/v uses fewer bits for 1/v than are included in W. Furthermore, a circuit is provided for selecting a subset number of bits equal to the number of bits in l/v. The selected subset varies depending on the size of V.

The conversion circuit includes a circuit that outputs a diametrical signal proportional to y/cos θ (cos θ is obtained from the X and y signals). The circuit that outputs the diametrical signal is y and [(1/c
osθ)-1] includes an arithmetic circuit that performs the calculation, and a circuit that adds y to the output of the arithmetic circuit.

In the figure, a block diagram of an ultrasonic scanning system is shown as 10G, and the system stores a scanning data memory 12 under the control of a memory controller 130.
an ultrasound scanner 11O for creating a sample of ultrasound echoes to be stored within 0 and a scan for storing data used to assign a grayscale value to a selected display pixel of display device 150; An address generator 140 associated with a memory controller that generates addresses for data stored in the data memory and a two-scan data memory and address generator 14
a filter 160 for interpolating by giving a gray scale value to a selected display pixel based on the output signal from 0;
video output circuit 170 for interfacing with
: controls the raster scanning of the display device 150 and the address generator 140 . Scanning data memory 120° display device 150
and a raster scanning signal generator 180 that prepares a control signal to the address generator 140 for synchronous operation of the filter 160 and the address generator 140.

The basic timing of the system 100 of this invention is line 1
With a 12.4 MHz clock pulse obtained at 90.

Scanner 110 is conventional and includes an ultrasound transmitter that transmits ultrasound pulses along a plurality of spaced apart paths to an image medium, such as human tissue.

The scanner 110 and the transmitter transmit data along parallel paths separated by a predetermined distance (in the case of linear scanning), or along paths separated by a predetermined angle from the same origin, that is, the pole of the sector to be scanned. It is designed to transmit pulses along the line.

As the pulse travels along a particular path, it encounters tissue boundaries and discontinuities, and echoes are reflected along the predetermined path and detected by the transducer. After a pulse is transmitted, the transmitter's electrical pulses can be sampled at a predetermined rate to obtain multiple data samples generated for each path. The time elapsed between the transmission of one pulse and each sample of one echo determines the penetration depth of the source of the echo, such as a tissue boundary or other discontinuity, into the object being examined. It is related to

Scan Data Memo January 20th is 2 pages of high speed static RA
M, and each member can hold 6 bits of data in 128 rows and 512 columns. The ultrasound echo signals received by the scanner 110 within the current image space scan period are stored in one page of the memory 120, while the data stored in other pages from the previous image space scan are Used for display purposes. Writing data to one page is done independently of reading data from other pages for display. Therefore, this device does not need to operate synchronously with the timing of scanner 110. When a decision is made to move from one page to another for display, the shift occurs regardless of the position of the transducer beam.

Referring to FIG. 2, a conventional method of interpolating display points along a raster scan line using a pair of sample points is illustrated in FIG. FIG. 2 shows the origin 0 and two separate paths or diameters 0θ and 0θn+1 of the sector scan along which the ultrasound pulse travels. The returned echoes are 0θ, 12-16 for each diameter direction for +1, 0
For θ□1□, samples are periodically sampled along each point 11-7. Paired points 6, 15, 8, 14.
9.13. and 10°12 lie along common arcs such as arc 210 (R) for pair point 10.12, arc 211 ('Rn+, ) for pair 9.13, and arc 212 for pair point 6.15, respectively. are doing. Raster scan lines CD and EF are shown overlapping on the sector scan diagram. Points l, 2°3.4 and 5 are display points that require interpolation to display within the display space. In the prior art, sample points 12 and 6 are point 1-
It was used for interpolation of 5. However, points 12 and 6 are acoustically weakly related relative to 1-5 because points 12 and 6 are sampled by ultrasound transmitted in separate phases and are in separate lateral frequency bands. There is only one. Using these two points for interpolation of other points, we get
The reconstructed image will have the problem of resolution discontinuity and will also suffer from artifacts and degradation with poor image quality.

In a preferred embodiment of the invention, instead of using points 12 and 6 to interpolate filled data point 1, intermediate data points 17 and 18 are interpolated first, and the value of data point l is Calculated using 17 and 18. Point 1
The position of point 1 relative to 2, 10.9 and 13 is used in the calculation. The values labeled S and T as shown in FIG. 2 are used for calculations. UK patent application 2089537A
shows how the various sample points are combined to interpolate the value 1, and is explained below how this is done in the preferred embodiment of the invention.

Although FIG. 2 shows only sector scans, the same applies to linear scans.

Referring again to FIG. 1, display 150 is a commonly used Lasque scan CRT display, such as the American black and white television format, R8-L170A NTSC standard broadcast video format. Under the control of raster scanning signals from signal generator 180, an electron beam is swept horizontally across the face of the CRT in display 150 at a rate of 15,750 swivels/second, while 60. It is swept from the top of the screen to the bottom at a rate of Hz. There are 525 horizontal sweeps in each video frame, with each scan line or sweep completed in 63.492 microseconds. Approximately 55 microseconds per scan line is allowed for video display, and the electron beam is allowed a retrace period of 8 microseconds before making a new trajectory.

FIG. 4 shows the timing of the horizontal sweep and retrace period. The ultrasound system 100 is divided into 768 display pixels, and within the video portion there are 640 display pixels.
display pixels are created. These display pixels are 63.492 microseconds per scan line or 7 pixel per scan line.
It is made using a 12.4-MHz clock so that it has 68 pixels. In the preferred embodiment of the invention, the actual display space is 640 and 480 per frame for 525 scan lines to yield a display pixel matrix of 512 and 480 display pixels.
Only 1 pixels are used.

5 and 6, the display space of display 150 of FIG. 1 is shown as display space 500, which is a 51'2 x 480 display space shown as columns 0-511 and rows 0-511. It consists of a pixel matrix. When scanning from left to right and top to bottom, pixel 502 in FIG. 5 is located at column 0, row 0. However, in the preferred embodiment, the coordinates of each display pixel in display space 500 are transformed to X and X coordinates in intermediate data space 520.

For example, display pixel 502 at position 0.0 is transformed to a coordinate position of ~256 within display space 520, while display pixel 504 at coordinate 511.0 is transformed into display space 520.
is converted so that it is at the coordinate position 255.0.

The circuit for performing this conversion is shown in Figure 6 as a whole at 60.
It is shown as 0. Although only the transformation circuit for one coordinate is shown, the same circuit is used for the second coordinate. The first value of the coordinate, −256, is loaded into register 602 and the coordinate Δ value, e.g., 1yO, is loaded into register 604. The output of register 604 is loaded into the input terminal of adder circuit 606, whose output is connected to six inputs of multiplexer 608. The output of register 602 is provided to the B input terminal of multiplexer 60g. The output of multiplexer 608 is sent to register 6.
10. The output of register 610 is a 20-bit coordinate in intermediate data space 520. The output of register 61O is loaded into the B input terminal of adder circuit 606. Register 610 is clocked by a reference 12.4 MHz clock.

A reset signal is output by the signal generator 180 at the start of each raster scan line of the display space by the display device 150 and is transferred via line 614 to the multiplexer 608.
The B input is selected to output from to register 610. The input terminals are then selected by multiplexer 608 for output with the clock until the end of the scan line. The Δ values in register 604 after the first pixel of a scan line are added sequentially and continuously across the scan line to provide the X coordinate pixels. Regarding the X coordinate, the reset signal is the same as above except that the reset signal is generated at the beginning or end of each frame rather than every scan line.

The relationship of the image space, ie the actual area inspected by the ultrasound beam, to the intermediate data space is illustrated by a 90° sector image space 520. This sector image space is shown superimposed on orthogonal intermediate data space 520. The sector-shaped pole 524 has X=0. It is placed at the position y=0, and the edge portion 526 of the sector is placed at the position x=0. y=
5] It is placed in 1.

The axis of the sector pole is the y-axis of data space 520 (x=0)
The positive pole angle θ is measured counterclockwise from the y-axis. Typically, a complete linear scan image space exists between X values of 0 and 120 and y values of 0 and 511.

If we want to display the entire image space within the entire display space, the initial X value is -256, the XΔΔ value is 0, the initial y value is Ol, and the initial yΔ value is 511/479. However, there are multiple initial values that can be selected, and there may also be multiple Δ values. By appropriate selection of the initial value and the Δ value, the circuit 600 can provide a scale between the image space and the display space, such that all images are 1/4 of the display screen (e.g., the initial value of (by choosing the initial values of y to be -256 and 0 and the Δ value to be 2), or (by choosing the starting values of By taking an arbitrary value between them, 1/64th of the entire image can be displayed on the entire screen.

In the preferred embodiment, approximately 120 separate paths are formed by the ultrasound pulse, and 512
samples are taken.

In this way, the image space can obtain data samples of 120 rows and 512 columns, all of which can be stored in a special way on one page of the scan data memo. Figure 5 shows that each member of the scan data memo is divided into four labeled and independently addressed quadrants; even columns/even rows (ER,
EC) 550: Even columns, even rows (ER, QC) 552;
Odd columns, even rows (OR, 'EC) 552. and odd columns, odd rows (OR1QC) 556. Each quadrant is six Hitachi 16Kx I CMOS static RAMs (type HM6167HP-55), each 16Kxl RAM arranged as a matrix of 256 columns and 64 rows. Six are used to store one word of 6 bits for each RAM address location (for each data sample).

Each of the 120 separate routes is assigned a separate line or row number from 0 to 119, which are sequentially numbered to represent adjacent routes. Similarly, data sample columns are assigned numbers from 0 to 511. Even numbered paths are in memory quadrant 55.
Rows of data are stored in quadrants 0 and 540, while odd numbered routes are stored in quadrants 552 and 556. In each row of memory, whether odd or even, even samples of data are stored in quadrants 550 and 552, and columns of odd samples are stored in quadrants 554 and 556. Control of the addressing of each quadrant of memory is used in conjunction with a modulo-two counting circuit to interpolate the even/odd memory segmentation into four quadrants.

FIG. 6 is a diagram illustrating a portion of address generator 140 of FIG. This output address generator 140 produces a 20 bit mixed X and y coordinate number in intermediate data space 520. Each X and y coordinate pair is associated with a display pixel within display space 500 for display device 150. This mixed number indicates that they have a multi-bit integer part and a multi-bit fractional part.

The X and y coordinates described above for fan image scanning are used for scan conversion circuit 700 (FIG. 7).

The scan conversion circuit 700 extracts the X and y coordinate numbers of the multiple bits and converts the coordinate numbers into r and θ of mixed polymorphic bits in polar coordinate format. This conversion is performed by circuit 700 in real time at the pixel clock rate for successively selected display pixels along the raster scan line for the entire frame. The integer parts of r and θ for each display pixel in real time are stored in the memory address circuit 9.
00, the memory address circuit 900 is part of the memory control circuit 130 and is used to address the scan data memory 12 which is the adjacent selected display pixel shown in FIG.
Four addresses of four sample image points in G are generated simultaneously. These four sample data are line 122
is sent to filter circuit 160 via. r and θ
The fractional portion of is sent via line 162 to filter 160 and combined with the four sample data to generate an interpolated grayscale value for the selected display pixel in a predetermined manner.

For linear scans and sector scans, the integer portions of X and y are utilized directly by the memory addressing circuitry and the fractional portions are used in filter 160 without further conversion by circuitry 700. The fractional portions of X and y are used to determine the display pixel location with respect to the location of the four sample data in image space.

To convert the X and y coordinates to r and qθ, first use ABS
It is necessary to first prepare a signal equal to /V.

This mixed signal representing θ and r is expressed by the following equation; θ-jan'-' (A B S X/y) r=y/c
Since the osθ display space 500 is a matrix of 512 rows and 512 columns of display pixels, X and Y must contain at least 9 integer bits to identify each display pixel. In order to enable scale conversion between image space and display space by the circuit illustrated by FIG. 6, and because conversion to r and θ is necessary,
The conversion of the display space coordinates of each display pixel to intermediate data space X and y coordinates, as well as to polar coordinates, if necessary, will normally include a fractional portion without generating integer coordinates. Thus, the X and y coordinate signals contain several bits to represent the fractional part. In a preferred embodiment, the 12-bit number y is
/y, r, and θ, while 20
A bit of the X signal is used. A in real time
Ingenious circuit arrangements are used to prepare large multi-bit signals such as BSx/y, r, and θ.

Referring to FIG.
Reference table (lookup table) through LIT
A circuit 704 is provided. This 12-bit y-coordinate signal is also provided to comparison circuit 708 via bus 700. Bits 0 and -8 represent the integer part of the y coordinate, while bits -1 to -3 represent the fractional part. A 20-bit X coordinate signal is sent via bus 710.

A signal is provided to a circuit 712 which generates a signal equal to the absolute value of ABSx. Since X can be either positive or negative, X can be in two's complement form and bit 9 is used in connection therewith.

Circuit 712 outputs a 19-bit parallel signal representing ABSx, and this output is sent to comparator circuit 708 and parallel bus 71.
6 to the barrel shifter circuit 714.

LUT circuit 704 takes the 12-bit y-coordinate input signal, inverts it, and provides a 12-bit output signal 1/y via bus 720 to one input terminal of multiplier circuit 722. Based on this value of y, the LUT circuit 70
4 provides four bit signals to barrel softer circuit 714 via bus 724.

In response to the 4-bit signal, circuit 714 transfers 12 bits of the l·9-bit ABS-x input signal to bus 726.
The signal is supplied to a multiplier circuit 722 via the multiplier circuit 722 to perform division by l/y.

In the 90° sector 522 shown in FIG. 5, the border of the sector is θ
−±45° or indicated by the line X=Y.

When y is the minimum, the lower 12 digits of X and 12 ABSX are selected and the l/y operation is calculated in circuit 714 in response to a 4-bit signal presented on bus 724.

In the middle range of y, the middle 12 bits of ABSx are selected by circuit 714, while at the highest value of y, the range of Again selected by circuit 714. Multiplier circuit 722 connects line 728 whenever A B S x/y is greater than or equal to l.
A high level X/yOVF signal is generated.

Multiplier circuit 722 supplies a 12-bit ABS x/y signal having a 9-bit integer part and a 3-bit fractional part to LUT circuit 730.
performs the determination of the r and θ signals. First r= y/c
After checking osθ, the LUT circuit 730 uses the function 1/co
12 regarding s[jan'(A B S X/Y)
Provides a bit signal. In addition, the LUT circuit 730 has 12
Outputs a 12-bit signal for each of the 212 possible input values of the ABS x/y signal. 3 AM2
A 7541A device is used for this purpose.

θ takes a value from 0 to 45° and 1/cos θ is 1/cos
(0°) and 1/cos (45°). In other words, in binary numbers, 1000 and 1.0[110
10'1000001] takes a value of 0. By accepting the binary number 1/cos θ, the 12 bits in the bracket shown above are changed, and LUT circuit 730 produces only the fractional portion of i/cos θ. In this way, LUT circuit 730 yields [(1/cosθ)-1]. y/cosθ is y(1+z) where z-[(1
/cosθ)-1]. In this way, LUT
The 12-bit output signal of circuit 730 is provided via switch 740 to multiplier 742 where it is multiplied with the 12-bit y signal to form yz. The output of multiplier 742 is the 12-bit y signal sent from bus 746.
It is supplied to the adder circuit 744 together with the signal y + yz
Create = y/cosθ. The output of summing circuit 744 is a 16-bit signal representing the diametric distance r of the selected display pixel with intermediate data space coordinates xy from the origin 0 of sector 522. Store only the remaining 12 bits of 1/cos θ when θ varies between θ° and ±45°, and use the formula y=
By using y+yz, the 12-bit calculation of y/cos θ can be easily completed.

In order to make a diametrical straight line of θ−±45° to sharply determine the fan shape 522, ABSx≧y, that is, θ
The x/yOV F signal from LUT circuit 722, representing -±45°, is transferred to switch 740, and switch 744 is responsive to the x/yOV F signal, regardless of the value of Z from LUT circuit 730. Su1/cos45
produces an output signal equal to a fractional part of °.

The 16-bit number representing the diameter r is 16 representing the value of y.
It is sent along with the bit from register 610 to switch 748. (The y number signal from register 610 is 20 bits.) If the scan mode is linear, switch 748 selects the L in/Sector signal 75.
2 provides a 15-bit column output from the y input. If the scan mode is polar coordinate format, switch 74
8 provides a 15-bit column signal derived from the 16-hit diameter signal r from summing circuit 744 in response to signal 752. It represents the number of sample columns along the path that are separated by a predetermined interval from this 15-bit column signal.

12-bit A13 from multiplier circuit 722
The S x/y output signal is also provided to LUT circuit 732 .

θ is calculated from A B S x/y by the function tan-' (A B
S y,/y−θ).

Each θ value must be assigned to one mixed line number associated with one of the +20 previously defined scan paths covering the fan-shaped image space. (During scanning of the fan-shaped image space by the ultrasound scanner 110, there are 120 angularly separated paths in the fan-shaped image space.) LUT circuit 732
provides a 16-bit output signal containing a 9-bit integer portion and a 7-bit fractional portion in response to A B S x/y.

The output signal of this LUT circuit 732 is obtained by combining the calculation of θ and the assignment of the number of the mixed single line assigned to this θ.

In the preferred embodiment, the +20 paths covering the sector between -45° and +45° are assigned line numbers 0 to 119, with line number O being -45° and line number +19 being +45°. Corresponds to °. jan'(A
Each θ obtained from B S x/y) is the line number - (θ) (I 19/9o) + t l'9. /
2 is converted into a line number by recognizing it.

LUT 732 is programmed to provide the line numbers described above in response to ABSX#. Thus θ=45° provides line number 119 and θ=06 yields line number 119/2=59.5.

Since LUT circuit 732 responds to ABSX#,
There is no circuit within LUT circuit 732 to calculate the line number for negative θ. However, the output of LUT circuit 732 is sent directly to switch 757 via switch 756 and to summing circuit 758. The other input terminal of adder circuit 758 receives the 16-bit signal for line number 119. When X is negative, θ is negative, and a positive signal SIGNXDLY is applied to switch circuit 757 to select the output of circuit 758 as the output for switch 7.
supplied to The LUT circuit 758 is connected to the LUT from l'19.
Subtract the output of circuit 732. In this way, θ−45
For °, LUT circuit 732 provides a 16-bit signal equal to 119, which is subtracted from 119 by circuit 758 to 0.
occurs.

When X is positive, switch 757 switches to LUT circuit 732
output directly via switch 756.

In summary, LUT circuit 732, adder circuit 758, and switch 757 calculate the following formula: %(0) for 5°≦θ≦0°).

The 16-bit signal for the number 119 is sent to switch 75.
6 is output as the second signal. This is 1/cos(
45°) to switch 740 serves a similar purpose. Switch 756 connects circuit 722 to create a sharp line along diameter line θ-±45° when X-y.
In response to the x/y OVF signal from the line number 119, switch the output to zero regardless of the output of the LUT circuit 732.

16 representing the wire number equal to θ from the switch circuit 757
The bit signal is provided to adder circuit 760.

A signal from the LUT circuit 762 is sent to the other input terminal of the adder circuit 760. The output signal of LUT circuit 762 is combined with the output signal of switch 757 in circuit 760. 1. , the output of the U T circuit 762 is a correction factor that is added for line number calculations when the outgoing wobbler scan head is used with the scanner 110.

The necessary modifications when using an oscillating wobbler type scan head (known as a hose collection) are illustrated with reference to FIG. As scanhead 802 rotates laterally in the direction of the curved line and along arrow 804, scanhead 802 delivers a series of pulses directed along a transmission path defined by axis 806 of the scanhead. The scan head is equipped with an encoder that delivers a digital signal representing the rotation angle of the shaft at the time of transmission of a pulse, measured from an arbitrary starting point, such as 0°. Before the next pulse is sent, the current of the transmitted pulse travels through the image medium until it encounters a discontinuity that generates an echo that returns along the original transmission path. . However, by the time the echo returns to the scanhead, the scanhead has rotated 0 degrees from its original transmission position. This amount of Δθ is greater than for echoes returning from larger diameter sections.

The receive aperture is moved away from the transmit aperture each time the scanhead output is sampled to generate a received echo signal. As a result, positional errors occur. This error is undesirable to the physician because it changes the measurements taken from the image. Since the scan head swings in opposite directions in each frame, this error changes the sign from one frame to the next, resulting in an unmistakable lateral flicker in the image.

For a given diameter, the Δθ error is proportional to the angular velocity ω of the scan head and inversely proportional to the velocity V of the ultrasound in the imaging medium. LOT circuit 762 outputs the 16-bit diameter signal r from circuit 744 and a fixed signal proportional to ω/■.

Depending on r, LOT circuit 762 supplies adder circuit 760 with a pose correction number, ie, a number equal to Δθ/2, from the output signal of circuit 757 when the scan head is rotating in the direction of increasing line number. It operates to subtract, and when the scan head is rotating in a direction in which the line number decreases, it operates to add to the output of the circuit 757. Δθ/2 is used instead of 80 because all the apertures are between half the length between the transmit and receive apertures.

The output of circuit 760 is provided to switch 764 as a 16-bit signal along with the X signal obtained directly from X register 610. In response to the L I N /5ector signal, switch 764 selects either the output (line number) of circuit 760 or output X, which is defined as the row signal. The row signal consists of 14 bits with a 7 bit integer part and an 8 bit fractional part.

The integer portion of the row signal (bits 0 to 6) from switch 764 and the integer portion of bits 0 to 8 of the column signal from switch 748 are routed to memory controller 1 via bus 132.
30, while the fractional bits of the row and column signals are provided via bus 134 to filter circuit 160. Before discussing filter circuit 160, a detailed description of address portion 900 in FIG. 9 of memory controller 130 regarding addressing of received echo signals will be provided.

Referring to FIGS. 2, 3, and 9, switch 748
The integer portion of the mixed signal obtained by and 764 is one of the four closest data samples obtained at the location of the selected display pixel in image space.
The location of the acquired data samples in image space (eg, members of a path that are distant from each other and the number of a sample sequence along that path) is identified. The position of the display pixel in the display space is converted into a pair of mixed X and Y signals sequentially by the circuit shown in FIG. 6, and then into a pair of mixed signals in polar coordinates by the circuit of FIG. is converted to The four acquired data samples closest to the display pixel define an area in the image space in which the selected display pixel is located. See Figure 2.

The position of the resulting data sample determined by the integer portion of the mixed signal is on either side of the selected display pixel associated with a particular sample column or column (corresponding to a column in the depth scanning data memory 120). given by the intercept of one of the predetermined spaced paths occurring on either side of the selected display pixel (corresponding to a row of scan data memory 120) with one of the lines. Particularly in polar coordinates, if the position of the obtained data sample determined by the integer part is the coordinate name Rn, O
If defined by n, the remaining three positions of the four obtained nearest data samples are Rn,on+1;R
n+1. θn: and Rn+1. This is the position 1-) of θn+1. See Figure 2. The four closest acquired data samples are located at a combination of even and odd row and column addresses in scan data memory 120.

In accordance with the method of storing the resulting data samples from sequential scan lines in columns and rows 552, 554 and 556 of the memory quadrants as previously described, the data is stored along the rows in the memory according to the columns. Number O
Even columns of data starting at column positions are stored in sequential addresses located in the even column quadrant, while data in odd columns starting at column positions are stored sequentially in addresses located in the odd column quadrant. For example, column 0.2.4... is quadrant 5
50 or 552, -blade row 13.5 is stored in the odd row quadrant 554,5.
56 at address 0.1.2. The same goes for even and odd columns. A memory address circuit 900 is provided to access the four data samples obtained closest to the display point from the four quadrants. The memory address circuit 900 shown in FIG. 9 includes even column and odd column address portions 902 and even and odd row address circuits 904. Circuit 902 includes a first group of adder circuits 910, 912 and 914 which are coupled in a predetermined manner to generate an 8-bit even column address. The least significant 4 pits of the integer sequence number, that is, the lower 4 digits, are added to the adder 91.
The four bits important for one method are fed to the A input terminal of adder 912, and the least significant bit, or least significant bit, is fed to the input terminal of adder 914. . This least significant bit is added to the adder 9
12 BO input terminals. The carry one terminal (CI) of the adder circuit 910 is grounded, the carry output terminal (Co) of the adder circuit 910 is connected to the ci terminal of the adder circuit 912, and the CO of the adder circuit 912 is connected to the 01 terminal of the adder circuit 914.

The circuit 902 further includes a second adder circuit group 916, 91
8 and 920 whose circuits generate odd column addresses in the same manner as above except that the least significant bit of the column integer input signal is inverted by inverter 922 and provided to the BO circuit of adder circuit 916. connected like this.

Circuit 902 described above shows that the following even and odd addresses are created in response to the integer portion of column signal n from switch 748: even column address n when column integer input signal n is even;
/2: When the column integer input signal n is an odd number, the even column address (
n+1)/2・If column integer input signal n is even number, odd column address n
/2; When the column integer input signal n is an odd number, the odd column address (
n-1)/2 This output signal is of course available in binary form.

The particular column identified by the integer part of the mixed number column of either switch 748 or 764 is the two columns 7 and 7 in which the four acquired data samples closest to the display pixel location are to be selected. For example, show column 7 than it should be 8. Column 7 is stored in quadrants 554 or 556 in such a way that the columns are stored at sequential addresses in the memory quadrants of the odd and even columns.
In either quadrant of (J) is the one found at address 3. That is, for an integer number of odd columns, the formula for odd addresses is (n-1>/2, which means For even addresses from circuit 902, the even columns are stored sequentially within the even quadrants, so the equation for even addresses is: for column 7, the even column addresses are ( n+1)/2=4. Thus, circuit 902 provides the correct sequential address in the even and odd column quadrants for the column identified by the integer part of the column's mixed number. act.

Circuit 904 is a combination of adder circuits that generate even and odd row addresses, which are coupled in a manner similar to circuit 902. The even column address signal from circuit 902 is in quadrant 5.
50 and 552, the odd column address signals from circuit 902 are transferred to quadrants 554 and 556, while the even row address signals from circuit 904 are routed to quadrants 550 and 554.
and odd row address signals from circuit 904 are transferred to quadrants 552 and 556.

The 7-bit fractional portion of the mixed column signal from switch 748 and the 7-bit fractional portion of the mixed row signal from switch 764 are transferred via filter 62 to filter circuit 960. There are also four 6-bit words f(Rn, θn+l"f(Rn+1'θn+1) representing the values of the four most recent data samples obtained for the display pixel.
;f(Rn, on);f(Rn on -1, θ□) is bus 1
22 and is transferred to the filter circuit 160. Filter circuit 160 combines the four resulting data samples with the fractional column and row number signals, denoted S and T, to obtain an interpolated gray scale value at the display pixel of interest. This is a well-known integrated circuit that calculates the algorithm.

f = f (R, θ ) + S [f (Rn + 1.0n + 1)
-1n n+1 f(Rnlθn4-1)] f2= r(Rn,on)+S [f(R1+1.O
n) -f(Rn+On)kof(Rn+S, θ, +T)-f2+T(fl-f2
) The above three equations show that each equation is executed in the same basic way. Figure 1O shows the first equation f
, G indicate the circuit lines to be executed. Other circuits are not shown as they are the same as above.

With reference to FIG. 1O, the scanning line θ at arcs Rn and Rn+1
The resulting data sample, located at n+l, is provided as a 6-bit word from bus 122 to subtraction circuit 1002. The subtraction circuit 1002 has f(Rn+□
, on+1) is subtracted from f(Rn, θn+,), and this 6-bit output is output to multiplier 1004 via bus 1006. Six of the seven bits of the fractional part of the column integer part from switch 748 are transferred from bus 162 to multigraph 1004'\bus io.
Transferred through og. The least significant bit of these 7 bits is used for rotation instruction. multiplier 10
04 is S[f(Rn+ 1'θn+ 1
) f(Rn, θn+1)].

The output of the multiplier 1004 is sent to the adder circuit 1010 as f
(Rn, on+1).

If fl, f2. If f(Rn+S, θ, 10T), then the output of multiplier 101O is performed similarly except for the function n of f(R+S, θ 10T), where the fractional part of the row mix word from switch 764 is Instead of S, T is used in the multiplier, and functions f and f2 are used as other signal inputs instead of the data signal obtained from the memory 120.

The above algorithm for combining the four obtained data samples is only one for combining the obtained data samples to obtain the gray scale value for the display pixel.
There is no single method. The intermediate interpolated values f, and f2 are used to obtain the final interpolated value between the distal paths in one display pixel before the first disparate path on one side of the display pixel. Instead of first finding a first intermediate interpolated value f1 along the displayed pixel and then finding a second intermediate interpolated value f, along a second path away on the opposite side of the displayed pixel. Interpolation can also be performed by creating intermediate interpolated values along one arc on one side of the display pixel and then along a second arc on the other side of the display pixel.

The intermediate interpolated values found on the two arcs can then be interpolated diametrically to obtain the final interpolated value. Using the latter method, the circuit shown in FIG.
The following algorithm f1- "(Rn, On) 10T [f(R,, On+
1)-f(Rnl On)] f2-f(Rn1.on)
+T[r(Rn+1.0□+1)-f(R,+1.θ.

)] f(R+S, θ 1T ) 2f 2 +T (rl−
The circuit shown in FIG. 11 can be similarly used by organizing the input signals according to f2)Rn.

Referring again to FIG. 7, multiplier circuit 722 always uses the A B S x/
y output signal. The configuration of the multiplier circuit 722 and the programming of the UT circuit 732 is based on a 90 degree fan scan with θ varying between -45 degrees and +45 degrees. FIG. 11 shows another embodiment that performs a 180° sector scan. This circuit is shown at 1100.

In a polar coordinate meter such as space 520 shown in FIG.
In a polar coordinate meter where measurements are taken as positive counterclockwise from 16, the 180° sector is divided into four 45° sectors, i.e. -45° from -90° (in the negative direction relative to the axis).
5° part; -45° to oQ part: +45 from Oo
It is useful to know that it consists of a 0° portion and a +45° to +90° portion (the portion along the positive X axis).

Using the ABSX signal and W greater than ABSX and y, v is AB! LUT store value tan-' (w/v
), all that is needed is obtained by determining the angular displacement within a 45° subsector from the formula tan-' (v/v). In this manner, a complete 180° sector is folded into one subsector to determine the angular displacement for a selected display pixel within a single subsector. Furthermore, ABSX is 19
It should be noted that y is greater in the range 0'' to -45° and in the range 45° to 90°.

Referring to FIG. 11, a 16-bit ABSX signal and a 16-bit y signal are sent to a comparison circuit 1104 and switch circuits 1106 and 110 via buses 1102 and 1103, respectively.
8. The ABSx and y signals are generated in a manner similar to that described in the description of FIG. Comparison circuit 110
4 outputs a high signal if the ABSx signal is larger than the y signal, and otherwise outputs a low signal.

Switch 1106 transfers the lower two input signals of ABSX or y in response to the ABSX≧y signal from circuit 1104. This output is indicated by ■ and is transferred via bus 1110 to LUT circuit 1112 which has the same function as LUT circuit 704 shown in FIG. LUT circuit +112
supplies a 12-bit signal 1/v to multiplier 1114. At the same time, LUT circuit 1112 provides a 4-bit signal on line 1116 to barrel knot register 1118, which functions similarly to circuit 714 of FIG. Switch 1108 provides a signal greater than the ABSX and X signals to shift register 1118 in response to ABSx≧y. In response to the 4-bit signal on line 1116, barrel knot register 118 selects the appropriate subset of the 12-bit input signal for transmission as signal W.

This W signal is transmitted to the multiplier 11 via the bus 1120.
14, and the signal W is multiplied by this multiplier to calculate W/V.

w/v is transferred to LUT circuit 1124 via bus 1122.

LUT circuit 1124 is similar to LUT circuits 730 and 73 in FIG.
It may consist of two separate circuits for performing two functions, or conversely it may be combined into a single LOT, such as the LUT circuit 1124 shown in FIG. One output of LUT circuit 1124 has a factor of 12 hits, Z is used to calculate the mixed diametrical signal, and r is used in a manner similar to that shown in FIG. The LUT circuit 1124 outputs a 2-bit angular displacement signal that varies between 0 and 45 degrees and is equal to jan-'(w/v).

For larger ABS, x or y, by substituting the variable ■ for values smaller than W, the above angular displacement signal can be determined by the angle at which the display pixel is located at any time, 180°.
is always positive regardless of the 45° subsector within all sectors of . Therefore, this circuit needs to be assigned line numbers for angular displacements that take this into account so as not to fold sectors.

The angular displacement signal from LUT circuit 1124 is connected to bus 1126.
through bus 1128 with a signal equal to constant A to multiplier 1130. The constant A is found by dividing the number of spaced apart paths that occur within the sector divided by the sector size. The output of multiplier 1130 is
(θ)(A) represents the number of lines contained within the angular displacement signal equal to tan'(w/v) provided by L U T 1124 within a sector of .

In a preferred embodiment, the number of sector scan lines is preferably zero at one 90° sector for a 180° sector scan range. As the sector scan angle increases, the line number also increases, and the maximum line number is given for a scan angle of +90°. To achieve this method fan-shaped 90°
B equal to the number of remote paths occurring in is input to a first input terminal of arithmetic logic circuit ALU 1134 via AND gate 1132. The second input to ALU 1134 is the signal (θ) (A) from multiplier 1130. The other input terminal of AND gate 1132 is ABSx≧
This is the signal of y.

The signals S I GNX and ABSx≧y are provided to exclusive OR gate 1136 . The X signal is supplied as a two's complement signal, and 5IGNX is the most significant bit of signal X. The output of exclusive OR gate 1136 is provided to the Sl input of ALU 1134 and to exclusive OR gate 1138.

The other inputs of exclusive OR gate 1138 are always high level signals. The output of exclusive OR gate 1138 is provided to the SO signal input of ALU 1134. The output of LUT 1134 is bus 114
0 to the adder circuit 1142 along with the constant B.

The output of summing circuit 1142 is the mixed line number assigned to the angular displacement signal from LUT circuit 1124 for the particular sector of interest. The circuit described above operates as follows; from −90° to −45°
For a sector of °, 5IGNX is negative and ABSX≧y
is positive. AND gate 1132 passes signal B to ALU circuit 1134 and exclusive OR gate 11
The output of 36 will be high. And exclusive O
The output of R gate 1138 goes low. SO is low and S
When l is high, the ALU circuit 1134 subtracts the input signal B from the second input signal (θ)(A). Addition circuit 1
The mixed line number output from 142 is (θ)(A) for the sector -90° to -45°.

For sectors from -45° to 00, 5IGNx is negative and ABSx≧y is negative. AND gate 1132 does not pass signal B to ALU circuit 1134. The output of the Etta exclusive OR gate 1136 is low and the output of the exclusive OR gate 1138 is high. When SO is high and Sl is low, the ALU circuit] 134 is sector-shaped -4
The ALU circuit 1134 subtracts the second input signal (θ)(A) from the first input, which is 0 for 5° to 0°, and transfers −(θ)(A) to the adder circuit 1142; Here B
is added. The line number mixed in the sector from -45° to 0° is B-(θ)(A).

For sectors 0° to +45°, S I GNX is positive and 8 B S x>y is negative. AND gate 113
2 does not pass the signal B to the ALtll134. The output of exclusive OR gate 1136 is positive while the output of exclusive OR gate 1138 is negative. When SO is low and St is high, the ALU circuit 113
4 subtracts the first input signal from the second input signal,
Since the first signal is 0 for the fan shape from 0° to +45°, positive (θ)(A) is output.

ALU circuit 1134 supplies this signal (θ) (A) to adder circuit 1142, and this signal is added to B. The mixed line number assigned to sector 0 to 45° is (
θ)(A)+B.

Finally, for sectors from 45° to 90°, ABSx>y is positive and 5IGNX is positive. AND Kate 1132 is B
is passed to ALU 1134 and exclusive OR gate 1136 becomes negative. The output J of exclusive OR gate 1138 is positive. When SO is high and 81 or low, QLt1 circuit 1134 subtracts the second signal from the first signal. Signal B-(θ)(A) is on bus 1140
is transferred to adder circuit 1142 through B, and the signal is added to B. The output of the adder circuit 1142 is 2B=(θ)(
A). To summarize, sector line number formula % formula %) () () ) ) () - As an example, assume that there are 120 scanning lines in a sector of 180 degrees. Therefore, A is a LUT of 120/l F30-2/3 and B=2/120=60, and 1124 outputs the value of e- from 0 to 45 degrees for the sector -90 degrees to -45 degrees. By entering these values into equation θA, we can obtain line number 0 for a sector angle of -90° and line number 30 for a sector angle of -45°.

LU'l' circuit 112 for fan shape -45° to 0°
4 gives the angle θ from 45° to 0. By substituting these values into 2B-θA along with the appropriate values A and B, line number 30 is assigned to the sector angle of -45°, and line number 60 is assigned to the sector angle of 0°. . LOT circuit 112 for sector 0° to 45°
4 provides an angle θ from 0° to 45°. Substituting these values into the equation OA+B yields line number 60 where the fan angle is equal to 0, and line number 90 for angle θ relative to 45°. Finally, a fan shape of 45° to 9θ.

For the LU'l'' circuit 1124, the angle 45° to 0
θ is supplied. By substituting these values into Equation 2B-θA, we can obtain line number 90 for a sector angle of 45° and line number 120 for a sector angle equal to 90°.

In FIG. 11, which is a portion of FIGS. 6 to 10 and FIG.
It is shown being clocked by MH2's clock. This clock was reviewed in conjunction with FIG. However, all of the processes described in connection with FIGS. 6-10 and 11 do not operate simultaneously on the X and y signals. The device shown here is a pipeline processor. The processing of the signal may be delayed for various simplifications or, in particular, in the parallel parts of the circuit, e.g.
Parallel circuits for parallel processing of the outputs of the multiplier 722 are not shown. The timing of the parallel processing of the various signals through the circuits described above to obtain mixed row and column numbers that occur in the memory addressing and filter circuits is illustrated in FIG. FIG. 12 is a state diagram of the processing transaction.

12, 6, 7 and 11 to determine the final interpolated gray scale value to be assigned to the selected display pixel through operation of the algorithm of FIG. The left-hand rows numbered 1-1 sequentially from 0 to 19 in Figure 12 to identify the 20 consecutive clock signals from the step of increasing X along a particular rask scan. .

Clock O indicates the step of increasing the value of X, where the increased value of X is placed in register 610. In the next clock period (1), the absolute value of X is determined by circuit 712. Of course, the absolute value X is determined at the same time, and this
is increased again and processing of the next selected display pixel is started. In practice, during the clock pulses described below for the processing of a particular pixel, a new pixel selected by increasing the value X is selected and its processing begins in parallel.

In clock period 2, the ABSx signal is compared with the y signal and substituted into variables W and vlJ<x and y. Comparison circuit 1
104 and switch circuits 1106 and 1108%. In clock period 3, LUT circuit 1112
determines l/v and the soft factor is soft register 1
118. At the same time, the W and ■ signals are delayed and stored in a renostar (not shown). In clock period 4, 1/v and W are delayed and W is shifted into shift register 1118 to obtain a 12-bit subset for transfer to multiplication circuit 1114. In clock period 5, W and W are a subset of 1/v. is multiplied and V is further delayed.

Next, in clock period 6, [(1/cosθ)-1]
Coefficients Z and θ equal to are determined in LUT circuit 1124 and stored in a register to delay . In clock period 7, θ is multiplied by a calculation circuit 730 and converted into a line number, while Z and y are multiplied by a calculation circuit 742. ■ will be delayed once again. A special 45° sector of symmetry is unfolded from the folded state and unfolded in ALU circuit 1134 in clock period 8 while y is added to yz in circuit 744 to determine the mixed column number. In clock period 9, sector rotation factor B is added to the output of A L U in circuit 1142 and a hose correction factor is determined by LUT circuit 762 . The output of the mixed column number circuit 744 is displayed. Then, in clock period 10, the pose collection factor is applied to circuit 11 in circuit 760.
42 is added to the line number determined by 42. A skinline offset factor is added to the mixed column signal during this clock period.

During clock periods 11-17, the fractional portion of the mixed column signal from switch circuit 764 is delayed, and during clock periods 11-14, the fractional portion of the mixed column signal is delayed. The fractional portion of this mixed column and row signal is delayed while the integer portion of the column and row signal is used by the memory addressing circuit of FIG.
The resulting data samples are latched and sent to filter circuit 160. The fractional portion of the column signals mixed during clock periods I5 to 17 is used to determine intermediate interpolated values f1 and f2 as shown in FIG. 1O. The fractional portion of the row signal mixed at clock pulses 18 and 19 is then used to complete the interpolation.

[Brief explanation of the drawing]

1 is a block diagram of an ultrasonic scanning system including a preferred embodiment of the scan converter of the present invention; FIG. 2 is a diagram representing Rask scan interpolation for fan conversion; and FIG. A diagram showing the state of memory for the interpolation of the present invention that performs scan conversion, Figure 4 is a timing chart showing the number of display pixels in conventional rask scanning, and Figure 5 is the correlation between display, image, and memory space. FIG. 6 is a block diagram of the coordinate conversion portion of the address signal generation portion in FIG. 1, and FIGS. 7a and 7b are detailed block diagrams of the address signal generation portion in FIG. Figure 8 is a diagram showing an example of wobbler error when an oscillation transducer is used in an ultrasonic scanning system; Figure 9 is a detailed block diagram of the first part of the memory control in Figure 1;
0 is a detailed block diagram of the filter in FIG. 1, FIG. 11 is a diagram showing another example of the address signal generation section in FIG. 1, and FIGS. 12a and 12b are diagrams of the scan conversion device in FIG. 1. It is an overall timing chart showing the operation. 100... Ultrasonic scanning system, 11.0... Ultrasonic scanning device, 120 Scanning data memory, 130 Memory controller, 140... Address signal generator, 1.
50・Display device, 160 Filter, 1.70 Video output circuit, 180・Rask scanning signal generator, 700
Scan conversion circuit, 900...Memory address circuit. Patent Applicant: Advanced Chikunorono Laboratories, Inc., Patent Attorney Aoyama, 1 person, continued from page 1 ■Int, C1, 4 Identification code Office reference number G 01
S 15/89 8124-5J [Phase] Inventor Christopher Pi USA-0 Zobuki Brescia 23481

Claims (1)

[Scope of Claims] (1) A received echo signal representing the amplitude of ultrasound energy returning from sample points distributed in image space and separated from each other in display space. Linear or sector scan modes are possible, converting the signal for display as display pixels along multiple consecutive rask scan lines distributed, with each received echo signal coming from an even or odd numbered path. a scan converter configured to receive and place even or odd sample sequences along its path, the scan converter having four memory quadrants, each quadrant associated with an even and odd path and sample sequence; a scanning data memory for storing one signal from the received signal in one of each quadrant; By combining the received echo signals from four sample points, selected one by one, in a predetermined manner, gray color is generated for each sequentially selected pixel from the display pixel along one rask scan line. 1. A scan conversion device comprising: circuit means for determining a scale value. (2) the scan data memory has at least one pair of scan data memories, each scan data memory having four quadrants associated with four even and odd mutually spaced paths and sample columns; The received echo signal from the current scan of the space is stored in one side of the pair of scan data memories, and is combined by the circuit means with the received echo signal from the previous scan stored in the other memory. A scan converter according to claim 1, wherein the scan converter is a scan converter according to claim 1. (3) a single stage of circuitry comprising: generating means for generating a pair of signals associated with a selected display pixel including a mixed path signal and a mixed column signal; and in response to the mixed path signal and the sampled column signal; Even number column/
2. Means for generating address signals for a scanned data memory comprising an even row address, an odd column/even row address, an even column/odd row address, an odd column/odd row address. Scan converter as described. (4) circuit means coupled to the scanning data memory and comprising a filter circuit for combining four adjacent received echo signals and a fractional portion in response to the fractional portions of the mixed path signal and the sample train signal; 4. A scan conversion device as claimed in claim 3, which determines a gray scale value of a display pixel. (5) the filter circuit comprises means for producing a first intermediate gray scale value from the received echo signal of the first side of the selected display pixel and the first portion of the fractional portion; means for producing a second intermediate gray scale value from the received echo signal on a second side opposite to the first side and the first part of the decimal part; and the first and second intermediate gray scale values and the decimal part. 4. A scan converter according to claim 4, further comprising means for producing a final gray scale value from the remainder of the part. means for generating a mixed rectangular matrix signal associated with the position of the selected display pixel within the sector image space; means for generating a signal; and operating according to whether the scan conversion device operates in a linear scan mode or a fan scan mode to switch between a mixed rectangular matrix signal generation means and a mixed sector polar signal generation means. (7) The scanning mode is a sector scan mode generated by an oscillating wobbler scan head, and the circuit means is configured to switch between the oscillating wobbler scan head and the oscillating wobbler scan head. Scan converter according to claim 1, comprising means for correcting associated Hose errors. (8) The circuit means comprising means for switching scale between display space and image space. Scan converter according to claim 1. (9) Received echoes representative of the amplitude of ultrasound energy returning from sample points along a plurality of paths distributed in the image space and separated from each other. Each received echo signal is capable of a linear or sector scan mode that converts the signal into a signal for display as display pixels along a plurality of consecutive rask scan lines distributed within the display space. A coordinate conversion circuit used in a scan conversion device that receives from an even or odd numbered path and places a selected display pixel in a display space in an even or odd column of samples along that path. means for generating orthogonal X and means for collapsing the fan-shaped image space into a smaller sub-sector; and means coupled to the angular displacement determining means for expanding the fan-shaped image space to produce an angular signal. (10) The means for collapsing the sector image space has means for creating a W output signal substantially equal to the greater of the absolute value of the X signal and a V output signal substantially equal to the smaller of the absolute value of the X signal; A coordinate transformation circuit according to claim 9, wherein the means for determining the displacement comprises: means for producing w/v; and means for producing a sub-sector angle signal substantially equal to tan' (w/v). . (11) The means for creating w/v includes a circuit that multiplies W and 1/v, where W is a multiple bit number having more bits than 1/v, and this circuit multiplies W and 1/v. 11. The coordinate conversion circuit according to claim 10, further comprising means for selecting a number of subsets of W equal to the number of pits of , and this number of subsets varies depending on the magnitude of V. (12) For w/v multiplication, the arithmetic circuit determines 1/v according to ■, and uses an l/v reference table that creates a signal proportional to the size of ■, a parallel input terminal that receives W, and the bits included in W. circuit which has parallel output terminals for supplying a subset of bits and transfers the W power to the output subset bits in response to a signal from a look-up table.
12. The coordinate transformation circuit according to claim 11, further comprising: multiplication means for multiplying the I/v output of the look-up table by the shifted output subset bit from the circuit. (J3) A received echo signal representing the amplitude of ultrasound energy returning from a sample point along a plurality of paths distributed in image space and separated from each other by a plurality of paths distributed in image space. It is converted into a signal for display as display pixels along continuous rask scan lines. Coordinates used in a scan converter capable of linear or sector scan modes, such that each received echo signal is received from an even or odd numbered path and placed in an even or odd sample column along that path. means for generating X and Y signals at right angles relative to the position of the selected display pixel in the display space; and a radial signal in response to the quadrature X and Y signals, the converting means includes means for outputting a signal determined by the X and y signals and proportional to y/cos θ This means y and [(1/c
osθ)-1] is a coordinate conversion device having an arithmetic circuit and a circuit that adds y to the output of the arithmetic circuit. (14) The circuit that generates the radial direction signal includes means for generating the W signal and ■signal, which are the large and small parts of the absolute value signals of X and y, means for outputting w/v, and cos [tan-' ( 13. The coordinate conversion circuit according to claim 12, further comprising means for outputting cos θ substantially equal to w/v)]. (15) The means for outputting w/v includes means for multiplying W and l/v, where W has more bits than l/v, and the means for multiplying by the number of bits in 1/v. 14. The coordinate conversion circuit according to claim 13, further comprising means for selecting a number of subset pits of W equal to , the number of subset bits being different depending on the magnitude of V.