JPS6022795B2 - data processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device such as an electronic cash register having a memory cassette that is detachably coupled thereto.

Recently, many electronic cash registers have been used in supermarkets, department stores, etc.

These electronic cash registers have a read-only memory (ROM) for storing programs and a random memory for storing information that may change, such as tax information, price lookup (PLU) information, etc. It is equipped with an access memory (RAM).

In the past, in order to change the information stored in this RAM, individual electronic cash registers were operated and new information was independently written into the RAM. Since such assembly is laborious and time consuming, a plurality of memory cassettes each having a memory area corresponding to the memory area for storing variable information in this RAM are used, and these memory cassettes are stored by a store/data processing unit. It has been proposed to commonly write variable information in memory cassettes and insert these memory cassettes into respective memory cassette receptacles of electronic cash registers to facilitate changing information in the RAM. However, in the prior art, no suitable means have been provided for ascertaining whether the memory cassette is securely coupled to a device such as an electronic cash register. SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that visually displays the operating state of a memory cassette connected to the main body of the data processing device using a light emitting element built into the memory cassette. DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory cassette used in electronic cash registers, etc., according to an embodiment of the present invention will be described below with reference to the drawings.

Figure 1 is a perspective view of an electronic cash register; Figure 2 is a perspective view of an electronic cash register;
The figure is a perspective view of a store data processor (SDP) 2.

In this embodiment, two types of memory cassettes are used: a terminal memory cassette 3 and a cache memory cassette 4. First, a predetermined number of terminal memory cassettes 3 are installed in the receptacle of the memory cassette receiving part 20 of the SDP 2, and the keyboard 2
By operating various keys on the terminal 1, a unique terminal number can be preset in each terminal memory cassette 3, and data such as tax table, price lookup PLU) data, date, etc. can be preset in these memory cassettes 3. Write common data sequentially.

In other words, this terminal memory cassette 3 contains a conventional electronic register random access memory (RAM).
) is stored.
Next, the cashier memory cassette 4 is inserted into the memory cassette receiving section 2 of the SDP 2, and by operating various keys on the keyboard 21, the cashier code, date, etc. are stored in the cashier memory cassette 4. Set the data. The memory cassettes 3 and 4 storing predetermined data in this way are connected to the memory cassette receptacles 11 and 12 of the electronic cash register 1.
are installed inside each.

As a result, the cashier performs tasks such as registration on the electronic cash register 1 by operating the keys on the keyboard 13 in the same way as in the case of a normal electronic cash register. . This registration data is recorded in both memory cassettes 3 and 4.
In the middle of a day's work, when a cashier moves from the first electronic cash register that he has been in charge of to another second electronic cash register to continue registering, he must use his own cashier memory cassette 4. need only be inserted into the memory cassette receptacle 12 of the second electronic cash register.

In this case, the memory cassette 4 of this cashier stores, following the registration data stored in the first electronic cash register, registration data corresponding to the registration task to be executed in the second electronic cash register. be done. On the other hand, in the terminal memory cassette 3 of this second electronic cash register, registration data corresponding to the registration business executed at this second electronic cash register is stored, regardless of the cashier operated. . In this way, the terminal memory cassette 3 stores registration data corresponding to a registration operation performed at a particular electronic cash register, and the cashier memory cassette 4 stores registration data corresponding to a registration operation performed at a particular electronic cash register. Registration data corresponding to the business is stored. This allows it to be used for individual cashiers, which can be removed from the cash register, moved with the cashier, and stored in the cash tray for loading and unloading cash, etc., depending on the cashier and the transaction being carried out. Cash, credit cards, etc. should always match the registered data recorded in the cashier memory cassette of this cashier. If they do not match, this cashier has made a registration error or another error. Such a check is performed, for example, at the end of a day's work. The memory cassettes 3 and 4 that have stored the registered data in this way are removed from the electronic cash register at the end of the day and installed in the SDP 2, where all the registered data of a predetermined number of terminal memory cassettes 3 are tallied. is,
The total sales of all electronic cash registers, that is, the daily total sales data of this store can be obtained.

In addition, all the registered data of a predetermined number of cashier memory cassettes 4 are totaled to obtain the total sales data of each cashier and the total sales data of all cashiers, that is, the total sales data of this store for one day. By comparing the total sales data obtained from the memory cassettes 3 and 4 thus obtained, it is possible to check the reliability of this sales data. Next, the configuration of SDP2 will be explained in detail.

FIG. 3 shows the cassette memory receiving section 20 of the SDP2.
When transmitting or writing data to memory cassettes, these memory cassettes are arranged in, for example, two rows of one-needle receptacles 20-1 to 20-1.
It is installed within 6. A numerical value indicating the receptacle number and an indicator lamp are arranged on each receptacle to indicate that data is being read or written to the memory cassette. Adjacent to the receptacles 20--20-16, one-needle storage receptacles 20-17 and 20-32 are provided for storing unused memory cassettes. Fourth
The figure shows the display section 22 of the SDP2.

In this example, a 10-digit display unit 22-1 is used, the first four digit display section of this display unit 22-1 is used to display the cashier code number and the memory cassette number, and the last six digits are used to display the cache code number and memory cassette number. The display selection is used to display monetary information, etc. The display section 22 further includes a plurality of display lamps for displaying various operation modes, but since these lamps are not directly related to the essence of the present invention, their explanation will be omitted here.

FIG. 5 shows the keyboard 21 of the SDP2.

This keyboard 21 has numbers "0bi", "0" to "9"
11 calendar number keys 21-1 indicating the cash, etc. registration keys 21-2 for registering information regarding the inflow and outflow of cash, etc., and cashier, overall store and weekly sales. Sales report keys 21-3 for creating a table of information; terminal code keys 21-4 for registering the terminal code number of the electronic cash register; and terminal code keys 21-4 for registering the cashier code number. cashier code key 21-5,
Sales information selection keys 21-6 for creating tables regarding transaction information, operating efficiency information, sales information by hour, sales information by department, and sales information by product code;
Control to set the operating mode. 21-7 and 21-8. Once the selection key 21-6 is pressed, it is held in this pressed position until it is pressed again and released. Figure 6 shows the electronic circuit section 2 of SDP2.
00 and this electronic circuit 200' are shown without the one-wire memory cassette 201 and 216 connected thereto.

This electronic circuit 20 is a central processing unit (CPU) 220
, a dedicated memory (ROM) 221, a random access memory (RAM) 222, and a single-needle memory cassette interface 223 to 238 for electrically coupling the CPU 220 and the memory cassette 201 to 216. We are prepared. This interface will be explained in detail later. In addition to the CPU 22 and Masa Kawa, the keyboard drive circuit 23 will be explained in detail later.
9 to the keyboard circuit 240 , a display drive circuit 241 to the display circuit 242 , and a printer drive circuit 243 to the dot printer circuit 24 .
4 is combined. FIG. 7 is a circuit diagram showing in detail the keyboard drive circuit 239 and keyboard circuit 240 shown in FIG. 6.

For example, when an address signal "0110" is sent from the CPU 220 via the address bus line, the address match detection circuit 23 of the keyboard drive circuit 239
9-1 detects that this keyboard drive circuit 239 is selected. As a result, this coincidence detection circuit 239-1 connects the output terminal "6" to the AND gate 239.
-2 and 239-3. As a result, a write signal sent from the CPU 220 via the write line is supplied to the 16-ship decoder 239-4 via the AND gate 239-2, setting the decoder 239-4 to the operating state. The decoder 239-4 thus set to the operating state sequentially and repeatedly outputs data from the output terminals "0" to "15" according to the data signal sent from the CPU 220 via the data bus line. A plurality of keys 24 arranged in a matrix form generate pulses.
0-1 and 240-2 supply V to the key matrix of keyboard circuit 240. Each key in this key matrix corresponds to each key shown in FIG. The output signal of this key matrix is sent to the CPU via four AND gates 239-5 to 239-8 and a data bus line.
220. These AND gates 239-5 through 239-8 connect read lines and A
It is energized by the output signal sent through the ND gate 239-3. In this way, the CPU 220 detects which key on the keyboard has been operated. Further, when there is a mistake in key operation, an error signal generated from the CPU 220 is applied to the input terminal A of the monostable multipipulator 239-9 via the error signal line.

As a result, a high level signal is applied to the oscillator 239-1 from the output terminal Q of the multipipulator 239-19, setting the oscillator 239-10 to the operating state.
The alarm 240 is activated by the output signal of this oscillator 239-10.
-3 is energized and generates an alarm. The multipipulator 239-9 is activated by the decoder 239 after the error is cleared.
The state is switched by the output pulse generated from output terminal 15' of output terminal 14, and a low level signal is generated from output terminal Q to stop the operation of oscillator 239-10. The memory cassette interface 223 is shown in detail.

Of course, the configuration of the other interfaces 224 and 228 is similar to that shown in FIG. 8, except that the address match detection circuits 223-1 are each configured to have a unique code. be. This interface 2
The coincidence detection circuit 223-1 of No. 23 is similar to the coincidence detection circuit 239-1 shown in FIG.
For example, output terminal "8" when sent from U220.
generates an output signal from the flip-flop circuit 223
-2 input terminal T.

In this state, when a signal is applied from the CPU 220 to the input terminal D of the flip-flop circuit 223-2 via the data bus line, the flip-flop circuit 232-2 connects the AND gates 223-3 and 223-2 to the input terminal D of the flip-flop circuit 223-2.
-4 and NAND gates 223-5. As a result, the output signal and the write signal sent from the CPU 220 via the read line and the write line pass through the AND gates 223-3 and 223-4. Further, an oscillator 223-6 is coupled to the input terminal of the NAND gate 223-5.
The -6 output pulse periodically turns on and off transistor 223-7 via this NAND gate 223-5. If the match detection circuit 223-1 is not supplied with an address signal having a unique code, a low level signal will be generated from the output terminal Q of the flip-flop circuit 223-2, and this will cause the NAND gate to 223
A high level output signal is generated from -5, and the collector is low.
Transistor 223-7, which is coupled to the ED energization terminal and whose emitter is grounded, is rendered conductive. Note that the CPU 220 is connected to the reset terminal R of the flip-flop circuit 223-2.
It is connected to the IJ set line from. Decoder 2
23-8 output terminals "0" and "1" in response to information signals sent from the CPU 220 via the data bus line.
, “2” or “3” to select the memory chip of the memory cassette coupled to this interface 223.

Further, the addressing of this memory cassette is performed via a plurality of addressing lines, each including an inverter 223-9 having a buffer function, and data transfer between this memory cassette and the CPU 220 is performed in both directions using an inverter 223-9 having a buffer function. Implemented via multiple data lines including circuit 223-10. FIG. 9 shows a circuit diagram of the cashier memory cassette 4.

When this memory cassette 4 is inserted into the memory cassette receiving section 2 of the SDP 2 shown in FIG. 2, the circuit of this memory cassette 4 is connected to the interface 22 shown in FIG.
It will be combined into 3. That is, the random access memory (RAM) 40 of this memory cassette 4
A plurality of addressing lines 402 for specifying one address are coupled to an addressing line with an inverter 223-7, and a plurality of data lines 403 for this RAM 401 are connected to an inverter circuit 223-7, respectively.
is connected to the data line with . A selection line 404 for selecting this RAM 401 is connected to a decoder 223-6.
read line 405 and write line 406 for this RAM 401 are coupled to AND gates 223-3 and 223-4, respectively;
When this memory cassette 4 is coupled with the interface 223, reading and writing of data to the RAM 401 is performed using the power supply line of the interface 223 and the power supply lines 407 and 408 of this memory cassette 4.
When this memory cassette 4 is removed from the interface 223, the stored contents of the RAM 401 are transferred to the internal power source E.
is held by Also, when this memory cassette 4 is coupled to the interface 223, the LED energizing line 4
09 is coupled to the collector of transistor 223-7 via the LED activation terminal. This LED energizing line 40
9 connects a light emitting element 410 such as a photodiode placed at a position that can be observed from the outside, for example, on the surface facing the connector section of this memory cassette, to the power supply line 407 and L.
It is connected between the ED energizing terminals. In normal times, that is, when an address signal with a unique code is not supplied to the coincidence detection circuit 223-1 of this interface 223, the transistor 223-7 is conductive, and the memory cassette is securely connected to this interface. The light emitting element 410 of 4 is energized to emit light, visually indicating that the memory cassette is securely coupled to the interface 223. Next, when information is transferred to the RAM 401, the interface 22
When an address signal with a unique code and a data transfer start signal are applied to the coincidence detection circuit 223-1 of No. 3, the flip-flop circuit 223-2 is set and a high level signal is generated from the output terminal Q. An inverted signal of the output signal of the oscillator 223-6 is generated from the NAND gate 223-5 to periodically turn on and off the transistors 223-7. This allows this interface 22
The light emitting element 410 of the memory cassette 4 coupled to the memory cassette 4 will be blinking, indicating that this memory cassette is in operation. FIG. 10 shows a circuit diagram of the terminal cassette 3.

This circuit uses four RAMs 31 1 to 314, and in order to select these RAMs, four chip selection lines 304 are connected to the decoder output terminals "0", "1", "2" and This is similar to the cache memory cassette 4 shown in FIG. 9, except that it is connected to the memory cassette "3". Next, the configuration of the electronic cash register 1 shown in FIG. 1 will be explained in detail.

FIG. 11 shows the display section 14 used in this electronic cash register 1. As shown in FIG.

This display section 14 has a one-digit display unit 14-1,
The display selection of the first six digits of this display unit 14-1 is used to display the amount, and the display selection of the bottom four digits is used to display the department and repeat. Note that this display section 14 includes a plurality of display lamps 14-2 to display various operation modes. FIG. 12 shows the keyboard 13 of the electronic cash register 1 in detail.

As is generally well known, this keyboard 13 has 11 calendar number keys 13-1 that are operated to number the numbers "00", "0" to "9", and a category for sales products. Department keys 13-2 for separate registration and function keys 13 operated for registering transaction details.
-3, and main keys 13-4 for setting the registration operation mode and the like. FIG. 13 shows the electronic circuit section 100 of the electronic cash register 1 and the cashier memory cassette and terminal memory cassette 3 shown in FIGS. 9 and 10, respectively, to which the electronic circuit section 10 is connected. shows.

This electronic circuit section 100 includes a central processing unit (CPU) 1
20, a read-only memory (ROM) 121, a random access memory (RAM) 122, a terminal interface 123 for electrically coupling the terminal memory cassette 3 to the CPU 1201, and a cashier memory cassette 4 to the CPU 120'. A cashier interface 124 is provided for electrical coupling. This CPU 12 is connected to a keyboard circuit 126 via a keyboard drive circuit 125, which will be described later.
It is coupled to the display circuit 128 via the display drive circuit 127 and connected to the printer circuit 13 via the printer drive circuit 129.
It is combined with 0. FIG. 14 is a circuit diagram showing in detail the keyboard drive circuit 126 and keyboard circuit 126 shown in FIG. 13.

This circuit is basically the same as the circuit shown in FIG. 7, and the data processing circuit 125-1 is replaced by the address match detection circuit 239-1 and AND gates 239-2, 23 of FIG.
It performs part of the functions of 9-3 and CPU 220,
For example, it is based on INTEL8279.

The decoder 25-2 sequentially and repeatedly generates output pulses from output terminals "0" to "9" in accordance with the address signal from the data processing circuit 126-1. The keyboard circuit 126 includes a key matrix 126-1 in which a plurality of keys corresponding to Taoist keys, department keys, function keys, etc. are arranged in a matrix, and a key matrix 126-1 consisting of a plurality of keys corresponding to control keys, etc. array 12
It has 6-2. When a key in the key matrix 126 is operated, this key operation is transmitted to the decoder 2.
Detected by the output pulse from 5-2, information regarding this key operation is sent to data processing circuit 125-1. Data processing circuit 1 that receives information regarding this key operation
25-1 converts the key information corresponding to this input information into data.
It is supplied to the CPU 120 via the bus line, and also sends a signal indicating that a key has been operated to the CPU 1201 via the key operation detection line. Also, the key array 126-
2 is operated, this key operation is detected by the output pulse from the decoder 125-2, and information regarding this key operation is transmitted to the CP via the data bus line.
At the same time, a key operation detection signal is sent to data processing circuit 125-I to C via a key operation detection line.
It is sent to PU120. In this manner, the circuit shown in FIG. 14 sends key information corresponding to the operated key to the CPU 12, similar to the circuit shown in FIG.

FIG. 15 shows a circuit diagram of the terminal interface 123.

This interface 123 is constructed similarly to the interface 223 of the SDP2 shown in FIG. 8, and functions similarly. In the terminal interface 123 shown in FIG. 15, circuit sections similar to those shown in FIG. 8 are given corresponding reference numerals. Of course, it is possible to configure address match detection circuit 123-1 to provide an appropriate code to address match detection circuit 123-1. Further, the cashier interface 124 can also be constructed in the same manner as the interface shown in FIG. 15, except that the code of the coincidence detection circuit is different. It is also possible to omit the decoders 123-6 in this cashier interface 124. Next, the operation of electronic cash register 1 and SDP 2 will be explained.

First, a predetermined number of terminal memory cassettes 3 to be used are installed in the receptacles of the memory cassette receiving section 20 of the SDP 2.

In order to write a terminal code into one of the terminal memory cassettes 3, an address matching detection circuit 223-1 (FIG. 8) of one of the memory cassette interfaces 223 to 228 (FIG. 6) is used. Unique code of
The corresponding numerical information is the layer number key 21-1 (Figure 5).
The match detection circuit 223-1 is supplied by operating . After this, “=” in action keys 21-2
"By operating the key, the flip-flop circuit 223-2
A signal is applied to the D input terminal of the flip-flop circuit 223-2, and a high level signal is generated from the Q terminal of the flip-flop circuit 223-2. As a result, the RA selected by the decoder 223-6 of this terminal memory cassette 3 is transmitted through the photodiode 309 and the phototransistor 310.
M, for example RAM311, is activated. Next, numerical information indicating a desired terminal code is stored in this RAM 311 by operating the calendar number key 21-1 and operating the terminal code key 21-4. A similar operation is performed when storing a terminal code in a memory cassette for another terminal. FIG. 16 is a flowchart showing the procedure for setting this terminal code or cashier code. Once every terminal memory cassette has been filled with a unique terminal code, the desired information is then written into the terminal memory cassette. This information writing operation is similar to writing desired information into the RAM of the electronic cash register in a conventional electronic cash register. FIG. 16 shows a modification of the cashier memory cassette 4 shown in FIG.

This cashier memory cassette has manual switch 4.
The configuration is substantially the same as that of the cashier memory cassette shown in FIG. 9, except that 11 is coupled between the light emitting element 410 and the negative power supply line 408. This manual switch 411 is operated manually when this cashier memory cassette is not inserted into the receptacle of the electronic cash register 1 or SDP 2, and when it is inserted into this receptacle, it is not accessible from the outside. , it is convenient to place it at an appropriate position in this memory cassette. When this memory cassette is not inserted into the receptacle, this manual switch 411
When operated, the light emitting element 410' is energized by the battery E and emits light, providing a visual indication that the battery E has sufficient energy to drive the RAM 401. FIG. 17 shows another modification of the cashier memory cassette 4 shown in FIG.

This cashier memory cassette contains diodes, resistors,
The structure is similar to that of the cashier cassette shown in FIG. 9, except that a series circuit including a light emitting element 412 and a manual switch 413 is connected between battery B and negative power supply line 408. Further, the switch 413 is manually operated from the outside, similar to the switch 411 used in the cashier memory cassette shown in FIG. When this switch 413 is operated, the light emitting element 41
2 is energized by battery E and emits light, and this battery E
Provides a visual indication that sufficient energy is retained to drive AM401. The light emitting element used in FIGS. 16 and 17 is designed so that it will not emit light even if switch 411 or 413 is operated when the electromotive force of battery B decreases to a certain extent and is no longer sufficient to drive RAM 401. ing.

Although the present invention has been described above with reference to Examples, the present invention is not limited to these Examples.

For example, although the memory cassette described in this embodiment is used in an electronic cash register, it is also possible to use this memory cassette as part of the arithmetic memory section of an electronic desktop calculator, for example.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an electronic cash register, FIG. 2 is a perspective view of a store data processing unit used in combination with the electronic cash register of FIG. 3
5 to 5 respectively show the memory cassette receptacle section of the store/data processing unit shown in FIG.
6 is an electronic circuit diagram of the store/data processing unit shown in FIG. 2; FIG. 7 is a detailed circuit diagram of the keyboard drive circuit and keyboard circuit shown in FIG. 6; 8 is a detailed circuit diagram of the interface circuit shown in FIG. 6, and FIGS. 9 and 10 are a memory cassette for a cashier and a memory for a terminal shown in FIG. 6, respectively, according to an embodiment of the present invention. The circuit diagram of the cassette, Figures 11 and 12 are respectively front views of the display and keyboard of the electronic cash register shown in Figure 1, and Figure 13 is the electronic cash register shown in Figure 1. 14 is a detailed circuit diagram of the keyboard drive circuit and keyboard circuit shown in FIG. 13, FIG. 15 is a detailed circuit diagram of the interface circuit shown in FIG. 13, and FIG. 16 and FIG. 17 shows a modification of the cashier memory cassette shown in FIG. 9, respectively. 3...Memory cassette for terminal, 4...Memory cassette for cache, 401...RAM, 402...Address line, 404...Data line, 407, 408...
Power line, 410, 412... Light emitting element, 411,
413...Manual switch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 8 Mountain vertical diagram Boat diagram Boat diagram 9 Figure 11 Figure Ship diagram 12 Figure 15 Figure M Ship diagram Dimensions Ship diagram 16 Figure 17 figure

Claims (1)

[Scope of Claims] 1. A data processing device comprising a data processing device main body and a memory cassette which is detachably coupled to the data processing device main body and through which data is transferred between the data processing device main body and the data processing device main body. In the device, the memory cassette has first and second power terminals, a storage unit coupled between the first and second power terminals, an addressing terminal, a data input/output terminal, and a light emitting element activation terminal. an address line coupled between the memory unit and the address designation terminal; a data transfer line coupled between the memory unit and the data input/output terminal; and a coupling between the first power supply terminal and the light emitting element energizing terminal. when the data processing device main body includes a keyboard having a plurality of numeric keys and function keys, a storage means, and the memory cassette in a detachable manner,
an interface circuit having a biasing means coupled to a light emitting element biasing terminal of the memory cassette; the keyboard;
It is coupled to a storage means and an interface circuit, and when writing or reading data to or from a memory cassette coupled to the interface circuit, a selection signal is applied to the energizing means of the interface circuit to energize the memory cassette. A data processing device comprising: a data processing unit that energizes the light emitting element by a means. 2. In the data processing device according to claim 1, the biasing means couples the light emitting element biasing terminal to the second power supply terminal when the memory cassette is coupled to the data processing device main body. switching means for continuously lighting the light emitting elements; and switching means for periodically turning off the light emitting elements in response to a selection signal supplied from the data processing unit during write and read operations. What is claimed is: 1. A data processing device characterized by comprising a control circuit that turns on the light. 3. The data processing apparatus according to claim 1, further comprising manual switching means coupled between the second power supply terminal of the memory cassette and the light emitting element energizing terminal.