JPS6022754B2 - Digital clock display circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to a display circuit for a digital watch.

There are two display methods for digital clocks: the 1st time system from AM/PMI to 1st time, and the 2nd time system from 0:00 to 23:00.

In order to have both of these display functions, a decoder circuit and an output conversion gate circuit are required for each, and 1
When configuring the chip monolithically, there is a problem in terms of the occupied area.

This invention was made in order to reduce the number of constituent elements of a display circuit that has two display functions: 1. Young time system and 2. Misaki time system.

This invention focuses on the fact that the 1-press time system AMI hours to 11 o'clock and the 24-hour system 1 o'clock to 11 o'clock are displayed in the same manner, and by sharing these, the configuration of the decoder circuit can be simplified. It is something that we are trying to change.

Hereinafter, the present invention will be specifically explained with reference to Examples. FIG. 1 is a logic circuit diagram showing one embodiment of the present invention.

This circuit consists of a first decoder circuit 1 for obtaining digital display outputs a to g of the 1st time system, and 2 digital display outputs a to g of the 1st to 2nd time and 0th time of the Misaki time system. The second decoder circuit 2 is used to obtain time 1 of the 2-Misaki time system when switching the display between the 12-hour system and the 24-hour system.
and a gate circuit 3 which uses a first decoder circuit for obtaining a digital display output of the first early time system from 11:00 to 11:00.

The first decoder circuit 1 receives an 8-bit time signal consisting of a signal having only 1, 2, 4, and 8 and its inverted signal, and has a circuit for forming an IQ Hayabusa numerical value output in the 1-child time system; It is composed of a 1G ship numerical value input and an o path for obtaining a display output for driving a numerical display device composed of 8 segments as shown in Fig. 2.

The second decoder circuit 2 inputs the same time signal as described above, and inputs the circuit that forms the 1G boat numerical outputs of 1 childhood to 2 Gunma and 0 o'clock among the 2 small time systems, and this 1Q Hayabusa numerical value. It is constituted by a circuit for obtaining a display output for driving a numeric display device constituted by eight segments similar to the above.

The first and second decoder circuits 1 and 2, including the gate circuit 3 to be described later, have gates connected to the input lines as shown in FIG. The output line is provided with an insulated gate transistor (SFET) whose drain and source are grounded, and the decimal value conversion and segment selection circuits are configured to Configure an input NAND circuit.

For this reason, when the MISFET is of n-channel type, it is configured with negative logic with the ground level set to "1", and when it is of p-channel type, it is configured with positive logic. .

The output of the IG Hayabusa number of the IG Hayabusa number conversion circuit is "0" when all its inputs are "1", and this "0"
The segment selection circuit that receives “MISFB” as input is
A predetermined segment is selected by setting the output line on which T is formed as "1".

Therefore, the IQ Hayabusa numerical value conversion output is configured to alternatively output "0". Note that when two digits are displayed, two are selected, but "0" is ultimately output as an alternative through time-division output, which will be described later. The gate circuit 3 outputs the 1st time system/2nd time system display switching signal (12/24) and the A
The M/PM display signal (AM/PM) is input.

The above display switching signal (12/24) is 1 when it is “0”.
2-hour system display, "1" indicates 24-hour system display, and the display signal (AM/PM) is to display AM when "0" and PM when "1". It is. NAND circuit (NAND,) that takes the above two signals as input
is used to switch to the first decoder circuit 1 when the output is "1", and to the second decoder circuit 2 when the output is "0".

Therefore, the MSFETs provided at the 1G numerical conversion outputs of the i-th decoder circuit are driven by the output of the NAND circuit, and the MISFETs provided at the IG Hayabusa numerical conversion outputs of the second decoder circuit are driven by the NAND circuit. The inverted output of the circuit is formed and driven by an inverter circuit (IN2). Note that the second decoder output 1G
The output for displaying the number of ships as 0 is a MISF driven by the output of the NAND circuit for displaying the above-mentioned 1 early time system output.
ET. This is the output for displaying 0 o'clock in the 2nd period time system, and is the display switching signal (12/24
) is also provided on the output line.
On the other hand, the output line for displaying the 1st childhood of the 1st childhood time system has a skin SF driven by an inverted signal of the display switching signal.
ET. As a result, the binary power is “0”
When displaying 1 Liu time system for “0”, “0”, and “0”,
Outputs the IQ Hayabusa value of 2 for the first decoder circuit 1, and outputs the 1G value of the second decoder circuit 2 of 0 when the 2-character system is displayed.
Output.

Note that the signal (10H) is used to obtain segment output for each digit by time division when displaying two digits.

In this embodiment, when displaying in the 1-anchor time system, only the first decoder is operated by the gate circuit 3, so that display outputs for 1 and 10 o'clock and from 1 to 11 o'clock can be obtained. In addition, when performing a ~2 special interval display, the gate circuit 3 operates the second decoder circuit for displaying 0 o'clock and 1 feeding time to 2 feeding time, and operates the first decoder circuit for displaying from 1 o'clock to 11 o'clock.
The decoder circuit is operated to obtain a display output of 0 to 2 decimations using both of the decoder circuits.

In this embodiment, since the decoder circuit is shared as described above, it can be simplified and the number of elements can be significantly reduced. Therefore, it is extremely useful when constructing an electronic digital timepiece using a one-chip monolithic IC. The invention is not limited to the examples described above, but can explore various embodiments.

In the embodiment described above, a mask ROM was used, but a decoder circuit or a gate circuit using various logic circuits may be used.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a segment pattern diagram of the numeric display device, and FIG. 3 is a diagram for explaining the circuit symbols of FIG. 1. 1, 2... decoder circuit, 3... gate circuit. Figure 1, East Z map, Figure 3

Claims (1)

[Claims] 1 It has two display functions, 12-hour system and 24-hour system, and its input information is time counter information from 0 to 11 and A
A display circuit for a digital watch, which is provided with M/PM information and 12-hour/24-hour display switching information,
a gate circuit for receiving the AM/PM information and the 12-hour/24-hour display switching information;
The gate circuit when the time system display switching information indicates a 12-hour system, the 12-hour/24-hour display switching information indicates a 24-hour system, and the AM/PM information indicates AM. a first decoder circuit that is operated by the output and outputs a display decode signal from 1 to 11 o'clock in accordance with the time counter information from 0 to 11 during operation; It is operated by the output of the gate circuit when the 24-hour system is indicated and the AM/PM information indicates PM, and decodes for displaying 0 o'clock and 12 to 23 o'clock according to the time counter information during operation. 1. A display circuit for a digital watch, comprising: a second decoder circuit that outputs a signal; and wherein the first and second decoder circuits have a common output.