JPS60227523A - Error correcting decoding circuit - Google Patents

Abstract

PURPOSE:To select the optimum operation mode in accordance with the using purpose and to lighten the burden of a CPU, by adding operations from the readout of data before correction from a buffer memory to the writing of the data in the buffer memory after correcting the code of the data. CONSTITUTION:A syndrome register 36, data register 34, majority circuit 41, mode register 80 connected with a timing circuit 27 which designates an operation mode, etc., are provided in an error correcting circuit. Continuous data received by a data receiving circuit 30 are serial-parallel converted at the data register 34 and stored in a buffer memory 29. The data before correction written in the memory 29 are read out and their error is corrected. The corrected data are again written in the memory 29 under the 1st operation mode. Moreover, the data before correction are read out and corrected by means of the registers 34 and 36, circuit 41, etc., and the corrected data are again written in the memory 29 under the 2nd operation mode. Under the 3rd operation mode, data before correction from a CPU are read anc corrected data are sent to the CPU. By selecting two or more operation modes, the burden of the CPU is lightened.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to code error control suitable for coded teletext broadcasting in which character/graphic information coded as a digital signal is multiplexed transmitted during the vertical blanking period of a TV signal. In particular, it relates to an error correction decoding circuit that attempts to recover as much as possible by correcting bit errors occurring on a transmission path.

(Technical Background) As an MD correction method for this type of service that uses a TV transmission line, one nof bit is composed of 272 bits to form a data signal of 272 data bits, 190 information bits, and 82 parity bits. The system for transmitting and decoding is disclosed in Japanese Patent Application No. 58-6579 and Japanese Patent Application No. 1983
-54002 and Japanese Patent Application No. 58-90017.

FIG. 1 shows the configuration of the error correction decoding circuit disclosed herein. In Figure 1, 1 is a CPU (not shown).
CPU bus line connected to output port 2.
and the output terminal of input port 3.

Output port 2 supplies uncorrected data 5 to error correction circuit 4 . The error correction circuit 4 includes a parallel-to-serial conversion circuit, a serial-to-parallel conversion circuit, a syndrome register, a data noster, a majority circuit, etc., and performs an operation to correct the (272,190) code. The error correction circuit 4 supplies the corrected data 6 and the ready signal 10 to the input port 3.

Start signal from CPU via output port 2? , load signal 8. and the collect signal 9 is the error correction circuit 4.
is supplied to.

Next, the operation shown in FIG. 1 will be explained. To start error correction, the CPU first supplies a start signal 7 to the error correction circuit 4 and resets the syndrome register. Next, predetermined bits (e.g. 8 bits).

The CPU supplies the uncorrected data to the error correction circuit 4 via the CPU node line 1 and the output port in units of 16 bits, and provides the load signal 8 each time. The error correction circuit 4 converts the 8-bit (or 16-bit) data from parallel to serial and inputs it into the data recorder and syndrome register. If so, 34
Repeat 1 times (17 times in 16-bit units). 27
A syndrome is created by introducing two bits of data into the syndrome register. When the syndrome is formed, the CPU gives a collect signal to the error correction circuit via the CPU node line 1 and the output date 2, and the error correction circuit 4 corrects the error in units of 8 bits (or 16 bits) and performs serial-parallel conversion. Post-correction data 6
The signal is returned to the CPU via input port 3° and CPU path line 1. If it is repeated 34 times in units of 8 pits (17 times in units of 16 bits), all 272 bits are corrected and loaded into the CPU.

The ready signal 10 indicates whether the CPU may load 8-bit (or 16-bit) uncorrected data into the error correction circuit, or whether the CPU may read 8-bit (or 16-bit) post-correction data. This is a signal to notify the CPU whether the

In this way, the system shown in Fig. 1 has the advantage that the (272, 190) code can be corrected in the memory map I10 format and the circuit configuration is simple. It also has the disadvantage of increasing the burden on the CPU since it must deal with everything from reading to processing of the received signal.

In Japanese teletext broadcasting, it is possible to transmit up to 12 kerats of data during one vertical blanking time, so when processing in units of 8 bits or 1 byte, it is difficult to correct errors. 34 bytes x 2 x 12 packets,
)-8/6 It requires byte time, and it also requires operations to give load and collect commands and to check ready signals, which puts a heavy burden on the CPU and makes it difficult to perform the decoding and display necessary for receiving character code broadcasting. It is necessary to avoid this because it will interfere with the processing to be carried out.

(Objective of the Invention) In order to take advantage of the advantages of the prior art and solve the problems, the present invention converts the transmitted data from serial to parallel, transfers it to the grapher memory, reads the uncorrected data from the buffer memory, and encodes the data. Operation mode (Embodiment 1) from correction to writing of corrected data to buffer memory; CFIU performs operations from correction to writing of transmitted data to reception buffer memory; reading of uncorrected data from buffer memory; code correction; An operation mode (Embodiment 2) for writing to the buffer memory is added to the conventional operation mode (Embodiment 3), so that the optimum operation mode can be selected depending on the purpose of use.

(Embodiment) FIG. 2 shows a mode designation circuit for switching between three operations in the present invention.

In Figure 2, 23 is the local data bus, and 8 is the CPU.
80 is a mode register, 82 is a mode 2 (second operation example) designation signal,
83 is a mode 3 (third operational embodiment) designation signal, and 27 is a timing control circuit.

The CPU outputs the data of the desired operating mode to the local data bus 23 (for example, the 0th bit corresponds to the mode 2 designation signal 82, and the 1st bit corresponds to the mode 3 designation signal 83) and writes the mode register. It is written into the mode register 8° by the signal 81. For example, when selecting mode 2 operation (second operation example), output "1, 0, 0, 0, 0, 0, 0, 0" to the CPU data bus and issue the mode register write signal 8. , outputs a mode 2 designation signal 82 to the timing control circuit 27.

When specifying operation mode 1 (first operation example), set the mode register 8o to “'o, o, o, o, o, o, o,
o'' is written. When both the mode 2 designation signal 82 and the mode 3 designation signal 83 are pao''', it is assumed that mode 1 is designated.

When specifying operation mode 3 (third operation example), select “o”
, i, o, o, o, o, o, o'' in the mode register 80
write to.

Below, operations when each operation mode is selected will be explained in order starting from operation mode 1 (first operation example).

A circuit diagram of a first operational embodiment of the present invention is shown in FIG. In FIG. 3, 20 is a data bus of the CPU (not shown), and 21 is an address bus of the CPU.

A data bus 20 of the CPU is connected to a first input/output terminal of a data bus control circuit 22.
The second input/output terminal of is connected to the local data bus 23.

The address bus 21 of the CPU is an address switching circuit 24.
is connected to the first input terminal of the address switching circuit 2.
An automatic address signal 26 is supplied from an address generation circuit 25 to the second input terminal of the address generator 4. The address switching circuit 24 selects either the CPU address signal applied to the first input terminal or the automatic address signal 26 applied to the second input terminal, based on the bus control signal 28 supplied from the timing control circuit 27. and buffer memory 2
A memory address signal is supplied to the address input terminal of 9.

The local data bus 23 is also connected to a data input/output terminal of a buffer memory 29 and a data input/output terminal of a data transfer circuit 30, so that the CPU, buffer memory, and data transfer circuit can exchange data with each other. I can do it.

The data transfer circuit 30 has serial reception data 3, which is packet reception data received and extracted by a character code broadcast receiving unit (not shown), and frame synchronization is established by the character code broadcast frame signal. A framing detection signal 32 indicating the character code and a synchronous clock 33 whose clocks are synchronized by the clock run-in of the character code are supplied.

The data register 34 is a register for storing and shifting 272-bit packet received data or 190 bits of information bits out of the 272-bit packet received data, and is uncorrected data converted from parallel to serial by the data transfer circuit 30. 35 and shift. Syndrome register 36 is the 10th patent of patent application No. 1986-6579.
It is similar to the one shown in the figure, and has a feedback loop through an adder 37 modulo 2, consisting of 82 bits.

38 is a load gate circuit; timing control circuit 2;
The uncorrected data 35 is sent to the syndrome register 3 via the adder 37 by the load gate signal 39 supplied from 7.
40 is a syndrome register signal, 4 is a majority circuit, 42 is a loading clock signal for loading data into the syndrome register and data register 34, and 43 is a correction signal. 44 is a clear signal for clearing the syndrome register 36; 45 is a collect gate circuit that determines whether or not to supply the result signal of the majority circuit 4 to the adder 37 and 48 as an error correction signal 47; 4
6 is a collect gate circuit for controlling, 49 is corrected data, 5o is a clock signal for performing serial-parallel/parallel-serial conversion, and 51 is a write/write signal for writing received data into the buffer memory 29. A signal 52 is a write/write signal for writing into the buffer memory 29.

Further, 53 is a vertical blanking signal or a signal similar to the vertical blanking signal, 54 is a horizontal synchronizing signal or horizontal blanking signal, and 55 is a status signal indicating the operating state.

56 and 57 are address update signals, and 58 is a CPU data request signal.

The local data bus 23 is connected to the index register 6
The index register is connected to the 00 Å power terminal, and is supplied with a write signal 63 from the CPU and an index shift clock 62 from the timing control circuit 27, and generates a correction index signal 61. The local data bus 23 is also connected to the output terminal of the framing detection register 7θ. 72
is a detection shift clock that shifts the framing detection signal 32 into the framing detection register 70.

Reference numeral 73 denotes a correction index signal; 74 refers to a case that ANDs the correction index signal 6 from the index register 60 and the correction index signal 73 from the framing detection lens 0 to create a correction index signal 75; A correction index signal 75 is provided to the circuit 27.

80 is a mode register, 8 is a mode register write signal, 82 is a mode 2 (second operation example) designation signal, 83 is a mode 3 (third operation example) designation signal, and 82 is a mode register write signal; When the outputs of and 83 are both °°0'', the operation mode is mode 1 (first operational embodiment).

Next, the operation shown in FIG. 3 will be explained.

The operations shown in Figure 3 can be roughly divided into: ■ Directly transmitting serial received data.
Parallel conversion and writing to buffer memory, ■ Read the uncorrected data from the graph memory and load it to the data register and syndrome register, ■ Circulate the data register and syndrome register to correct errors, ■
It consists of four operating modes: writing corrected data to the buffer memory. Finally, the CPU reads out the data stored in the buffer memory.

A flowchart of the concept of these operations is shown in FIG. First, in the first operation mode (operation mode (-)), the received data of all packets of one vertical retrace time are sequentially stored in the graphic memory. Second. Third and fourth operating modes (■
, ■, and ■q operation modes), processing is performed in units of 17 kerats, but before that, it is determined whether or not the packet should be corrected. index register 60
and framing detection register 70 provides an index indicating whether that node is to be corrected, as will be discussed in more detail below.

If the packet should be corrected, the second. 3rd and 4th
The second operation mode (■, ■, and ■) is executed, and if the packet should not be corrected, the second. Search for the next packet without executing the third and fourth modes of operation.

In this way, all the data in the packet that should be corrected is corrected,
- When the data is stored in the buffer memory, the operation ends.The system data signal 55 is issued to inform the CPU that the data can be read from the buffer memory.

The explanation will be given below in order starting from the first operation mode.

FIG. 5 is for explaining the first operation mode and shows the timing of the received data of the character code broadcast. In Fig. 5, 100 is a horizontal synchronization signal, 10 is a color burst, 102 is a 16-bit clock run-in for clock synchronization, 103 is a framing signal for frame synchronization, and 104 is a 272-bit clock. data bits forming the serial reception data 31.

The data transfer circuit 30 receives a framing detection signal 32 indicating that frame synchronization has been achieved in response to the framing signal 103, and can know the start time of serially received data. In addition, since the synchronized clock 33 synchronized by the clock run-in 102 is received, 27
During the 2-bit data bit time, 3 bits of serial reception data are taken in sequentially by the synchronous clock 33 and immediately processed.
Convert in parallel. If the capacity of the local data bus 23 is 8 bits, serial reception data is sent to the local data bus every 8 pins or 1 bit.

Also, at the same time as the data is sent to the local data bus 23, the write signal 9 and the pulse signal 5 are sent to the timing control circuit 23.
7 to the buffer memory as a write/write signal 52. When writing is completed, the address update signal 57 is sent from the data transfer circuit 30 to the address generation circuit 25.
The automatic address signal given to 2.2+1.2+2・
...take slow, step-by-step progress. The starting address of the automatic address signal for a specific packet is automatically determined, for example as shown in FIG.

In the first operation mode, the data bus control circuit 22 operates to separate the CPU data bus 20 and the local data bus 23, and the address switching circuit 24 receives the automatic signal supplied from the address generation circuit 25 out of the two input signals. It operates to select the address signal 26 and transmit it to the address input terminal of the buffer memory 29.

In this way, three pieces of serial reception data of 1 packet = 272 bits are serial-parallel converted and sequentially written into the buffer memory 29 from address α. FIG. 6 shows an operational flow for storing one or more received data in the buffer memory 29. If 8 bits - 1 byte are processed and written, it is repeated 272/8-34 times for one e-ket, and the stored addresses are from address 2 to address α+33.

In Japanese character code broadcasting, up to 12 packets of data can be transmitted during one vertical blanking time, as shown in FIG. In FIG. 7, 110 is a vertical synchronization signal, 11 is a vertical blanking signal, and 112 is 1
Reed with the signal generated from 1, vertical blanking time 2
1H(1) 1 represents one horizontal scanning time. ) is a signal obtained by extracting only the latter 12H. In Japanese character code broadcasting, data can be transmitted during the time when l12 is °L, that is, the latter half 12H of the vertical blanking time.

53 in FIG. 2 is a signal of 112, for example. The address generation circuit 25 counts the horizontal synchronization signal 54 during 112 °I L 11 and provides a partial signal of the automatic address signal. Therefore, when the data transfer for one packet is completed, the next horizontal synchronizing signal 54 arrives, and by counting this, the address is switched to the address where the next data is to be stored. Thereafter, in the same manner, the operation flow shown in FIG. 6 is repeated 12 times to store 12/g of uncorrected data in the buffer memory 29.

In addition, the 112 detects the framing detection signal 32 in order to detect when the framing detection signal 32 is not output during the °゛L" period (when there is no data or the frames cannot match). The shift clock 72 detects the framing. Renostar? Take it into θ.

FIG. 10 shows the relationship between the framing detection signal 32 and the detection shift clock 72. 10'0-1 in Figure 10
04 is equivalent to that in FIG. 32 (a)
is the framing detection signal when synchronization is achieved by the framing signal. At the end of the framing signal 103, it changes from °゛L" to TIHj+, and "1" is read by the detection shift clock 72.,?2( b
) is a framing detection signal when synchronization cannot be achieved by the framing signal, and remains unchanged at "'L", and II OII is read into the framing detection register 7θ by the detection shift clock 72.

The framing detection register 70 is a 12-bit shift register, with each bit corresponding to a 79-bit number of 74-bit data. In addition, the buffer memory areas for storing the Δ and g numbers and the uncorrected data are also corresponding to each other.
FIG. 8 shows an example of the correspondence between the bits and kerat numbers of the framing detection register 70 and the buffer memory area.

Although 34 addresses are sufficient for the data area for one node, 64 addresses are reserved in FIG. 8 to facilitate the configuration of the address generation circuit. Therefore, of the 64th data area of 1 Nog Kerato, the latter 30 areas are unused. When the writing of 12.times.12 is completed, 111° and 112 in FIG. 7 become "H" from II L II, and the first operation mode ends.

In FIG. 7, vertical blanking signal 11 or signal 1
12 is reversed from II L II to tt H", the second
enters operating mode. Before entering the first operating mode, a signal designating a packet to be corrected is sent from the CPU to the index register 60. For this reason, the CPU
From CPU data bus 20, data bus control circuit 22
, (the path control signal 28 is
It operates to connect the data bus 20 and the local data bus 23. ) and local data bus 23
8 bits of data to be set are given in parallel via the CPU, and written to the index register 60 by a write pulse 63 from the CPU. If the index register is 12 bits, it is necessary to set it twice.

In this way, the serial output 6 of the index register 60 and the serial output 3 of the framing detection register 70 are ANDed to determine whether or not the item or kerat that is about to be corrected is the one to be corrected. can be known. The timing control circuit 27 does not enter the correction operation (second operation mode + third operation mode + fourth operation mode) when the correction index signal 75 is °°O'', and the index shift clock 62 and the detection shift clock 7 index register 60 by
and shifts the contents of the framing detection register 70,
It also sends an address update signal 56 to the address generation circuit,
The address is updated to the first address of the next 4 kets.

When the correction index signal is “1”, the second
．． Enter the third and fourth operating modes.

Also in the second operation mode, the data/gas control circuit 22 in FIG. 3 operates to separate 20 and 23.
The address switching circuit 24 operates to select the automatic address signal 26 given from the address generation circuit 25 and supply it to the address input terminal of the buffer memory 29.

In the second operation mode, the uncorrected packet data stored in the buffer memory 29 as shown in FIG. The uncorrected data 35 is supplied to the first input terminal of the adder 37 via the data input terminal of the data register 34 and the load gate circuit 38 .

Convert 8 bits from buffer memory 29 34 times (1 bucket) = 272 bits from parallel to serial and transfer to data register 3
4 and syndrome register 36. The timing control circuit 27 outputs an address update signal 56 for each read, and increases the value of the address generation circuit 25 by +1.
do.

Erroneous detection can be performed by the syndrome thus formed.

Termination of the second operating mode, i.e. data register 34
When data loading to the syndrome register 36 is completed, the third operation mode is automatically entered.

In the third operation mode, a correction clock signal 43 is generated from the timing control circuit 27 to shift the data register 34 and the data register 36. Also, the load gate circuit 38 is turned off, while the collect gate circuit 4
5 turns on. Error correction is performed using exclusive OR circuit 48 (2
(modulo adder)). The error correction signal 47 is a linear combination of 17 states of the 82 syndrome registers, and is outputted by the majority circuit 41 among the 17 states.

However, this error correction signal is the correct signal 46.
In response to this, the signal is configured to pass only during an error correction operation. Furthermore, when there is an error in that bit, the error correction signal 47 modifies the syndrome register 36 to remove the influence of that bit. The corrected data 49 is fed back to the data input terminal of the data register 34 again.

Note that, prior to correction, the syndrome register 36 is incremented by one pint. This is used as an error correction code (2
73,191) Select the majority code and decrease by 1 bit (2
72,190) This is due to the fact that it is made into a code.

In this way, when a 272-bit shift (273 bits/shift in the syndrome register) is missed, a signal of 1 packet) - 272 bits is restored,
The third operating mode ends.

The error correction method of this embodiment is basically based on the patent application No. 58-6.
579, as explained in Section 9.

When the third operating mode ends, the fourth operating mode is automatically entered. In the fourth operation mode, the corrected data is serial-parallel converted and stored in the buffer memory 29. Prior to sending the corrected data, an error status signal 59 is sent.
is sent to the local data path 23 and stored at the leading address of the area in the graph memory 29 that stores the corresponding 3-digit corrected data. Thereafter, 272-bit corrected data is sent out, but since the 82-bit parity bit is not necessary in the corrected data, only 190 information bits are written into the buffer memory 29. In the fourth operation mode, since the error correction signal is prohibited by the collect signal 46, the corrected data secured in the data register 34 becomes the corrected data 49 and is sent to the transfer circuit 30. The data is serial-to-parallel converted and stored in the buffer memory 29 via the local data storage 23.

Thus, the corrected data is 190 per kerat.
The pit data is divided into 24 bytes, and 25 bytes are written, including 1 byte of error status signal 59. At this time, every time one byte is sent, a write pulse 52 and an automatic address signal 26 are sent from the timing control circuit 27.
is applied to the buffer memory 29. Thereafter, an address update signal pulse 56 is given to the address generation circuit 3o to update the automatic address signal 26. Also in the fourth operation mode, the address switching circuit 24 selects the automatic address signal 26 and supplies it to the input terminal of the buffer memory 29. Further, the data bus control circuit 22 operates to separate the 2 degrees and 23. As explained above, the second, third and fourth operation modes are a series of operations regarding data of one packet. When these series of operations are completed, the index register 6o and the framing detection register 70 are shifted, and the automatic address of the address generation circuit 25 is updated to the address of the next packet. It is determined based on the correction index signal 75 whether the new packet is something that should be corrected or not. Correction index signal 75 is on
If so, there is no need to correct it and index register 6o
Then, the framing detection register 7o is further shifted by one bit, the automatic address signal 26 is updated to the address of the next packet, and the correction index signal 75 of the next packet is updated.
will be checked. Correction index signal 75
When is 1'', the second, third and fourth operation modes are entered. Similarly, when the work for 12 packets is completed, the correction is completed.

Then, the corrected data is stored in the corrected data area of the buffer memory 29 as shown in FIG. In FIG. 9, 64 addresses are reserved as an area for one packet, but in reality only 25 bytes are used.

When the correction of all and keratos to be corrected in FIG. 3 is completed, the timing control circuit 27 issues a status signal 55.
This indicates to the PU that the CPU may read the buffer memory 29.

The fifth operating mode is a mode in which the CPU detects the status signal 55 and the C'PU reads the buffer memory. In this mode, the CPU provides a data request signal 58 to the timing control circuit 27. As a result, the timing control circuit 27
A bus control signal 28 is provided to connect the address bus 2 and the local data bus 23 and to inhibit the automatic address signal 26 and supply the signal of the address bus 2 of the CPU to the rubber buffer memory 29. In this way, the CPU can read the output data of the buffer memory 29 via the local data bus 23 and the CPU data bus 20. As explained above, in the first operational embodiment, the CPU can obtain corrected data simply by first setting the index register.

A circuit configuration diagram of the second operational example is shown in FIG. 1st
In Fig. 1, 20 to 74 are equivalent to the same numbers in Fig. 3, and 76 is a correction index signal, and the output of the index reno star 60 is sent as is to the timing control circuit, and is used as a correction index signal. Become.

80 to 83 are equivalent to those in FIGS. 2 and 3, but if the second operational embodiment is selected, 82 is set in advance as a parameter.
The mode register 80 is set so that ", 83 becomes '°0".

90 is a command register, 91 is a =+vnd register write signal, and 92 is a correction start signal.

The difference from the first operational example is that the first operational example (FIG. 3) converts serial received data 31 into a framing detection signal 3.
2 and a synchronized clock 33, the signal is input to the data transfer circuit 30, serial-to-parallel converted, and written into the buffer memory 29, and from the vertical blanking signal or a signal similar to the vertical blanking signal 56 °'L''. The correction operation (second, third, and fourth operation modes) was started by detecting the rise to "H", but in the second operation example, the data before correction is written to the buffer memory 29 and the correction is performed. The point is that the CPU handles everything up to the input of the start signal.

The operation of the second operation example will be described below with the operation of the CPU writing uncorrected data into the buffer memory 29 as the sixth operation mode.

In the tr sixth operation mode, the data bus control circuit 22 connects the local data bus 23 to the CPU data bus 20, and the address switching circuit 24 completely inhibits the output of the automatic address signal 26 from the address generation circuit 25, and connects the CPU address bus 21 to the address switching circuit 24. A bus control signal 28 is provided so that the signal enters the buffer memory 290 input terminal.

Therefore, I want to correct the CPU by the number of Kerato.

can be written to the file memory 29. The address to be written is the same as shown in FIG. 8, and by writing the address i corresponding to the address of the buffer memory 29 storing the uncorrected data to the index register 6o, the error correction decoding circuit should be corrected. Packet data can be given.

The CPU stores the uncorrected data in the buffer memory 29,
When the data of the ieket to be corrected has been set in the index register 6o, it is output to the CPU data bus 20 and the local data bus 23, and a correction start signal 92 is sent to the command register 9 by the command reno star write signal 91.
Set to o. When the timing control circuit 27 receives the correction start signal 92 from the command register 9o, the timing control circuit 27 causes the data bus control circuit to disconnect the CPU data bus 20 and the local data bus 23, and the address switching circuit 23 disconnects the automatic address signal 26 from the address generation circuit 25. The bus control signal 28 is applied to the input terminal of the buffer memory 29.
Output. Thus, the sixth operation mode is completed, and thereafter, the correction index signal 76 is checked in the same way as in the first embodiment, and the process proceeds sequentially to the second, third, fourth and fifth operation modes.

As explained above, in the second operational example, the CPU controls the writing of uncorrected data to the buffer memory 29, the writing of 79 bits of data to be corrected to the index register 60, and the timing of starting correction. This is the difference from the first operational example.

FIG. 12 shows a circuit configuration diagram of a third operational example of the present invention. The feature of the third operational embodiment is that the CPU directly writes one packet worth of data to the error correction decoding circuit, performs correction decoding, and directly reads the data from the IA ticket under the control of the CPU. This is to perform corrective decoding.

In FIG. 12, 93 is a load start signal indicating that the CPU writes data to the error correction decoding circuit, 94 is a read start signal indicating that the CPU reads data from the error correction decoding circuit, and 83 is a read start signal indicating that the CPU reads data from the error correction decoding circuit. This is a mode 2 designation signal indicating the operation mode No. 3. 95 is a data write signal from the CPU, 96 is a data read signal from the CPU, and 97 is a ready signal. The other numbers are the same signals as in FIGS. 2, 3, and 11.

Next, the operation shown in FIG. 12 will be explained.

First, the CPU sends data specifying the third operation example to the CPU.
It is output onto the U data bus 20 and set in the mode register 80 by the mode register write signal 81. Further, a mode 2 designation signal 83 is output from the mode register 80 to the timing control circuit 27, and preparations for entering the third embodiment are completed.

The CPU sets a load start signal in the command register 90 to start writing the uncorrected data.

When the command register 90 and the command register start signal 93 are given to the timing control circuit 27, the timing control circuit 2
A syndrome register reset signal 44 is output from 7, the CPU enters a state of waiting for data to be written, and a ready signal 97 is output.

When the ready signal 97 is output, the CPU outputs uncorrected data to the CPU data bus 20 in units of 8 bits (1 byte), and sets it in the data transfer circuit 30 using the data write signal 95.

The data write signal 95 is also given to the timing control circuit 27, and the timing control circuit receives the load clock signal 42.
The uncorrected data 35 which has been parallel-to-serial converted by the data transfer circuit 30 is supplied to the first input terminal of the adder 37 via the data register 34 and the load gate circuit 38.

The CPU repeatedly writes the uncorrected data 34 times, 8 bits at a time, and converts the 272 bits from parallel to serial to the data register 34 and syndrome register 36.
Roadsle to.

When 34 writes of 8 bits each are completed, the CPU outputs data indicating the start of correction to the CPU data bus 20 and sets it in the command register write signal 91 in the command register write signal 90. When a correction start signal 92 is applied from the command register 90 to the timing control circuit 27, correction decoding is started. The corrective operation is the same as the third mode of operation in the first operational embodiment. When the correction is completed, a ready signal is output, allowing the CPU to know that the correction has been completed.

The CPU can read the error status signal 59 through the data transfer circuit 30 and can know whether all the errors have been corrected. If all the errors have been corrected, the CPU advances to the next corrected data reading operation mode. If errors remain, there is no need to read the corrected data.

In the corrected data read mode, the CPU provides a read start signal to the command register 90 via the data bus 20. The read start signal 94 is sent to the timing control circuit 2.
7, the timing control circuit issues a loading clock signal 42, sends the corrected data stored in the data register 34 to the data transfer circuit 30, and outputs a ready signal 97.

When the ready signal 92 is output, the CPU issues a data read signal 96 and reads out the serial-to-parallel converted 8-bit data from the data transfer circuit via the data bus 20.

The data read signal 96 is also applied to the timing control circuit, and the timing control circuit again sends the corrected data from the data register 34 to the data transfer circuit 30 and outputs a ready signal 97.

The operation of the third embodiment is completed by reading out the 190-bit data in the CPU data section in 24 times.

(Effects of the Invention) As explained above, according to the present invention, it is possible to select the optimal operation mode depending on the number of packets to be transmitted and the transmission method. It can be reduced.

The present invention can be applied not only to code-based teletext receivers but also to other majority code decoding circuits.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of the conventional technology, FIG. 2 is a circuit diagram for explaining the method of switching operation modes, FIG. 3 is a circuit configuration diagram of the first operational embodiment of the present invention, and FIG. 4 6 is a flowchart for explaining the first operational example of the present invention, FIG. 5 is a timing diagram of packet reception data of character code broadcasting, and FIGS. 7 and 10 are for explaining the present invention. 8 is a mapping diagram when storing uncorrected data in the buffer memory, FIG. 9 is a mapping diagram when storing post-corrected data in the buffer memory, and FIG. 11 is a mapping diagram when storing the corrected data in the buffer memory.
FIG. 12 is a circuit diagram of a third operational embodiment of the present invention. 1...CPU pass line, 2...Output port, 3...
・Input port, 4...Error correction circuit, 20...CP
U data bus, 21...CPTJ 7 trespass,
22... Data bus control circuit, 23... Local data bus, 24... Address switching circuit, 25... Address generation circuit, 26... Automatic address signal, 27.
...Timing control circuit, 2B...Path control signal, 29
...Buffer memory, 30...Data transfer circuit, 31
... Serial reception data, 32 ... Framing detection signal, 33 ... Synchronization clock, 34 ... Data register, 35 ... Data before correction, 36 ... Syndrome register, 37 ... Adder, 38...Load gate circuit, 39...Load gate signal, 40...Ndrome register signal, 41...Majority circuit, 42...
- Load block signal, 43... Clock signal for collect, 44... Clear signal, 45... Collect gate circuit, 46... Collect gate signal, 47... Error correction signal, 48... Adder , 49...Data after correction, 50...Clock signal, 51...Write pulse signal, 52...Write/write signal, 53...Vertical blanking signal or vertical blanking signal similar signals,
54...Horizontal synchronization signal or horizontal blanking signal, 5
5... Status signal, 56° 57... Address update signal, 58... Data request signal from CPU, 59... Error signal, 60... Index register, 61, 73, 75.76...・Correction index signal, 62... Index shift black signal, 63.
...Writing nogle signal from CPU, 70...Framing detection register, 71...Detection shift clock signal, 22...Clock signal, 74...And gate, 8o...Mode register, 8I ...Mode register write signal, 82...Mode 1 designation signal, 8
3...Mode 2 designation signal, 90...Command register, 91...Command register write signal, 92...
・Correction start signal, 93...Load start signal, 94...
・Read start signal, 95...Data write signal from CPU, 96...Data read signal from CPU, 97
... Ready signal, 100 ... Horizontal synchronization signal, 101
...Color burst, 102...Clock run in,
103...Framing signal, 104...Data bit, 110...Vertical synchronization signal, 111...Vertical blanking signal, 112...Signal generated from 111. Patent Applicant Oki Electric Industry Co., Ltd. Japan Broadcasting Corporation 40 <+I+I6It>03 04 1 12 8°Sut Date 67 68 Figure 9 Showa Year Month Date Commissioner of the Japan Patent Office 1, Indication of Case 1982 Patent Application No. 60916 2. Invention title error correction decoding circuit 3. Relationship with the amended person case Patent application office (105) 1-7-12 Toranomon, Minato-ku, Tokyo
No. 5, "Detailed Description of the Invention" column of the specification to be amended and "Drawings" 4, Figure 6, Contents of the amendment As shown in the attached sheet 6, Contents of the amendment (1) r8 on page 5, line 16 of the same document /6J is r8
] Corrected as 6J. (2) “Operating mode” on page 13 of the same book, lines 8 to 9.
I corrected it to "movement". (3) In the same book, page 13, line 12, "first operation mode" is corrected to "first operation." (4) In the same book, page 13, line 12, "■ operation mode" is corrected to "■ operation." (5) In the same book, page 13, line 15, it says "4th mode J." (6) In the same book, page 13, lines 15 to 16, the phrase “■ operation mode” is corrected to “■ operation.” (7) The same book, page 14 The phrase "fourth operation mode" on the third line of the page should be corrected to read "the fourth operation." (8) The phrase "■ operation mode" on the third to fourth lines of page 14 of the same book should be corrected. (9) Correct “operation mode” on page 14, line 5 of the same book to “operation.” αli Correct “operation mode” on page 14, line 12 of the same book. 02 Correct "1 operation mode" on page 4, line 14 of the same book to "operation". 02 r2.2+' on page 15, line 19 of the same book l, 22
..." is corrected to "α, α+1.α+2・”. αj In the same book, page 16, line 17, “2nd address” is replaced with “
Correct it to "address α". α→ In the same book, page 19, line 11, "operation mode" is corrected to "operation". αυ In the same book, page 19, lines 13 to 14, the phrase ``second operation mode'' is corrected to read ``1 second operation''. H Ibid., page 19, line 14, "first operation mode" is corrected to "first operation." I, 1. In the same book, page 19, line 19, the phrase ``operation mode'' is corrected to ``operation.'' Q → In the same book, page 20, lines 13 to 14, the phrase [second operation mode, tenth third operation mode, tenth fourth operation mode] is replaced with “second operation of child 3, movement of child 4”. ” he corrected. α ``Operating mode'' in the 1st line to 2nd line of page 21 of the same book.
I corrected it to "movement". (b) In the third line of page 21 of the same book, the phrase "operation mode" is amended to read "operation." Q]) On page 21, line 9 of the same book, the phrase "operation mode" is corrected to "operation." (b) In the fourth line of page 22 of the same book, the phrase "operation mode" is amended to read "operation." (b) In the same book, page 22, lines 6 to 7, the phrase "operation mode" is corrected to "operation." In the same book, page 22, line 8, "operation mode" is corrected to "operation." (c) On page 23, line 14 of the same book, the phrase "operation mode" is corrected to "operation." (c) On page 23, line 17 of the same book, the phrase "operation mode" is corrected to "operation." (b) On page 23, line 18 of the same book, the phrase "operation mode" is corrected to "operation." (C) In the same book, page 24, line 8, the phrase ``operation mode'' is corrected to read ``1 operation.'' (c) In the third line of page 25 of the same book, the phrase "operation mode" is corrected to "operation." (G) "Operation mode" in the first to second lines of page 26 of the same book.
I corrected it to "movement". 00 In the same book, page 26, line 16, "operation mode" is corrected to "operation." 0 Proverbs In the same book, page 27, line 8, the phrase ``operation mode'' is corrected to ``operation.'' 0] On page 27, line 10 of the same book, the phrase ``It is a mode.'' is corrected to ``It is an action.'' (b) “In this mode” on page 27, line 10 of the same book.
The phrase "in this action" should be corrected. 0 o'clock In the third line of page 29 of the same book, the phrase "operation mode" is corrected to "operation." OQ In the same book, page 29, line 8, "operation mode" is corrected to "operation." 0no In the same book, page 29, line 10, the phrase "operation mode" is corrected to "operation." 0 → In the same book, page 30, line 17, "operation mode" is corrected to "operation." 0 → In the same book, page 30, line 19, "operation mode" is corrected to "operation." 0Q "Mode 2 designation signal 83" on page 32, line 7 of the same book
The text has been corrected to read "mode 3 designation signal 83." 0]) In the same book, page 33, line 18, "operation mode" is corrected to "operation." 0) Correct the drawing (Figure 4) to the attached sheet.

Claims (1)

[Claims] The device includes a syndrome register, a data renosk, a majority circuit, and an operation mode designation means, and converts uncorrected data that is serially input into serial to parallel form and temporarily stores it in a buffer memory. Next, the uncorrected data stored in the buffer memory is read out from the buffer memory, error correction is performed, and the uncorrected data is stored in the buffer memory again. A second operation mode reads data from the buffer memory, performs error correction, and then stores it in the buffer memory, and a second operation mode reads uncorrected data sent from a CPU, etc., corrects errors, and sends the corrected data to a CPU, etc. An error correction decoding circuit that corrects errors in code data based on a majority error correction method using a difference set cyclic code, characterized in that at least two or more operation modes can be selected from among the three operation modes. .