JPS60206226A - Code error correcting and decoding circuit - Google Patents

Abstract

PURPOSE:To shorten a correction time, and adding error information on the number of corrections to corrected data and decide a received signal by counting the number of corrected bits and ending correcting operation when the count result exceeds a specific value. CONSTITUTION:An error correction signal 40 outputted from a majority decision making circuit corresponds to a collect gate signal 39 and is passed through a collect gate 38 only during error correcting operation. A correction number counter 51 counts this signal 40, and sends a correction number signal 52 to a data transfer circuit 20 and also outputs a correction over signal 53 indicating the number of corrections exceeds the specific value to a timing control circuit 17 and a data transfer circuit 20. Then it is stopped after the correcting operation. Further, data before being corrected is read out of a buffer memory 19 and loaded in a syndrome register 26 and a data register 24 to make error corrections, and the corrected data 42 is written in the memory 19 together with additional error information.

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to code error control suitable for coded teletext broadcasting in which character/graphic information coded as a digital signal is multiplexed transmitted during the vertical blanking period of a TV signal. This occurs especially in transmission lines.

(Technical Background) As an error correction method for this type of service that uses a TV transmission channel, one packet consists of 272 bits, and a data signal of 272 data bits, 190 information bits, and 82 bits of base bits is used. The method of forming, transmitting, and decoding is based on Japanese Patent Application No. 58-6579 and Japanese Patent Application No. 58-6579.
No. 8-54002 and Japanese Patent Application No. 58-90017.

FIG. 1 shows the configuration of the error correction decoding circuit disclosed herein. In FIG. 1, 1 is a CPU pass line connected to a CPU (not shown), and is connected to an input terminal of an output port 20 and an output terminal of an input port 3. The output port 2 outputs the uncorrected data 5 to the error correction circuit 4.
supply to. The error correction circuit 4 is a parallel-to-serial conversion circuit, and a direct-to-serial conversion circuit.
It includes a parallel conversion circuit, a syndrome register, a data register, etc., and performs an operation to correct the (272,190) code. The error correction circuit 4 supplies corrected data 6 and an error status signal 7 to the input port 3.

Next, the operation shown in FIG. 1 will be explained. The uncorrected data is supplied from the CPU to the output port 2 via the CPU path line 1. The uncorrected data received by the output port 2 is corrected by the error correction circuit 4, resulting in the corrected data 6, which is supplied to the input port 3 and delivered to the CPH via the CPU path line 1.

At the same time, the error correction circuit 4, after correcting one packet of error,
In order to indicate whether the syndrome register has become O", an error status signal 7 is generated and sent to the CPU line 1 via input port 3. If the syndrome register is O", the uncorrected data is This means that there is no error in the data before correction, or even if there is an error in the data before correction, it has been correctly corrected, so by detecting the error status signal, the CPU can know whether the data after correction is correct or not. .

However, the above-mentioned conventional technology has the following drawbacks.

In FIG. 1, assuming that signals are exchanged between the CPU and the error correction circuit via the CPU path in units of, for example, 8 bits)=,=1-1 bytes, then 1=9 bits=272 bits.
It takes 34 bits of time to supply the uncorrected bit data from the CPU to the error correction decoding circuit, and it takes 34 bits of time to supply the uncorrected bit data from the CPU to the error correction decoding circuit. It takes a similar amount of time to supply.

Furthermore, in Japanese teletext broadcasting, up to 12
It is possible to transmit up to packets, and if you try to process them all, C
The data transfer time between the PU and the error correction decoding circuit is as long as 34 byte times x 2 x 12 = 816 byte times. These transfers are performed by the CPU's write and read commands, and the CPU is unable to perform other processing during this transfer time, so it is necessary to receive and display teletext.
This will cause problems in processing such as code deciphering and display format generation. In particular, since the error correction operation in the error correction circuit 4 is performed asynchronously with the CPU operation, the CPU always detects whether or not the error correction for 4 kets has been completed, and the error correction is completed. Then, the operation must immediately shift to reading data from the input port 3, so other processing by the CPU is interrupted frequently and intermittently.

As explained above, in the conventional technology shown in FIG.
The disadvantage was that it placed a heavy burden on the PU and required much of the processing time, making it virtually impossible to perform all the processing necessary to receive and display teletext. In the error correction decoding circuit shown,
After the correction, it was only possible to know whether the correction was made correctly or not, and it was not possible to know whether the missing bits were corrected or not. In order to convert the received code data into a digital code, it is necessary to determine whether the signal value at each point in time is 1" or not.
It is necessary to determine whether the threshold voltage is 0", and if the threshold voltage for determination is not selected correctly, the correct digital code will not be generated.In order to set the threshold voltage correctly, it is necessary to determine the degree of error at a certain threshold voltage. I need to know and give feedback on this.

Thirdly, Japanese Patent Application No. 58-54002 discloses an invention that repeats correction by changing the decision threshold of the majority decision circuit. Even if you make changes and make corrections over and over again, it cannot be corrected, so it is a waste of time.

In addition, when the number of erroneous bits is large, each time the correction operation is repeated, the erroneous bits may be erroneously corrected, resulting in an increase in the number of erroneous bits. In such a case, even if the code is decoded and displayed using data before correction, the result will be a display with many errors.

(Object of the Invention) An object of the present invention is to provide a correction number counter that counts the number of corrected bits, and to perform a correction operation when the count exceeds a predetermined value. The purpose of the present invention is to shorten the correction time and add error information such as the number of corrections to the corrected data to make it easier to discriminate the received signal.

(Example) A circuit diagram of the first embodiment of the present invention is shown in FIG.

In FIG. 2, 10 is a data bus of a CPU (not shown), and 11 is an address bus of the CPU. The data bus 10 of the CPU is connected to the first input/output terminal of the data bus control circuit 12, and the data bus 10 is connected to the second input/output terminal of the data bus control circuit 12.
The input/output terminal of is local data/? connected to the bus 13. The address node 11 of the CPU is connected to a first input terminal of an address switching circuit 14, and an automatic address signal 16 is supplied from an address generation circuit 15 to a second input terminal of the address switching circuit 14. =. The address switching circuit 14 selects between the CPU address signal applied to the first input terminal and the automatic address signal 16 applied to the second input terminal according to the Noise control signal 18 supplied from the timing control circuit 17. At some point, one of the outputs 1 is selected and a memory address signal is supplied to the address input terminal of the buffer memory 19.

The local data node 13 also includes the log file memory 1.
9 and the data input/output terminal of the data transfer circuit 20.
The buffer memory and data transfer circuit are capable of exchanging data with each other.

The data transfer circuit 20 includes serial reception data 21, which is received by a character code broadcast receiving unit (not shown) and extracted, and frame synchronization is performed according to the framing signal of the character code broadcast. A framing detection signal 22 indicating that a frame has been taken, and a synchronization clock 23 which is cyclically synchronized with the clock run-in of character code broadcasting are supplied.

The data register 24 is a register for storing 190 bits of information bits out of 272 bits of packet received data, or 272 bits of 9 packet received data, and is converted from parallel to serial by the data transfer circuit 20. The uncorrected data 25 is received and shifted.

The syndrome register 26 is equivalent to the one disclosed in FIG.
There is a feedback loop via an adder 27 modulo 2. 28 is a load gate circuit, and a load gate signal 29 is supplied from the timing control circuit 17.
This controls whether or not the uncorrected data 25 is supplied to the syndrome register 26 via the adder 27.

30 is a syndrome register signal, 31 is a majority circuit,
32 is a threshold signal, 33 is a threshold generation circuit, 34 is a threshold clock for updating the threshold, 35 is
a loading clock signal 36 for loading data into the syndrome register 26 and data register 24;
37 is a correction clock signal, 37 is a clear signal for clearing the syndrome register 26, and 38 is a result signal of the majority circuit 31. A collect gate signal 39 indicates whether or not to supply the result signal of the majority circuit 31 to the adder 41 as an error correction signal 40. 42 is a corrected data, 43 is a clock signal for performing serial-to-parallel/parallel-to-serial conversion, and 44 is for receiving data. 45 is a write/write signal for writing to the buffer memory. 46 is a vertical blanking signal;
Alternatively, 47 is a horizontal synchronization signal or a horizontal blanking signal similar to a vertical blanking signal, and 48 is a status signal indicating the operating state.

49 is a register that is set when the syndrome register becomes 0", and its output signal, an error status signal 50, is supplied to the data transfer circuit 20. Further, 51 is a register that corrects a bit error. A correction number counter for counting the number of times, and a correction number signal 5
2 is sent to the data transfer circuit 20, and at the same time, a correction au signal 53 indicating that the number of corrections exceeds a predetermined value is sent to the timing control circuit 17 and the data transfer circuit 20.

54 and 55 are address update signals, and 56 is a CPU data request signal.

Next, the operation shown in FIG. 2 will be explained.

The operating modes in Figure 2 can be roughly divided into: ∎ Serial-to-parallel conversion of serial received data and writing to the grapher memory, ∎ Reading uncorrected data from the buffer memory and loading into the data register and syndrome register, ∎ Data Four operations: 1. Correct errors by cycling through registers and syndrome registers, changing the majority decision threshold, and repeating the cycling; 1. Writing corrected data to buffer memory. Consists of modes. Also, the fifth
In the operation mode, the CPU reads the corrected data stored in the buffer memory.

FIG. 3 is for explaining the first operation mode, and shows the timing of packet reception data of character code broadcasting. In FIG. 3, 7o is a horizontal synchronization signal, 71 is a color burst, 72 is a 16-bit clock run-in for clock synchronization, 73 is a framing signal for frame synchronization, and 74 is 272-bit data. These bits form the serial reception data 21.

The data transfer circuit 20 receives the framing detection signal 22 indicating that frame synchronization has been achieved by the framing signal 73, and can know the start time of serially received data. Also, since the synchronized clock 23 synchronized by the clock run-in 72 is received, the 27
2-bit data bit time, serial reception data 21 is taken in sequentially using a synchronous clock and converted into serial-to-parallel data ・Capacity of local data bus 13: 8 buffers The beginning of the area for storing uncorrected data for packets with memory. If the address is α, the data transfer circuit 2o gives the address update signal 55 to the address generation circuit 15 every time 8-bit data is sent.
The automatic address signal is α+1. α+2. α+3. ...Step by step slowly. Furthermore, each time these 8-bit data are sent out, a write i4 pulse signal 44 is supplied to the buffer memory as a write i4 pulse signal 45 via the timing control circuit 17.

In the first operation mode, the data bus control circuit 12
operates to separate signals 10 and 13, so that the data bus of the CPU can be used for other purposes, while the address switching circuit 14 selects between the two input signals the automatic address supplied from the address generation circuit 15. It operates to select signal 16 and transmit it to the address input terminal of buffer memory 19.

In this way, the serial reception data 21 of 1 packet = 272 bits is serial-parallel converted and stored in the buffer memory 19 at α.
Data is written sequentially starting from the address. The operation flow for storing one packet worth of received data in the buffer memory 19 is shown in the fourth section.
As shown in the figure. If 8 bits = 1 byte are processed and written, the addresses that are repeatedly stored 272/8=34 times in one packet are from address α to α+33.

In Japanese character code broadcasting, up to 1214 bits of data can be sent during one vertical blanking time, as shown in FIG. In Figure 5, 80
81 is a vertical synchronizing signal, 81 is a vertical blanking signal, and 82 is a signal generated from the vertical blanking signal 81, which is a signal obtained by extracting only the latter half 12H of the vertical blanking time 21H.

In Japanese character code broadcasting, data can be sent during the time when the signal 82 is "L", that is, during the latter half 12H of the vertical blanking time.

Signal 46 in FIG. 2 is, for example, signal 82.

In the address generation circuit 15, the signal 82, that is, 46 is 'L''
During this period, the horizontal synchronization signal 47 is counted and a partial signal of the automatic address signal is provided. Therefore, when data transfer for one packet is completed, the address is switched to the address where the next 9 bits of data are to be stored. Similarly, the operation flow shown in FIG. 5 is repeated 12 times, and 12 packets of uncorrected data are stored in the buffer memory 19. FIG. 6 shows an example of the correspondence between a packet number and an address in the buffer memory that stores uncorrected data of that packet number. 1. Address 34 is sufficient as the data area for the mother packet, but in order to simplify the configuration of the address generation circuit, the 6th address is sufficient.
In the figure, 64 addresses are reserved, so of the 64 addresses of one packet data area, the latter 30 addresses are unused. When writing of the uncorrected data corresponding to 12.times. of kerats to the buffer memory is completed, the signals 81 and 82, ie, 46 in FIG. 5 change from 'L' to 'H#', and the first operation mode ends.

In FIG. 5, vertical blanking signal 81 or signal 8
2, that is, 46 is inverted from II L H to "H", the second operating mode is entered. Also in the second operation mode, the data bus control circuit 12 in FIG.
The address switching circuit 14 operates to select the automatic address signal applied from the address generation circuit 15 and supply it to the address input terminal of the buffer memory 19.゛Also, the address generation circuit 15
The address is updated by an address update signal from the timing control circuit 17.

In the second operation mode, θ of the buffer memory 19
Read data 8 bits at a time starting from the address. The data transfer circuit 20 performs parallel-to-serial conversion, and the uncorrected data 25 is supplied to the first input terminal of the adder 27 via the data input terminal of the data register 24 and the load gate circuit 28. . 8 in one read from pack memory
By transferring the bits 34 times, 272 bits (1 or kerato) are parallel-to-serial converted and loaded into the data register 24 and the syndrome register 26. Error detection can be performed using the syndrome thus formed. That is, if all the syndrome register signals 30 are "O", there is no error in the data, and if any bit is "P1", there is an error in the data.If there is no error, the third operation mode is activated. Although it is not necessary to perform the correction operation, in this embodiment, the third operation mode is entered even in this case.

The error correction method of this embodiment is basically based on the patent application No. 58-6.
This is as explained in Japanese Patent Application No. 58-54002, and the point that correction is performed by sequentially lowering the threshold value is as explained in Japanese Patent Application No. 58-54002. Some of the features of this embodiment are that a correction number counter is provided to count the number of error corrections, that a correction number signal and an error status signal indicating the number of corrections are sent out, and that when the number of corrections exceeds a predetermined value, This is to stop the corrective action.

The second operation mode and the third operation mode are paired, and when the second operation mode ends, that is, the data loading to the data register 24 and the syndrome register 26 is completed, the third operation mode is automatically started. Enter the mode. In the third operation mode, a correction clock signal 36 is generated from the timing control circuit 17 and the data register 24
and the syndrome register 26. Also, the load gate circuit 28 is turned off, while the collect gate circuit 38 is turned on. Error correction is done using an exclusive OR circuit (
Adder modulo 2) Perform 41 steps. The error correction signal 4o is output by combining the states of the 82 syndrome registers into 17 linear combinations, and comparing the 17 states with a threshold value (the first threshold value is 17) by the majority circuit 3. It is something that

However, this error correction signal 40 is connected to the collect gate signal 3.
9 and is configured to pass only during an error correction operation. Furthermore, when there is an error in that bit, the error correction signal 40 modifies the syndrome register 26 to remove the influence of that bit. The corrected data 42 is fed back to the data input terminal of the data register 24 again.

Note that, prior to correction, the syndrome register 26 is incremented by one bit. This is used as an error correction code (
273,191) Select the majority code and decrease by 1 pit (
272,190) code. When a 272-bit shift (a 273-bit shift in the syndrome register) is performed in this manner, a signal for 17th kerat 2 and 2 bits is restored. At this time, by checking the error status signal 5o, it is possible to determine whether or not the error has been corrected correctly. If all the bits in the syndrome register 26 are not 0'', it means that an error code still exists in some bit position, so the error code correction operation is performed again.However, at this time, the timing control circuit 12 A threshold clock is given, and the threshold generation circuit 33 subtracts and counts this, so the threshold value is reduced by 1. In other words, the threshold value is set to 16, and the error correction is performed using the previous threshold value of 17. Use data.

The above operations are carried out until the threshold value 9 is completed.

However, when all the bits in the syndrome register 26 (D) become 0", it means that the error correction operation has been completed. In other words, the data at that point is the correct value, so from then on, the error correction operation will be completed. There is no need to pass through a correction circuit.

Conversely, if the number of bits to be corrected is abnormally large, it means that there were abnormally many errors υ in the original data, and correction is impossible, so corrections must be made before threshold 9 ends. It is better to cancel it. For this purpose, the correction number counter 51 counts the number of corrections, and when the number exceeds a predetermined value, it issues a correction over signal 53 and supplies it to the timing control circuit 17.

The flowchart of the operation in the third operation mode is shown in the seventh section.
As shown in the figure.

As explained above, when the third operation mode ends,
The corrected data is reserved in the data register 24. When the third operating mode ends, the fourth operating mode is automatically entered. In the fourth operation mode, the corrected data is serial-parallel converted and stored in a buffer memory. Prior to sending out the corrected data, first send the error status signal 5θ, correction over signal 53, and correction number signal 52 to the local data bus 13, and select the starting address of the area in the buffer memory 19 where the corrected data is to be stored. Store in. From then on, 272-bit corrected data will be sent, but
In the corrected data, 82 bits of parity bits are unnecessary, so only 190 bits of information bits are written into the buffer memory. In the fourth operation mode, the error correction signal is prohibited by the collect gate signal 39, so the corrected data that has already been corrected and secured in the data register 24 becomes the corrected data 42. The data is sent to the data transfer circuit, serial-parallel converted, and stored in the buffer memory via the local data block 3.

As shown in Japanese Patent Application No. 58-90017, the first part of the 272-bit ij ticket data is expanded by (8°4)...
8 showing service identification and interrupt priority order by timing code
Next to the SI/IN bit, there is a 6-bit packet control (pC) for packet content identification, followed by 22 bytes of pure information bits.

Therefore, if the corrected data is packed 8 bits at a time, the first 2 bits of each byte will be mixed into the data section of the previous byte. In order to avoid this problem, in this embodiment, as in Japanese Patent Application No. 58-90017,
Two additional bits are added to the second byte of data to make it 8 bits. In this way, the corrected data consists of 24 bytes of data section 1, 1 byte of error information added to the first address, and 25 bytes of error information added to the first address.
Bytes are written.

This operational flow is shown in FIG. During the fourth operation mode described above, the timing control circuit 17 applies a write pulse 45 to the buffer memory every time one byte of data is sent from the data transfer circuit, and the address update pulse 54 applies an automatic address signal to the buffer memory. 16 is updated. Even in the fourth operation mode, the address switching circuit 14
selects the automatic address signal 16 and transfers the buffer memory 19
Supplied to the address input terminal of Also in the fourth operation mode, the data bus control circuit 12 operates to separate 10 and 13, so the CPU may perform other operations.

The second operation mode, third operation mode, and fourth operation mode described above are a series of operations. That is,
The uncorrected data of the first parent packet is read out from the buffer memory 19, loaded into the syndrome register 26 and data register 24 (second operation mode), and error correction is performed (third operation mode). Add error information to the data and write it to the buffer memory 19 (fourth
mode of operation). When these series of operations are completed, the second packet operation starts, and the second operation mode is started in the same way.
A third operation mode and a fourth operation mode are executed. From now on, perform the same movements up to 12th and Kerato. In this way, the corrected data is stored in the corrected data area of the buffer memory 7-19 as shown in FIG. In FIG. 9, 64 addresses are reserved as an area for 1 packet, but in reality only 25 bytes are used.

As shown in FIG.
and sends the buffer memory 19 to the CPU.
Indicates that it may be read.

The fifth operating mode is a mode in which the CPU detects the status signal 48 and reads the contents of the buffer memory. In this mode, the CPU provides a data request signal 56 to the timing control circuit 12. As a result, the timing control circuit 17 connects the CPU data bus 10 and the local data bus 13.
The path control signal 18 is still applied to inhibit the automatic address signal 16 and supply the signal on the CPU's address bus 11 to the buffer memory 19. Thus, the output data of the buffer memory is available to the data bus of the CPU via the local data bus 13, so that data in the area of the buffer memory addressed by the CPU can be read.

In the above explanation, an example has been shown in which 8 bits are used as the bit capacity of the local data bus 13, and data transfer between the buffer memory 19 and the data transfer circuit 20 is performed in 8-bit units. For example, 16 bits or 4 bits is also possible. However, in the case of 16 bits, it is necessary to treat the SI/IN and packet control as 14 bits at the same time so as not to shift the 14 bits by 2 bits.

Further, the data register 24 does not necessarily have to have 272 bits, but may have only 190 bits, which corresponds to information bits. However, in this case, the time corresponding to 82 bits is the clock signal for loading the data register,
and correction clock signals must be prohibited.

In addition, we have explained an example in which the error information including the error status signal, correction over signal, and correction number signal is kept within 1 byte, but if the number of bits of the correction number signal is increased, the error information becomes multiple bytes. You may do so.

Further, in this embodiment, 17 to 9 are used as threshold values for majority decision, but the gist of the present invention is not limited to specific amounts such as 17 and 9.

In the first embodiment shown above, the corrected data is sent to the adder 4
This output signal is given as serial data 42 and is configured to be serial-to-parallel converted by the data transfer circuit 20. As a second embodiment, the corrected data is shown in FIG. It is also possible to extract data in 8-bit parallel format. In Figure 10, 24.25,
40° and 4° are both the same as in FIG.

However, here, 41 is not the final corrected data, but the data register is used in the process of sequentially correcting errors by changing the threshold value, in preparation for error correction at the next threshold value. Used only for updating. In Figure 5,
Reference numeral 90 is a register of 8 bits on the leading edge side of the data register 24, and 91 is an output signal of the register 90, which is connected to the data transfer circuit 2o as final corrected data. If the data is output in 8-bit i4 parallel in this manner, the data transfer circuit 20 simply latches it at a predetermined timing and sends it to the local data bus 13.

Next, in the first embodiment, even if correct correction cannot be made even if the threshold value is lowered to 9, or even if the number of error corrections exceeds a predetermined value, the corrected data is stored in the buffer. It was stored in the corrected data area of memory. However, in such a case where correction is impossible, there are many errors in the original received data, and if error correction is performed on such received data, the error will be corrected and the error may occur. There is a possibility that it will increase.

Therefore, in the third embodiment, in such a case where correction is impossible, the uncorrected data of the packet already stored in the buffer memory is stored in the corrected data area of the packet in the buffer memory 19. Information data section 2
4. We propose adding error information to the code and writing the packet control section with a 2-bit shift. In this way, the CPU can read the data before the error increases, and since the data is shifted by 2 bits, it is easier for the CPU to process the data, and it can also know the error information. I can do it.

(Effects of the Invention) As described above, the present invention provides a buffer memory for recording uncorrected data and post-corrected data, and writes received data to the buffer memory and writes uncorrected data to the buffer memory. By providing a data transfer circuit for automatically reading the data and writing the corrected data into the Pazofa memory, the operational load on the CPU can be reduced.

Furthermore, since the number of corrected bits is counted and the correction operation is terminated when the number of corrections exceeds a predetermined value, the correction time can be shortened.

Therefore, the present invention can be applied not only to teletext receivers based on the code system, but also to crowded digital devices that use majority error correction using difference set cyclic codes.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of the prior art, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIGS. 3 and 5 are timing diagrams for explaining the embodiment, and FIGS. 8 is a flowchart for explaining the embodiment, FIGS. 6 and 9 are mapping diagrams of data stored in the buffer memory, and FIG. 10 is a circuit diagram showing the second embodiment of the present invention.01
...CPU pass line, 2...Output port, 3...
- Input port, 4...Error correction circuit, 5...Data before correction, 6...Data after correction, 7...Error status signal, 10...CPU data bus, 11...
CPU address bus, 12... Data bus control circuit, 13... Local data bus, 14... Address switching circuit, 15... Address generation circuit, Noro... Automatic address signal, 17... timing control circuit, 18
.../JS control signal, 19... buffer memory, 2
0... Data transfer circuit, 21... Serial reception data, 22... Framing detection signal, 23... Synchronous clock, 24... Data register, 25... Data before correction, 26... Syndrome Renosta, 27...
- Adder, 28... Load gate circuit, 29... Load gate signal, 30... Syndrome register signal, 31... Majority circuit, 32... Threshold signal, 3
3... Threshold generation circuit, 34... Key value clock, 35... Clock signal for loading, 36... Clock signal for correction, 37... Clear signal, 38... Collect game Collect gate signal, 39...Collect gate signal, 4
0...Error correction signal, 41...Adder, 42...
Post-correction data, 43... Clock signal, 44... Write pulse signal, 45... Write/Guru signal, 46
...Vertical blanking signal or signal similar to vertical blanking signal, 47...Horizontal synchronization signal or horizontal blanking signal, 48...Status signal, 49...
Register, 50...Error status signal, 5no...
- Correction number counter, 52...Correction number signal, 53...
Correction over signal, 54.55... Address update signal, 56... CPH data request signal, 7°...
・Horizontal synchronization signal, 71...Color burst, 72...
・Clock run-in, 73...Framing signal, 7
4...Data bit, 80...Vertical synchronization signal, 81
. . . Vertical blanking signal, 82 . . . Signal generated from vertical blanking signal 8, 9o . output signal. Figure 6 Figure 7 Figure 8 Figure 9 Continuation of page 1 O Inventor Shokukuri Heavy Oil 3-12 Moriyamachi, Kanayo-ku, Yokohama City, Japan Victor Co., Ltd. 1, Incident Indication 1988 Patent Application No. 60905 2, Name of the invention Code error correction decoding circuit 3, Relationship with the case of the person making the amendment Patent applicant address (〒105) 1-7-12 Toranomon, Minato-ku, Tokyo
Address (105) 1-7 Kaoru, Toranomon, Minato-ku, Tokyo
No. 2 No. 6, Contents of amendment (1) In the 9th line of page 21 of the specification, the phrase "first wa" is amended to read "first wa." (2) On page 25, line 13 of the same book, the phrase “special equipment” was replaced with “
Correct it as "Specific value". (3) Above the text “Figure 5” on page 26, line 7 of the same book

Claims (1)

[Claims] (1) An error correction circuit that includes a majority decision circuit, corrects errors in input code data, and transfers the corrected data; and a buffer that stores the input code data and corrected data. A code error correction decoding circuit having a memory counts the error correction signals outputted from the majority circuit, and generates a correction number signal representing the counted number of corrections and a signal indicating that the number of corrections exceeds a predetermined value. A code error correction decoding circuit comprising a correction number counter that sends a correction over signal to the correction circuit.