JPH0155786B2 - - Google Patents

Description

[Detailed Description of the Invention] (Technical Field) The present invention relates to code error control suitable for coded teletext broadcasting in which character and graphic information coded as digital signals is multiplexed transmitted during the vertical blanking period of a TV signal. In particular, the present invention relates to a code error correction decoding circuit which attempts to recover as much as possible by correcting bit errors occurring on a transmission path.

(Technical background) As an error correction method for this type of service that uses TV transmission channels, one packet consists of 272 bits, 272 data bits and 272 information bits.
A method for forming, transmitting, and decoding data signals of 190 bits and 82 bits of parity was proposed in a patent application.
58-6579 (Japanese Unexamined Patent Publication No. 133751/1983), Patent Application No. 1983-
54002 (Japanese Unexamined Patent Publication No. 181841/1983) and patent application 1982
-90017 (Japanese Unexamined Patent Publication No. 59-216388).

FIG. 1 shows the configuration of the error correction decoding circuit disclosed herein. In FIG. 1, 1 is a CPU bus line connected to a CPU (not shown),
It is connected to the input terminal of output port 2 and the output terminal of input port 3. Output port 2 supplies uncorrected data 5 to error correction circuit 4 . The error correction circuit 4 includes a parallel-to-serial conversion circuit, a serial-to-parallel conversion circuit, a syndrome register, a data register, etc., and performs an operation to correct the (272, 190) code. The error correction circuit 4 supplies corrected data 6 and an error status signal 7 to the input port 3.

Next, the operation shown in FIG. 1 will be explained. The data before correction
It is supplied from the CPU to output port 2 via CPU bus line 1. The uncorrected data received by the output port 2 is corrected by the error correction circuit 4, resulting in corrected data 6, which is supplied to the input port 3 and delivered to the CPU via the CPU bus line 1. .

At the same time, the error correction circuit 4 generates an error status signal 7 and sends it to the CPU bus line 1 via the input port 3 to indicate whether the syndrome register has become "0" after error correction of one packet. I'll put it on. If the syndrome register is "0", it means that there was no error in the data before correction, or that the data was corrected correctly even if there was an error in the data before correction.The CPU detects the error status signal. , it is possible to know whether the corrected data is correct or not.

However, the above-mentioned conventional technology has the following drawbacks.

In Figure 1, the transmission and reception of signals between the CPU and the error correction circuit via the CPU bus is, for example, 8 bits = 1.
Assuming that correction is performed in byte units, it takes 34 bytes to supply 1 packet = 272 bits of uncorrected data from the CPU to the error correction decoding circuit, and 1 packet of data corrected by the error correction circuit 4. It takes a similar amount of time to supply the data from the error correction decoding circuit to the CPU.

Furthermore, in Japanese teletext broadcasting, it is possible to transmit up to 12 packets in one vertical period, and if you try to process all of them, one vertical period =
The data transfer time between the CPU and the error correction decoding circuit during 16.67 ms is 34 byte times x 2 x 12 = 816 byte times. These transfers are performed by the CPU's write and read instructions, and since the CPU cannot perform any other processing during this transfer time, it cannot decode and display the codes necessary for receiving and displaying teletext. This will interfere with processing such as format generation. Especially the error correction circuit 4
Since the error correction operation in is performed asynchronously with the CPU operation, the CPU constantly detects whether or not error correction for one packet has been completed, and as soon as the error correction is completed, the CPU Because the CPU has to shift to reading data, other CPU processing is interrupted frequently and intermittently.

As explained above, the conventional technology shown in Figure 1 places a heavy burden on the CPU and requires much of the processing time, making it virtually impossible to perform all the processing necessary for receiving and displaying teletext. It had the disadvantage of getting used to it.

Secondly, in the error correction decoding circuit shown in FIG. 1, it is only possible to know whether or not the correction was made correctly after the correction, but it is not possible to know how many bits have been corrected. In order to convert the received code data into a digital code, it is necessary to determine whether the signal value at each point in time is "1" or "0", and the threshold voltage for determination must be selected correctly. Otherwise, you will not be able to obtain the correct digital code. In order to determine the threshold voltage correctly, it is necessary to know the degree of error at a certain threshold voltage and to feed back this information.

Thirdly, Japanese Patent Application No. 58-54002 discloses an invention in which correction is repeated by changing the decision threshold of the majority decision circuit, but when the number of error bits is large, the decision threshold is changed. Even if you change it and make corrections repeatedly, it cannot be corrected, so it is a waste of time.

Furthermore, if the number of error bits is large, each time the correction operation is repeated, the error may be incorrectly corrected, resulting in an increase in errors. In such a case, the display will have more errors than when the code is decoded and displayed using data before correction.

(Object of the Invention) An object of the present invention is to provide a correction number counter that counts the number of corrected bits, and to terminate the correction operation when the count result exceeds a predetermined value, in order to solve the problems of the prior art described above. The object of the present invention is to shorten the correction time and add error information such as the number of corrections to the corrected data to make it easier to discriminate the received signal.

(Embodiment) In FIG. 2 which shows a circuit diagram of the first embodiment of the present invention, 10 is a data bus of a CPU (not shown), and 11 is an address bus of the CPU.
The data bus 10 of the CPU is the data bus control circuit 1
The second input/output terminal of the data bus control circuit is connected to the local data bus 13. The address bus 11 of the CPU is connected to a first input terminal of an address switching circuit 14, and an automatic address signal 16 is supplied from an address generation circuit 15 to a second input terminal of the address switching circuit 14. The address switching circuit 14 uses the bus control signal 18 supplied from the timing control circuit 17 to select either the CPU address signal applied to the first input terminal or the automatic address signal 16 applied to the second input terminal. A memory address signal is supplied to the address input terminal of the buffer memory 19.

The local data bus 13 is also connected to a data input/output terminal of the buffer memory 19 and a data input/output terminal of the data transfer circuit 20, so that the CPU, buffer memory, and data transfer circuit exchange data with each other. be able to.

The data transfer circuit 20 receives serial reception data 2, which is packet reception data received and extracted by a character code broadcast reception unit (not shown).
1. Due to the framing signal of character code broadcasting,
A framing detection signal 22 indicating that frame synchronization has been achieved, and a synchronization clock 23 synchronized by the clock run-in of character code broadcasting are supplied.

The data register 24 is a register for storing and shifting 272-bit packet reception data or 190 bits of information bits out of the 272-bit packet reception data.
Uncorrected data 25 parallel-to-serial converted by 0
is received and shifted. The syndrome register 26 is similar to that disclosed in FIG. 10 of Japanese Patent Application No. 58-6579, and has an 82-bit feedback loop via a modulo-2 adder 27. 28 is a load gate circuit, which receives the load gate signal 2 supplied from the timing control circuit 17.
9 controls whether or not the uncorrected data 25 is supplied to the syndrome register 26 via the adder 27.

30 is a syndrome register signal, 31 is a majority circuit, 32 is a threshold signal, 33 is a threshold generation circuit, 34 is a threshold clock for updating the threshold, 35 is a syndrome register 26
and a loading clock signal for loading data into the data register 24; 36 a correction clock signal; 37 a clear signal for clearing the syndrome register 26; The collect gate signal 3 determines whether or not to supply the adder 41 as
a collect gate circuit for control by 9;
42 is corrected data, 43 is a clock signal for performing serial-parallel/parallel-serial conversion, 44 is a write pulse signal for writing received data into the buffer memory, and 45 is a write pulse for writing into the buffer memory. It's a signal. Further, 46 is a vertical blanking signal or a signal similar to the vertical blanking signal, 47 is a horizontal synchronization signal or a horizontal blanking signal, and 48 is a status signal for indicating the operating state.

Reference numeral 49 is a register that is set when the syndrome register becomes "0", and its output signal, an error status signal 50, is supplied to the data transfer circuit 20. Further, 51 is a correction number counter for counting the number of times a bit error is corrected, and it sends out a correction number signal 52 to the data transfer circuit 20, and also sends out a correction number signal 52 to the data transfer circuit 20, as well as a correction overload signal indicating that the number of corrections exceeds a predetermined value. The signal 53 is sent to the timing control circuit 17 and the data transfer circuit 20.
send to

54 and 55 are address update signals, and 56 is an address update signal.
This is the CPU data request signal.

Next, the operation shown in FIG. 2 will be explained.

The operating modes in Figure 2 can be roughly divided into serial-to-parallel conversion of serially received data and writing to the buffer memory, reading uncorrected data from the buffer memory and loading it to the data register and syndrome register, and circulating the data register and syndrome register. It consists of four operating modes: , correcting errors by repeating cycling while changing the majority decision threshold, and writing corrected data to buffer memory. Also,
As a fifth operation mode, the CPU reads the corrected data stored in the buffer memory.

FIG. 3 is for explaining the first operation mode, and shows the timing of packet reception data of character code broadcasting. In FIG. 3, 70 is a horizontal synchronization signal, 71 is a color burst, 72 is a 16-bit clock line in for clock synchronization,
Reference numeral 73 indicates a framing signal for frame synchronization, and 74 indicates 272 data bits, which form the serial reception data 21.

The data transfer circuit 20 receives a framing signal 73
By receiving a framing detection signal 22 indicating that frame synchronization has been achieved, the start time of serial reception data can be known. Also, since the synchronous clock 23 synchronized by the clock line in 72 is received, the serial reception data 21 is sequentially fetched and serial-to-parallel converted by the synchronous clock during the 272 data bit time. . If the capacity of the local data bus 13 is 8 bits, then every 8 bits of serial received data is sent to the local data bus. If the starting address of the area for storing uncorrected data regarding a packet in the buffer memory is address α, the data transfer circuit 20 will give the address update signal 55 to the address generation circuit 15 every time 8-bit data is sent. , the automatic address signal advances sequentially as α+1, α+2, α+3, . . . . Furthermore, each time these 8-bit data are sent out, a write pulse signal 44 is supplied to the buffer memory as a write pulse signal 45 via the timing control circuit 17.

In the first operating mode, the data bus control circuit 12 operates to separate 10 and 13, so that the data bus of the CPU can be used for other purposes, while the address switching circuit 14 operates to separate the two input signals. It operates to select the automatic address signal 16 supplied from the address generation circuit 15 and transmit it to the address input terminal of the buffer memory 19.

In this way, serial reception data 21 of 1 packet=272 bits is serial-parallel converted and sequentially written into buffer memory 19 starting from address α. FIG. 4 shows an operational flow for storing one packet of received data in the buffer memory 19. 8 bits =
Assuming that each byte is processed and written, the addresses that are repeatedly stored are from address α to α+33, 272÷8=34 times for one packet.

In Japanese character code broadcasting, up to 12 packets of data can be sent during one vertical blanking time, as shown in Figure 5. Fifth
In the figure, 80 is a vertical synchronization signal, 81 is a vertical blanking signal, and 82 is a signal generated from the vertical blanking signal 81. This is a signal extracted from only the latter half 12H of the vertical blanking time 21H. be. In Japanese character code broadcasting, signal 82 is “L”
It is possible to send data during the second half of the vertical blanking time, ie, the latter 12H of the vertical blanking time. Signal 46 in FIG. 2 is, for example, signal 82.
The address generation circuit 15 counts the horizontal synchronizing signal 47 while the signal 82, that is, 46 is "L", and provides a partial signal of the automatic address signal. For this reason, 1
When data transfer for a packet is completed, the address is switched to the address where the data of the next packet should be stored. Similarly, the operation flow shown in FIG. 5 is repeated 12 times, and 12 packets of uncorrected data are stored in the buffer memory 19. FIG. 6 shows an example of the correspondence between a packet number and a buffer memory address storing uncorrected data of that packet number. Although 34 addresses are sufficient as the data area for one packet, 64 addresses are reserved in FIG. 6 in order to simplify the configuration of the address generation circuit. Therefore, the second half of the 6th data area of 1 packet
Block 30 is unused. When writing of 12 packets of uncorrected data to the buffer memory is completed, the signals 81 and 82, ie, 46 in FIG. 5 change from "L" to "H", and the first operation mode ends.

In FIG. 5, when the vertical blanking signal 81 or signal 82 or 46 is inverted from "L" to "H", the second operating mode is entered. Also in the second operation mode, the data bus control circuit 12 in FIG. 2 operates to separate 10 and 13,
The address switching circuit 14 operates to select the automatic address signal given from the address generation circuit 15 and supply it to the address input terminal of the buffer memory 19. Further, the address generation circuit 15 updates the address based on an address update signal from the timing control circuit 17.

In the second operation mode, data is sequentially read out 8 bits at a time from address 0 of the buffer memory 19, parallel-to-serial conversion is performed in the data transfer circuit 20, and the uncorrected data 25 is transferred to the data register 24.
is supplied to the first input terminal of the adder 27 via the data input terminal of the adder 27 and the load gate circuit 28 . 8 bits are read out once from the buffer memory, and 1 packet = 272 bits is converted from parallel to serial in 34 times, and loaded into the data register 24 and the syndrome register 26. Error detection can be performed using the syndrome thus formed. That is, if all the syndrome register signals 30 are "0", there is no error in the data, and if any bit is "1", there is an error in the data. If there is no error, the third operation mode, that is, the correction operation may not be performed, but in this embodiment, the third operation mode is entered even in this case.

The error correction method of this embodiment is basically
58-6579, and
The point of performing correction by lowering the threshold value in sequence is as explained in Japanese Patent Application No. 58-54002. Some of the features of this embodiment are that a correction number counter is provided to count the number of error corrections, that a correction number signal and an error status signal indicating the number of corrections are sent out, and that when the number of corrections exceeds a predetermined value, The corrective action is to be stopped.

The second operating mode and the third operating mode are paired, and the end of the second operating mode, i.e.
When the data loading to the data register 24 and syndrome register 26 is completed, the third
enters operating mode. In the third operating mode, timing control circuit 17 generates a correction clock signal 36 to shift data register 24 and syndrome register 26. Also, the load gate circuit 28 is turned off, while the collect gate circuit 38 is turned on. Error correction is performed by an exclusive OR circuit (adder modulo 2) 41. Error correction signal 40 is a syndrome register
The 82 states are made into 17 linear combinations, and the majority circuit 31 among the 17 states is output by comparing it with a threshold value (the initial threshold value is 17).

However, this error correction signal 40 is configured to pass only during an error correction operation in response to the collect gate signal 39. Additionally, error correction signal 40 modifies syndrome register 26 to remove the effect of that bit when that bit is in error. The corrected data 42 is fed back to the data input terminal of the data register 24 again.

In addition, before correction, syndrome register 2
6 by 1 bit. This is because the majority code (273, 191) was chosen as the error correction code and one bit was reduced to make it the (272, 190) code. Thus a 272-bit shift (273-bit shift in the syndrome register)
When this is performed, one packet of 272 bits worth of signals is restored. At this time, by checking the error status signal 50, it can be determined whether or not error correction has been performed correctly. If all the bits in the syndrome register 26 are not "0", this means that an error still exists in one of the bit positions, so the error correction operation is performed again.
However, at this time, the threshold clock is given from the timing control circuit 17, and the threshold generation circuit 33 subtracts and counts this, so the threshold 1
will be reduced by That is, the threshold value is set to 16, and data after error correction is performed using the previous threshold value of 17 is used.

The above operations are carried out until the threshold value 9 is completed. However, when all the bits of the syndrome register 26 become "0" during the process, it means that the error correction operation has been completed. That is, since the data at that point is a correct value, there is no need to pass it through the error correction circuit thereafter.

Conversely, if the number of bits to be corrected is abnormally large, it means that there were an abnormally large number of errors in the original data, and correction is impossible, so corrections should be made before threshold 9 ends. It is better to cancel it. For this purpose, the correction number counter 51 counts the number of corrections, and when the number exceeds a predetermined value, it issues a correction over signal 53 and supplies it to the timing control circuit 17.

A flowchart of the operation in the third operation mode is shown in FIG.

As explained above, when the third operation mode ends, the corrected data is transferred to the data register 24.
is secured. When the third operating mode ends, the fourth operating mode is automatically entered. In the fourth operation mode, the corrected data is subjected to value-parallel conversion and stored in the buffer memory. Prior to sending the corrected data, first, the error status signal 50, correction over signal 53, and correction number signal 52 are sent to the local data bus 13, and the buffer memory 1
9 is stored at the first address of the area where the corrected data is to be stored. Afterwards, 272-bit corrected data will be sent, but the corrected data will be 82 bits.
Since the parity bits are not necessary, only 190 information bits are written to the buffer memory.
In the fourth operation mode, since the error correction signal is prohibited by the collect gate signal 39, the corrected data that has already been corrected and secured in the data register 24 is replaced by the corrected data 4.
2 and sent to the data transfer circuit, subjected to serial-to-parallel conversion, and stored in the buffer memory via the local data bus 13.

As shown in Japanese Patent Application No. 58-90017, the beginning of the 272-bit packet data is an 8-bit SI/IN indicating the service identification and interrupt priority order using the (8, 4) extended Hamming code, and then There are 6 bits of packet control (PC) for packet content identification, followed by 22 bytes of pure information bits. Therefore, if the corrected data is packed 8 bits at a time, the first 2 bits of each byte will be mixed into the data section of the previous byte. In order to avoid this problem, in this embodiment, 2 additional bits are added to the second byte of data to make it 8 bits, similar to Japanese Patent Application No. 58-90017. Thus, as corrected data, 24 bytes of data part and 1 byte of error information added to the first address are written per packet, making 25 bytes. This operational flow is shown in FIG. During the fourth operation mode described above, a write pulse 45 is applied from the timing control circuit 17 to the buffer memory every time one byte of data is sent from the data transfer circuit, and an address update pulse 54 is used to update the automatic address. Signal 16 is updated. Also in the fourth operation mode, the switching circuit 14 selects the automatic address signal 16 and supplies it to the address input terminal of the buffer memory 19. Furthermore, in the fourth operation mode, the data bus control circuit 12 operates to separate the signals 10 and 13, so the CPU may perform other operations.

The second operation mode, third operation mode, and fourth operation mode described above are a series of operations. That is, one packet of uncorrected data is read from the buffer memory 19, loaded into the syndrome register 26 and data register 24 (second operation mode), error correction is performed (third operation mode), and the corrected data is loaded. Error information is added and written to the buffer memory 19 (fourth operation mode). When these series of operations are completed, 2
The operation for the packet is started, and the second operation mode, third operation mode, and fourth operation mode are executed in the same manner. Hereafter, the same operation is performed up to 12 packets. Thus, the corrected data is stored in the corrected data area of the buffer memory 19 as shown in FIG. In FIG. 9, 64 addresses are reserved as an area for one packet, but in reality only 25 bytes are used.

As shown in FIG. 9, when the corrected data of all packets are stored, the timing control circuit 17 issues a status signal 48 to indicate to the CPU that the buffer memory 19 may be read by the CPU.

In the fifth operating mode, the CPU sends the status signal 4
8 is detected and the CPU reads the contents of the buffer memory. In this mode
The CPU provides a data request signal 56 to the timing control circuit 17. This causes the timing control circuit 17 to connect the CPU data bus 10 and the local data bus 13, and also disables the automatic address signal 16 to connect the CPU data bus 10 to the local data bus 13.
The signal of the address bus 11 is transferred to the buffer memory 19.
A bus control signal 18 is provided so as to be supplied to the bus.
In this way, the output data of the buffer memory is available to the data bus of the CPU via the local data bus 13, so that the data in the area of the buffer memory addressed by the CPU can be read.

In the above explanation, 8 bits is used as the bit capacity of the local data bus 13, and the buffer memory 1
Although an example has been shown in which data is exchanged between the data transfer circuit 20 and the data transfer circuit 20 in units of 8 bits, other numbers of bits, such as 16 bits or 4 bits, are also possible. However, in the case of 16 bits, SI/IN
It is necessary to treat both data and packet control as 14 bits, and to shift the 14 bits by 2 bits.

Furthermore, the data register 24 does not necessarily have to be 272 bits, but corresponds to information bits.
Just 190 bits is fine. However, in this case 82
It is necessary to inhibit the loading clock signal and the correction clock signal for the data register during the time corresponding to the bit.

In addition, the error information includes the error status signal, correction over signal, and correction number signal.
Although an example has been described in which the error information is within a byte, the number of bits of the correction number signal may be increased so that the error information becomes a plurality of bytes.

Further, in this embodiment, 17 to 9 are used as thresholds for majority decision, but the gist of the present invention is not limited to specific values such as 17 and 9.

In the first embodiment shown above, the corrected data is the output signal of the adder 41, which is given as serial data 42, and is serial-to-parallel converted by the data transfer circuit 20. However, as a second embodiment, the corrected data can be extracted in 8-bit parallel as shown in FIG. In FIG. 10, 24, 25, 40,
and 41 are the same as in FIG.
However, here, 41 is not the final corrected data, but the data register is used in the process of sequentially correcting errors by changing the threshold, in preparation for error correction at the next threshold. Used only for updating. In FIG. 10, 90 is a register of 8 bits on the output top side of the data register 24, and 91 is an output signal of the register 90, which is connected to the data transfer circuit 20 as final corrected data. If the data is output in 8-bit parallel in this manner, the data transfer circuit 20 simply latches it at a predetermined timing and sends it to the local data bus 13.

Next, in the first embodiment, even if correct correction cannot be made even if the threshold value is lowered to 9, or even if the number of error corrections exceeds a predetermined value, the corrected data is stored in the buffer memory. was stored in the corrected data area. However, in such a case where correction is impossible, there are many errors in the original received data, and if error correction is performed on such received data, the error will be incorrectly corrected and the errors will increase. There is a possibility that it will be stored away.

Therefore, in the third embodiment, in such a case where correction is impossible, the information data portion of the uncorrected data of the packet already stored in the buffer memory 19 is stored in the corrected data area of the packet in the buffer memory 19. We propose adding error information to 24 bytes and writing the packet control section with a 2-bit shift. In this way, the CPU can read the data before the error increases, and since the data is shifted by 2 bits, it is easier for the CPU to process it, and it can also know the error information. .

(Effects of the Invention) As described above, the present invention includes a buffer memory for storing uncorrected data and post-corrected data, and performs operations such as writing received data to the buffer memory, reading uncorrected data from the buffer memory, Furthermore, by having a data transfer circuit for automatically writing the corrected data into the buffer memory, the operational burden on the CPU can be reduced.

Furthermore, since the number of corrected bits is counted and the correction operation is terminated when the number of corrections exceeds a predetermined value, the correction time can be shortened.

Therefore, the present invention can be applied not only to teletext receivers based on the code system, but also to a wide variety of digital devices that use majority error correction using difference set cyclic codes.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of the prior art, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIGS. 3 and 5 are timing diagrams for explaining the embodiment, and FIGS. FIG. 8 is a flowchart for explaining the embodiment, FIGS. 6 and 9 are mapping diagrams of data stored in the buffer memory, and FIG. 10 is a circuit diagram showing a second embodiment of the present invention. 1...CPU bus line, 2...Output port,
3...Input port, 4...Error correction circuit, 5...
Data before correction, 6...Data after correction, 7...Error status signal, 10...CPU data bus,
11...CPU address bus, 12...Data bus control circuit, 13...Local data bus, 1
4... Address switching circuit, 15... Address generation circuit, 16... Automatic address signal, 17... Timing control circuit, 18... Bus control signal, 19...
...Buffer memory, 20...Data transfer circuit, 2
1...Serial reception data, 22...Framing detection signal, 23...Synchronization clock, 24...Data register, 25...Data before correction, 26...
Syndrome register, 27...Adder, 28...
...Load gate circuit, 29...Load gate signal, 30...Syndrome register signal, 31...
...Majority circuit, 32...Threshold signal, 33...
Threshold generation circuit, 34...Threshold clock,
35...Load clock signal, 36...Correction clock signal, 37...Clear signal, 38...Collect gate circuit, 39...Collect gate signal, 40...Error correction signal, 41...Adder, 4
2...Data after correction, 43...Clock signal, 4
4...Write pulse signal, 45...Write pulse signal, 46...Vertical blanking signal or signal similar to the vertical blanking signal, 47...Horizontal synchronization signal or horizontal blanking signal, 48... ...Status signal, 49...Register, 50...Error status signal, 51...Correction number counter, 52
... Correction number signal, 53 ... Correction over signal, 5
4, 55...Address update signal, 56...CPU
data request signal, 70...Horizontal synchronization signal, 71...Color burst, 72...Clock run in, 73...Framing signal, 74...
Data bit, 80... Vertical synchronization signal, 81...
Vertical blanking signal, 82... Vertical blanking signal 8
Signal generated from 1, 90...Register of the first 8 bits output from the data register 24, 91...
...Output signal of register 90.

Claims (1)

[Scope of Claims] 1. A local data bus; A buffer memory coupled to the local data bus and storing uncorrected and corrected data; An address signal output from a CPU (central processing unit) is selectively transferred to the buffer memory; an address switching circuit that transfers data to and specifies an address of the buffer memory; an address switching circuit that is coupled between a data bus of the CPU and the local data bus, and that separates the data bus and the local data bus in response to a control signal; a bus control circuit; a majority circuit that generates an error correction signal; and a majority circuit that receives the error correction signal and outputs a correction number over signal that indicates that the number of corrections exceeds a predetermined value and a correction number signal that indicates the number of corrections. an error correction circuit that includes a correction number counter and receives uncorrected data and outputs corrected data; and an error correction circuit that is coupled to the local data bus and the error correction circuit and that receives character code data in a first operation mode. After converting into the uncorrected data, the uncorrected data is transferred to the buffer memory via the local data bus, and in the second operation mode, the correction number over signal and the correction number signal output from the correction number counter, and the a data transfer circuit that sequentially transfers the corrected data output from the error correction circuit to the buffer memory via the local data bus; and outputs a control signal to the data bus, the data transfer circuit, and the error correction circuit. 1. A code error correction decoding circuit comprising: a timing control circuit; and a code error correction decoding circuit.