JP3530548B2 - Image decoding apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a variable length coded image.
The present invention relates to an image decoding apparatus and method for decoding image data .

[0002]

2. Description of the Related Art Image information compression methods include a fixed length coding method (for example, DPCM method) and a variable length coding method. The fixed-length coding method has a feature that image data and transmission data have a one-to-one correspondence, so that even if a transmission error occurs, the effect can be suppressed within a coding unit (line or block). . On the other hand, the variable-length coding method can realize a high compression rate, but since the image data and the transmission data do not have a one-to-one correspondence, there is a drawback that if a transmission error occurs, its influence will be widespread.

Conventionally, the variable length coding method is used in a transmission medium having a low occurrence rate of transmission errors (for example, a data transmission path between inside and outside a computer system or a disk medium), and the fixed length coding method is used in the transmission. Transmission medium with high error,
For example, it was used in satellite communication lines.

[0004]

In recent years, there is an increasing demand for transmitting image information through a transmission medium having a high transmission error rate such as a satellite communication line, and image transmission at a high compression rate is desired.

Therefore, the present invention is directed to an image decoding apparatus capable of recovering from a transmission error at an early stage even with a variable length coding system, and a method therefor.
The purpose is to present the method .

[0006]

SUMMARY OF THE INVENTION An image decoding apparatus according to the present invention divides image data into a plurality of blocks and performs a variable length coding on the block-by-block basis. Input means for inputting transmission data generated by adding data, detection means for detecting the sync data from the transmission data, first memory for sequentially storing the transmission data, and output of the detection means. Accordingly, the second memory for acquiring the address information indicating the position where the head data of the block is stored on the first memory, and storing the acquired address information, and the second memory Reading means for sequentially reading the variable-length encoded image data from the first memory based on address information stored in the memory; And having a decoding means for decoding the variable length encoded image data is issued.

Further, in the image decoding method according to the present invention, the image data is divided into a plurality of blocks, and the sync data indicating the beginning of the block is added to the image data which is variable length coded in block units. The transmission data generated by the above is input, the sync data is detected from the transmission data, the transmission data is sequentially stored in the first memory, and the transmission data is sequentially stored in the first memory, and the transmission data is stored in the first memory according to the detection result. Address information indicating the position where the data at the head of the block is stored is acquired, the acquired address information is stored in a second memory, and the first address is stored based on the address information stored in the second memory. It is characterized in that the variable-length coded image data is sequentially read from one memory, and the read variable-length coded image data is decoded.

[0008]

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic block diagram of an embodiment of the present invention. 10 is a transmitter, 12 is a transmission line, and 14 is a receiver.

The transmitter 10 will be described. The image signal to be transmitted is input to the input terminal 20, and the blocking circuit 2
2 divides the image signal from the input terminal 20 into a plurality of blocks within the screen, and outputs the blocks to the variable length coding circuit 24 in block units. The variable-length coding circuit 24 performs variable-length coding on the image signal in block units, and the sync addition circuit 26, as shown in FIG. 2, adds a block identifier to the beginning of the block-unit code output from the variable-length coding circuit 24. Is added as a sync signal. The sync signal includes block number information. The modulation circuit 28 modulates the output of the sync addition circuit 26 by a predetermined method and outputs it from the output terminal 30 to the transmission line 12.

The receiver 14 will be described. The modulated signal from the transmission line 12 is applied to the demodulation circuit 34 via the input terminal 32 and demodulated. The demodulation circuit 34 outputs the received code data to the memory 36 and the sync detection circuit 40. The write address generation circuit 38 generates an address that is sequentially incremented at a rate corresponding to the transmission rate, and the address is applied to the memory 36 as a write address. The write address generation circuit 38 may generate the write address of the memory 36 according to the timing signal from the demodulation circuit 34. This allows the memory 3
6 sequentially stores the received code data output from the demodulation circuit 34.

The sync detection circuit 40 detects the output of the received code data of the demodulation circuit 34 and outputs the sync addition circuit 2 of the transmitter 10.
The sync signal added in 6 is detected, and the block number value included in the sync signal is output. Pointer memory 42
Stores the write address generated by the write address generation circuit 38 according to the output of the sync detection circuit 40. That is, the pointer memory 42 stores the block start address of the data stored in the memory 36. Pointer
The storage address in the memory 42 corresponds to the block number included in the sync signal. The pointer memory 42 is, for example, a dual port memory with SRAM elements.

The block number generation circuit 46 sequentially generates block numbers in synchronization with the blocks of the received image,
It is applied to the pointer memory 42 as a read address. The pointer memory 42 uses the block number generation circuit 4
The value stored in the address corresponding to the block number 6 generated (that is, the address indicating the head data storage position of the block of that block number in the memory 36) is read and applied to the read address generation circuit 44. The read address generation circuit 44 loads the address from the pointer memory 42 and then sequentially increments the address. The data stored in the memory 36 is read from the read address generated by the read address generating circuit 44 and applied to the variable length decoding circuit 48.

In this way, the variable length decoding circuit 48 is always supplied from the beginning data of each block, so that the influence of the transmission error does not spread to the next block.

In the above embodiment, the reading from the memory 36 is restricted to the head data of each block regardless of the presence or absence of the transmission error. However, only when the undecodable transmission error appears, the next data from the memory 36 is read. It goes without saying that the control may be performed so as to read the data after the head of the block.

[0017]

As can be easily understood from the above description, according to the present invention, the address information at the head of a block is
Address stored in another memory and stored in said memory
Reads variable length coded image data based on information
The memory where the beginning of the block is stored
Since the upper position can be instantly grasped and the data can be easily read from the beginning of the block, the error propagation can be limited to a specific block unit at the time of a transmission error, and the image can be instantly restored . Therefore, even with data transmitted through a transmission line having a high transmission error rate, image deterioration due to a transmission error can be prevented more than ever before.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an embodiment of the present invention.

FIG. 2 is a data transmission configuration diagram of the present embodiment.

[Explanation of symbols]

10: transmitter 12: transmission line 14: receiver 2
0: Input terminal 22: Blocking circuit 24: Variable length coding circuit 26: Sync addition circuit 28: Modulation circuit 30: Output terminal 32: Input terminal 34: Demodulation circuit 3
6: Memory 38: Write address generation circuit 40: Sync detection circuit 42: Pointer memory 44: Read address generation circuit 46: Block number generation circuit 4
8: Variable length decoding circuit

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References Japanese Patent Laid-Open No. 2-162981 (JP, A)                 Japanese Patent Laid-Open No. 4-220889 (JP, A)                 JP-A-4-245881 (JP, A)                 JP-A-5-115007 (JP, A)                 JP-A-5-130583 (JP, A)

Claims (2)

(57) [Claims] 1. Image data divided into a plurality of blocks and variable length coded image data in units of the blocks,
Input means for inputting transmission data generated by adding sync data indicating the beginning of the block, detection means for detecting the sync data from the transmission data, and a first memory for sequentially storing the transmission data. A second address for acquiring address information indicating a position where the head data of the block on the first memory is stored in accordance with an output of the detection means, and storing the acquired address information; A memory; a reading unit that sequentially reads the variable-length coded image data from the first memory based on address information stored in the second memory; and the variable-length read by the reading unit An image decoding apparatus comprising: a decoding unit that decodes encoded image data. 2. Image data divided into a plurality of blocks and variable length coded image data in block units,
The transmission data generated by adding the sync data indicating the beginning of the block is input, the sync data is detected from the transmission data, the transmission data is sequentially stored in the first memory, and the transmission data is stored according to the detection result. And acquiring address information indicating a position where the head data of the block is stored on the first memory, storing the acquired address information in a second memory, and the second memory Characterized in that the variable-length coded image data is sequentially read from the first memory based on the address information stored in the memory, and the read variable-length coded image data is decoded. Image decoding method.