JPS60227463A - Manufacture of semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase memory capacitance while preventing punch-through phenomenon appearing between each of grooves to serve as memory capacitance sections also to fine memory cells by surrounding the inner walls of the grooves by impurity layers having the same conduction type as a substrate. CONSTITUTION:An isolation region 22 is formed on a P type Si single crystal substrate 21, and an SiO2 film 23, an Si3N4 film 24 and an SiO2 film 25 are shaped on the whole surface in succession. The film 25, the film 24 and the film 23 are removed while using a resist 26 as a mask, and grooves A, A' are formed to the substrate 21. The film 25, the film 24 and the film 23 are removed, and an epitaxial layer 27 containing a P type impurity is shaped on the surface from which the substrate 21 is exposed. The P type impurity included in the layer 27 is pushed into the substrate 21 through heat treatment to form impurity diffusion layers 28, and an epitaxial layer 29 containing an N type impurity is grown on the surface from which the substrate 21 is exposed. The film 23 is removed, a thin SiO2 film 30 is shaped on the whole surface, and an electrode 31 is formed so as to contain a capacitance forming region.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor memory getIk, and more particularly to a method of manufacturing a semiconductor memory device that achieves a much larger storage capacity.

(Prior art and its problems) Semiconductor memory cells that store binary information in the form of charges have a small cell area, so they are excellent as cylindrical integrated memory cells. For example, in an explanatory article published in the July 18, 1983 issue of Nikkei Electronics, pages 169 to 194, entitled ``Design of memory cells as the basis for realizing highly integrated dynamic RAM'', as shown in Figure 1. A memory cell (hereinafter referred to as IT) consisting of one transistor and one capacitor
(abbreviated as IC cell) is shown. This ITIC cell has few components and has a small cell area, so it is currently widely used as a memory cell for highly integrated memories.

In FIG. 1, reference numeral 3 denotes a capacitor/4' capacitor electrode which forms a storage capacitor between it and the inversion layer 6. Reference numeral 2 denotes the f-) electrode of the switching transistor, which controls the movement of charges between the diffusion layer 4 and the inversion layer 6, which are connected to the word and bit holes. Further, 7 is an isolation region from an adjacent memory cell. In this conventional example, the storage capacity is determined by the area of the canopy pole 3, the dielectric constant of the insulating film 5, and its film thickness.

In other words, the following three methods can be used to secure large storage capacity.
There are two ways.

(1) Increase the area of the capacitor electrode.

(2) Reduce the thickness of the insulating film.

(3) Use an insulating film with high -' electrical conductivity.

Incidentally, high integration of memories is generally achieved by reducing the memory cell size as microfabrication technology advances, and in the ITIC cell structure shown in the conventional example, the area of the capacitor electrode is reduced. Therefore, in conventional ITIC cells, a significant decrease in storage capacity has been prevented by reducing the thickness of the insulating film. However, the thickness of the insulating film is approaching its limit. On the other hand, as the miniaturization of cells continues to progress, the storage capacity of conventional ITIC-15 cells will continue to decrease unless an insulating film with a high dielectric constant is used. Insulating films with a cylindrical dielectric constant are at the exploratory stage and there is no prospect that they will be put to practical use in the near future.

In this current situation, an analogy can be drawn from the 1982 Fall 4
In a lecture titled "Application of deep trenches to capacitor formation" at the 3rd Annual Conference of the Japan Society of Applied Physics (Presentation Proceedings, page 434), the surface area of the capacitor electrode region was oscillated as shown in Figure 2. Means are shown for increasing the area of the capacitor electrode without increasing the area of the capacitor electrode. This is the second
As can be seen from the figure, by providing a groove in the capacitor electrode area, the area of the capacitor electrode area is increased. In addition, in FIG. 2, 11 is a silicon substrate, 12, 1
2' is the dirt electrode of the switching transistor connected to the word line, 13 is the capacitor electrode, 1.4.14
' is an N-type diffusion layer connected to the bit line, 15, 15
' is an insulating film forming a capacitor, 16 is a depletion layer, 17
is in a separate area. Since the operating principle is the same as that in FIG. 1, its explanation will be omitted here. This method of increasing the capacitor electrode area by forming grooves makes it possible to ensure sufficient storage capacity by increasing the depth of the grooves even as memory cells become smaller. However, in conventional structures like this, when the distance between the groove that forms the storage capacitor and the groove becomes narrower as memory cells become smaller, a punch-through phenomenon occurs between the two grooves that form the capacitor. The drawback was that stored information was destroyed.

(Object of the Invention) An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor memory device that eliminates such conventional drawbacks and can handle a larger storage capacity with better controllability than the conventional type. It's about doing.

(Structure of the Invention) The non-invention includes a step of forming a groove on a first conductivity type semiconductor substrate, and selectively forming a first conductivity type semiconductor layer only on a portion of the inner wall of the groove where the semiconductor substrate is exposed. a step of forming a second conductivity type semiconductor layer selectively only on the fourteenth conductivity type semiconductor layer; a step of forming a thin insulating film on the second conductivity type semiconductor layer; This method of manufacturing a semiconductor memory device is characterized by performing a step of forming a conductive electrode so as to cover at least the second conductive type semiconductor layer on the film, and a step of plating.

(Principle and operation of the invention) The present invention first forms a groove serving as a capacitor on a first conductivity type semiconductor substrate, and then selectively forms a first conductivity type semiconductor layer and a second conductivity type semiconductor layer only on the surface of the groove. A thin insulating film and a capacitor electrode material are sequentially formed on the surface of the groove, and first and second conductive type semiconductor layers are formed selectively and with good Ti controllability only on the surface of the groove that will become the capacitor. Therefore, according to the present invention, the capacitance between the second conductive type semiconductor layer and the first conductive type semiconductor substrate is increased with better controllability compared to the conventional type, and it also serves as a storage capacitor for fine memory cells. It is possible to effectively prevent the knocking phenomenon that occurs between the beak and the groove.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

[Example 1] Figures 3(a) to 3(1) are schematic cross-sectional views showing the manufacturing process along l- when the entire inner wall of the groove is used as a storage capacitor portion in the present invention. .

FIG. 3(a) shows that after an isolation region 22 is formed on a P-type silicon single crystal substrate 21 by a commonly used device isolation method, such as the LOCO8 method, a silicon dioxide film 23 and a silicon nitride film are formed on the entire surface of the wafer. A state in which a film 24 and a silicon dioxide film 25 are formed one after another, and areas other than the groove forming region are further covered with a resist 26 is shown.

In FIG. 3(b), the silicon dioxide film 25, the silicon nitride film 24, and the silicon dioxide film 23 are sequentially etched away using a reactive step etching technique using the resist 26 covered with an etching-resistant mask. After that, the silicon substrate 21 is etched again by reactive sputter etching technique using the renost 26 and the silicon dioxide film 25 as an etching-resistant mask to form a groove A of a desired depth.
, A' is formed, and then the silicon dioxide film 25 is etched away using an isotropic etching technique such as buffered hydrofluoric acid. When the silicon dioxide film 25 is removed using buffered phosphoric acid, the silicon dioxide film 23 is also etched at the same time and retreats from the opening ends of the trenches A and A'.

FIG. 3(c) shows that after the silicon nitride film 24' is removed by etching, a thin epitaxial layer 27 containing 2M impurities is formed only on the exposed surface of the silicon substrate 21 by a selective epitaxial layer growth technique. Shows the grown state. To selectively form an epitaxial layer, Int
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This can be easily achieved by using the technology published under the title AxlGrowth J.

FIG. 3(d) shows the epitaxial layer 2 formed by heat treatment.
The P-type impurity contained in step 7 is pushed into the silicon substrate 21 to form the impurity diffusion layer 28, and then selective epitaxial layer growth technique is used again to contain the N-type impurity only on the exposed surface of the silicon substrate 21. A state in which a thin epitaxial layer 29 has been grown is shown.

FIG. 3(6) shows that after the silicon dioxide film 23 is removed, a thin silicon dioxide film 30 is formed on the entire surface by a thermal oxidation method, and then a polycrystalline silicon film is formed so as to include the capacitance formation region. A state in which an electrode 31 is formed is shown. Here, in order to form a capacitance between the polycrystalline silicon 31 and the silicon substrate 21, only a thin silicon dioxide film "30" is formed by thermal oxidation, but in order to further increase the capacitance, a silicon dioxide film It may also have a two-layer structure of a silicon nitride film and a silicon nitride film.Also, polycrystalline silicon is used to form the electrode 3], and this polycrystalline silicon grows with sufficient rotation even in a narrow groove width. Therefore, the port is completely buried in polycrystalline silicon.

FIG. 3(f) shows the dirt oxide film 30 of the switching transistor and the dirt electrode 32 connected to the word line.
N-type diffusion wJ33 is formed and further connected to the bit line.
This shows a state in which a memory cell is formed by forming an N-type diffusion dove 34 connected to the epitaxial layer 29 containing the Nfi impurity. Embodiment 1 described above is an example in which the capacitive portion is formed on the entire inner wall of the groove, and Embodiment 2, which will be described next, is an example in which the capacitive portion is formed only in a part of the inner wall of the groove, and only on one side wall. It is.

(Example 2) FIGS. 4A to 4F are schematic sectional views sequentially showing the manufacturing process when only the side wall of the groove is used as the memory answer front part in the present invention.

FIG. 4(a) shows a state in which a silicon dioxide film 42, a silicon nitride film 43, and a silicon dioxide film 44 are sequentially formed on a P-type silicon single crystal substrate 41, and then the area other than the groove forming area is covered with a resist 45.

FIG. 4(b) shows that after the silicon dioxide film 44, silicon nitride film 43, and silicon dioxide film 42 are etched away using the resist 45 as an etching-resistant mask, the silicon dioxide film 44, the silicon nitride film 43, and the silicon dioxide film 42 are etched away using a reactive step etching technique or the like. The resist 45 and the silicon dioxide film 44 are used as etching masks, and the silicon substrate 41 is etched away again using a reactive etching technique or the like to form a groove Bi shadow of a desired depth, and the inner wall of the defect is heated. Silicon dioxide film 4 by oxidation method
Then, by ion implantation, an impurity of the same conductivity type as the substrate is added only to the bottom of groove B, for example. This shows the state in which Ron 47 is driven.

FIG. 4(c) shows the state in which the entire wafer is covered with photoresist 48.

FIG. 4(d) shows how the photoresist 48 is applied to the reactive film 4.
After etching away from the surface using vine etching technology or glazma etching technology, leaving only the area near the bottom of the groove B, the resist 48 remaining at the bottom of the groove is used as an etching mask to form a shape on the side wall of the groove. A state in which the silicon dioxide film 46 is removed by etching is shown.

FIG. 4(e) tl'i shows a state in which a thin epitaxial layer J-49 containing P-type impurities is grown only on the side wall of the groove B where the silicon substrate 41 is exposed using the selective epitaxial growth technique.

FIG. 4(f) shows that the P-type impurity contained in the epitaxial layer is forced into the silicon substrate by heat treatment to form a diffusion layer 49', and then the silicon substrate 41 is exposed again by selective epitaxial growth technique. #4B
A wide epitaxial layer 5 containing N-type impurities only on the sidewalls of
FIG. 4(g) shows a state in which 0 is grown. After a thin silicon dioxide film 51 is formed on the wall of the trench BIIIJ by thermal oxidation, a thick polycrystalline silicon 52 is formed on the entire surface of the wafer. This shows a state in which polycrystalline silicon 52 is removed only from the surface by etching, leaving polycrystalline silicon 52 only inside dB.

FIG. 4(h) shows the silicon dioxide film 4 remaining on the surface.
4 shows a state in which a thick silicon dioxide film 53 is formed by oxidizing the upper part of the polycrystalline silicon 52 buried in the groove using the etching mask 43 as an oxidation-resistant mask.

In FIG. 40), after removing the silicon nitride film 42', a dirt oxide film 54 of the switching transistor and a dirt electrode 55 connected to the word line are formed, and an N-type diffusion layer 56 connected to the bit line is formed. This shows a state in which a memory cell is formed by forming an N-type diffusion layer 57 connected to the epitaxial layer 1-50 containing the N-type impurity group.

As described above, when a capacitor is formed only on the groove side wall as shown in Example 2, two separated capacitor portions are formed in one groove. Therefore, by grounding the polycrystalline silicon buried in the trench and operating the memory cell, this trench can also be used as an isolation structure between elements.

(Effects of the Invention) As described above, according to the present invention, by surrounding the entire or part of the inner wall of the substrate with an impurity layer of the same conductivity type as the substrate, the conventional structure can be replaced with a groove in the forming part. In any case, it is possible to suppress the punch-through phenomenon that occurs between the groove capacitor parts, which becomes a problem when the storage capacity increases and the miniaturization progresses. Note that if only to prevent 79-inch through, it would be sufficient to increase the impurity concentration of the silicon substrate, but increasing the impurity concentration of the silicon substrate increases the stray capacitance of the other diffusion layers formed, causing damage to the memory itself. The disadvantage is that the response speed is reduced. For this reason, it is preferable to form an impurity layer of the same conductivity type as the substrate only around the groove. As a method for forming such an impurity layer, there is a method of diffusing the impurity or a method of diffusing the impurity throughout the silicon dioxide film. However, in either case, it is very difficult to form impurity JrIi of low quality in a well-controlled manner while taking into account its concentration and the depth of the diffusion layer. In the present invention, by using a selective epitaxial growth technique, it is possible to easily form a low-temperature impurity layer of the same conductivity type as the substrate only around the groove of the capacitance formation portion in a well-controlled manner.

As described in detail above, according to the present invention, a large memory capacity can be formed with good controllability even in a small memory cell area, so a memory cell suitable for high integration can be easily obtained. It is effective.

[Brief explanation of drawings]

Figure 1 is a schematic sectional view of a conventional ITIC memory cell, Figure 2 is a schematic cross-sectional view of a conventional ITIC memory cell.
The figure is a schematic cross-sectional view of an ITIC memory cell using a conventional trench, and FIGS. It is a sectional view. In the figure, 21.4 Toy silicon i&, 32.55... Dirt electrode of the switching transistor connected to the word line, 31.52... Capacitor electrode, 33°56...
・N-type diffusion layer connected to the bit line, 30°51...
- Insulating film forming a canopy, 22... Isolation region, 23.25.42.44.46.53... Silicon dioxide film, 24.43... Silicon nitride film, A, A'. B... Groove, 27, 49... Epitaxial layer containing P-type impurity, 28.49... P-type impurity diffusion layer, 2
9.50...Epitaxial layer containing N-type impurities,
34.57...N-type diffusion layer, 26.45.48...
Resist, 47...indicates a P-type diffusion layer, respectively. Figure 1 Figure 3 ((1) ' Figure 3 Figure 4 (b) Figure 4 (d) Figure 4 4/4e) Figure 4

Claims (1)

[Claims] (1) A step of forming a groove on a first conductivity type semiconductor substrate; a step of selectively forming a first conductivity type semiconductor layer only on a portion of the inner wall of the groove where the semiconductor substrate is exposed; 1st
a step of selectively forming a second conductive type semiconductor layer only on the conductive type semiconductor layer; a step of forming a thin insulating film on the second conductive type semiconductor layer; and a step of forming at least the second conductive type semiconductor layer on the insulating film. 1. A method for manufacturing a semiconductor memory device, comprising the steps of: forming a K 4 'It type electrode so as to cover the type semiconductor layer.