JPS6022595B2 - inverter circuit - Google Patents

inverter circuit

Info

Publication number
JPS6022595B2
JPS6022595B2 JP54163384A JP16338479A JPS6022595B2 JP S6022595 B2 JPS6022595 B2 JP S6022595B2 JP 54163384 A JP54163384 A JP 54163384A JP 16338479 A JP16338479 A JP 16338479A JP S6022595 B2 JPS6022595 B2 JP S6022595B2
Authority
JP
Japan
Prior art keywords
voltage
base
transistors
transistor
winding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54163384A
Other languages
Japanese (ja)
Other versions
JPS5686079A (en
Inventor
隆裕 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Life Solutions Ikeda Electric Co Ltd
Original Assignee
Ikeda Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ikeda Electric Co Ltd filed Critical Ikeda Electric Co Ltd
Priority to JP54163384A priority Critical patent/JPS6022595B2/en
Publication of JPS5686079A publication Critical patent/JPS5686079A/en
Publication of JPS6022595B2 publication Critical patent/JPS6022595B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5383Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a self-oscillating arrangement
    • H02M7/53832Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a self-oscillating arrangement in a push-pull arrangement
    • H02M7/53835Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a self-oscillating arrangement in a push-pull arrangement of the parallel type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

【発明の詳細な説明】 本発明は交互に導適する一対のトランジスタを備えたイ
ンバータ回路に関し、そのスイッチングロスを減少させ
て、ィンバータ回路の効率を高めるようにしたものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inverter circuit including a pair of transistors that are alternately conductive, and the efficiency of the inverter circuit is improved by reducing the switching loss.

例えば、従来から知られているプッシュプルィンバータ
回路として第1図に示すものがある。
For example, there is a conventionally known push-pull inverter circuit shown in FIG.

この構成を説明すると、1は直流電源で、その正極側は
電源スイッチ2、ィンダクタ3を直列に介して発振トラ
ンス4の1次巻線5,6のセンタータップに接続し、1
次巻線5,6の両端には一対のトランジスタ7,8をブ
ッシュプルに接続している。即ち、トランジスタ7,8
の各コレク夕を1次巻線5,6の両端に接続し、また両
ェミツタを直流電源1の負極側に接続し、さらに各ベー
スをそれぞれバイアス抵抗9,10を介して電源1の正
極側に接続するとともに発振トランス4のベース巻線1
1に接続している。12はコンデンサで、1次巻線5,
6の両端に接続し、そのィンダクタンス成分と自己のキ
ャパシタンス成分とにより並列共振回路を形成する。
To explain this configuration, 1 is a DC power supply, the positive side of which is connected to the center tap of the primary windings 5 and 6 of an oscillation transformer 4 via a power switch 2 and an inductor 3 in series.
A pair of transistors 7 and 8 are connected to both ends of the next windings 5 and 6 in a bush-pull manner. That is, transistors 7 and 8
Each collector is connected to both ends of the primary windings 5 and 6, and both emitters are connected to the negative pole side of the DC power supply 1, and each base is connected to the positive pole side of the power supply 1 through bias resistors 9 and 10, respectively. and the base winding 1 of the oscillation transformer 4.
Connected to 1. 12 is a capacitor, primary winding 5,
6, and its inductance component and its own capacitance component form a parallel resonant circuit.

13は発振トランス4の2次巻線で、図示省略の負荷に
接続される。
13 is a secondary winding of the oscillation transformer 4, which is connected to a load (not shown).

上記横成のィンバータ回路は、周知の如く起動時はトラ
ンジスタ7,8のいずれかをバイアス抵抗9,10を介
してターンオフさせ、また起動後はベース巻線11に誘
起される起動力によりトランジスタ7,8を交互にター
ンオン、ターンオフさせて2次巻線13に所定周波の交
流電力を誘起させる。即ち、ベース巻線11に誘起され
る電圧は1次巻線5,6のィンダクタンスとコンデンサ
12の容量とで決定される共振電圧と同期の正弦波の電
圧であり、その極性は共振に従って交番し、ベース巻線
11の極性によりバイアス抵抗9,10を介して流れる
電流をトランジスタ7のベースかトランジスタ8のベー
スに流し〜トランジスタ7,8をオンオフさせる。例え
ばベース巻線13の樋性が第1図のようになっている場
合、ベース巻線13の電圧によりトランジスタ8のべ−
ス、ェミッタ間が順方向トトランジスタ7のベース、ェ
ミッタ間が逆方向に電圧が印加される為、バイアス抵抗
1囚を介して流れる電流はトランジスタ8のベースに流
れ「バイアス抵抗9を介して流れる電流もベース巻線1
畳の巻線を通じてトランジスタ8のベースに流れ、トラ
ンジスタ8がオンになり「トランジスタTがオフになり
、ベース巻線11の極性が反転するとトランジスタ8が
オフしトランジスタ7がオンになる。そして〜トランジ
スタ7,8に流れるベース電流は直流電源1の電圧「バ
イアス抵抗9,奪Qの抵抗値及びベース巻線i lの電
圧で決定されるが、ベース巻線11の電圧の極性が反転
するときはトベース巻線1 翼に誘起される電圧は略P
Vとなる為〜 この時のベース電流は直流電源1の電圧
とバイアス抵抗9,10の抵抗値のみで決定される。ま
た「ベース巻線11の主な働きは直流電源亀よりバイア
ス抵抗9,IQを介して流れる電流をトランジスタ7,
8のどちらのベースに流すかを決定する事であり、ベー
ス巻線11に誘起する電圧を直流電源1の電圧により充
分低く設定すると、ベース電流は直流電源首の電圧及び
バイアス抵抗9,18の抵抗値のみにより決定される。
ところが、従来のインバータ回路では以下の問題がある
As is well known, in the Yokosei inverter circuit, at startup, either of the transistors 7 and 8 is turned off via bias resistors 9 and 10, and after startup, the transistor 7 is turned off by the starting force induced in the base winding 11. , 8 are turned on and off alternately to induce alternating current power of a predetermined frequency in the secondary winding 13. That is, the voltage induced in the base winding 11 is a sinusoidal voltage that is synchronous with the resonant voltage determined by the inductance of the primary windings 5 and 6 and the capacitance of the capacitor 12, and its polarity is alternated according to the resonance. However, depending on the polarity of the base winding 11, a current flows through the bias resistors 9 and 10 to the base of the transistor 7 or the base of the transistor 8, thereby turning the transistors 7 and 8 on and off. For example, if the base winding 13 has a groove as shown in FIG.
Since voltage is applied in the reverse direction between the base and emitter of transistor 7, the current flowing through bias resistor 1 flows to the base of transistor 8, and the current flows through bias resistor 9. Current is also base winding 1
It flows through the Tatami winding to the base of transistor 8, turns on transistor 8, turns off transistor T, and when the polarity of base winding 11 is reversed, transistor 8 turns off and transistor 7 turns on. The base current flowing through 7 and 8 is determined by the voltage of the DC power supply 1, the resistance value of the bias resistor 9, the resistance value of the bias resistor Q, and the voltage of the base winding I, but when the polarity of the voltage of the base winding 11 is reversed, The voltage induced in the base winding 1 blade is approximately P
The base current at this time is determined only by the voltage of the DC power supply 1 and the resistance values of the bias resistors 9 and 10. ``The main function of the base winding 11 is to transfer the current flowing from the DC power source through the bias resistor 9 and IQ to the transistor 7.
8, the voltage induced in the base winding 11 is set sufficiently lower than the voltage of the DC power supply 1, and the base current is equal to the voltage at the neck of the DC power supply and the bias resistors 9 and 18. Determined only by resistance value.
However, conventional inverter circuits have the following problems.

ベース巻線11の極性が反転すると、オフしていた一方
のトランジスタ7,81こはベース電流が流れ、ただち
にオンに移行するが、オンしていた他方のトランジスタ
7,8はその特性上ベース電流が流れなくなってもすぐ
にはオフ状態に移行せず一定期間遅れてターンオフし、
この期間トランジスタ79 8は同時にオンになり、イ
ンダクタ3が無い場合は直流電源1の両端がトランジス
タ7,8により短絡されたと同等になって「トランジス
タ7,8に大きな電流が流れ「大きな電力損が生じる。
即ち、1次巻線5,6は逆方に巻かれている為、トラン
ジスタ7,8が同時にオンになると1次巻線5,6のィ
ンダクタンスが無くなって大きな電流が流れ、ィンダク
タ3はトランジスタ7,8が同時にオンになたとき大き
な電流が流れるのを抑える効果があり、トランジスタ7
,8が同時にオンとあっても破損することは無いが、ス
イッチングロスが大きくなることは避けられない。しか
も、2次巻線13に接続されている負荷の大小によりト
ランジスタ7,8のコレクタ電流が負荷に対応して変化
する為、負荷が最大にあったときにおいてもトランジス
タ7,8が飽和状態であるようにそのベース電流を大き
く設定しておくのが一般であり、このため特に負荷が小
さくなったときはベース蟹流が必要ち久上に大きくなり
「ターンオフ時間が長くなって「スイッチングロスが増
大する。このスイッチングロスを小さくするには、ベー
ス電流を小さくしてトランジスタ?,8を非飽和状態で
動作するようにして、ターンオフ時間を短くすればよい
のであるが、このようにすればトランジスタ7,8のコ
レクタ、ェミツタ間の電圧が高くなり「 コレク夕、ェ
ミツタ間の電圧によるロスが大きくなる。つまり、ベー
ス電流を大きくするとスイッチングロスが大きくなり、
逆に小さくするとコレク夕Lェミツタ間の電圧によるロ
スが大きくなるという問題を生じる。そこで、ベース電
流を適当に制御し、トランジスタ7,8を飽和状態と不
飽和状態の中間に設定すると、コレクタ「 ェミッタ間
の電圧が低くなると共に、ベース電流を大きすぎず、ベ
ース、ェミツタ間の蓄積キャリアが少なくなってターン
オフ時間が短くなり、トランジスタ7,8が同時にオン
になる期間が短くなるので、上記2種類のロスを共に小
さくでき、問題は解消する。
When the polarity of the base winding 11 is reversed, base current flows through the transistors 7 and 81 that were off and immediately turns on, but due to their characteristics, the base current of the other transistors 7 and 8 that was on is Even if the current stops flowing, it does not immediately turn off, but turns off after a certain period of time.
During this period, transistors 79 and 8 are turned on at the same time, and if there is no inductor 3, it becomes equivalent to having both ends of the DC power supply 1 short-circuited by transistors 7 and 8, and a large current flows through transistors 7 and 8, resulting in a large power loss. arise.
That is, since the primary windings 5 and 6 are wound in opposite directions, when the transistors 7 and 8 are turned on at the same time, the inductance of the primary windings 5 and 6 disappears and a large current flows, and the inductor 3 becomes the transistor. This has the effect of suppressing the flow of a large current when transistors 7 and 8 are turned on at the same time.
, 8 are on at the same time, no damage will occur, but switching loss will inevitably increase. Furthermore, the collector currents of transistors 7 and 8 change depending on the load connected to the secondary winding 13, so even when the load is at its maximum, transistors 7 and 8 remain in a saturated state. Generally, the base current is set to a large value, so especially when the load becomes small, the base current becomes necessary. In order to reduce this switching loss, it is possible to reduce the base current so that the transistor 8 operates in a non-saturated state and shorten the turn-off time. The voltage between the collector and emitter of 7 and 8 increases, and the loss due to the voltage between the collector and emitter increases.In other words, when the base current is increased, the switching loss increases,
On the other hand, if it is made smaller, a problem arises in that the loss due to the voltage between the collector L emitter increases. Therefore, by appropriately controlling the base current and setting transistors 7 and 8 between the saturated state and the unsaturated state, the voltage between the collector and emitter will be lowered, and the base current will not be too large, and the voltage between the base and emitter will be reduced. Since the accumulated carriers are reduced, the turn-off time is shortened, and the period during which the transistors 7 and 8 are simultaneously on is shortened, both of the above two types of losses can be reduced, and the problem is solved.

しかしながら「 ある一定の負荷に対して、ベース電流
をトランジスタ7,8が不飽和と飽和の中間になる一定
電流に設定した場合、負荷が変動すると、最適なべ−ス
電流から大幅にずれ、ロスが大きくなる事がある。特に
負荷が大きくなって不飽和状態になったときには、ロス
は非常に大きくなり、インバータ回路の効率を顕著に改
善するに至っていない。本発明は上詫間題点を解消する
ことを目的とし、その特徴とするところは「直流電源1
の一端を、発振トランスの1次巻線の両端に一対のトラ
ンジスタを介して夫々接続すると共に、直流電源の池端
を前記1次巻線の中間タップに接続し、発振トランスの
ベース巻線から前記一対のトランジスタを交互に導適す
るように該トランジスタにべース電流を流すベース駆動
回路を設け、発振トランスの2次巻線に交流電圧を取出
すようにしたィンバータ回路において、抵抗と各トラン
ジスタに対して夫々順方向となる一対のダイオードとを
備える電圧検出回路を、前記抵抗とダイオードとの直列
回路が発振トランスの1次巻線に対して夫々並列になり
、かつその抵抗とダイオードとの接続点からトランジス
タのコレクタ、ェミツタ間のオン電圧に比例した比例電
圧を取出すように設け、前記電圧検出回路から比例電圧
を入力しかつ前記トランジスタが飽和状態と不飽和状態
の中間になるように該トランジスタのベース電流を制御
するベース電流制御素子を、前記ベース駆動回路に設け
た点にある。
However, ``If the base current is set to a constant value where transistors 7 and 8 are between unsaturated and saturated for a certain load, if the load fluctuates, the base current will deviate significantly from the optimal base current, resulting in loss. Especially when the load becomes large and becomes unsaturated, the loss becomes very large and the efficiency of the inverter circuit has not been significantly improved.The present invention solves the above problem. Its purpose is to
One end of the primary winding of the oscillation transformer is connected to both ends of the primary winding of the oscillation transformer through a pair of transistors, and the end of the DC power supply is connected to the intermediate tap of the primary winding, and the base winding of the oscillation transformer is connected to the In an inverter circuit in which a base drive circuit is provided to supply a base current to a pair of transistors so as to alternately conduct the transistors, and an alternating current voltage is taken out to the secondary winding of an oscillation transformer, the resistor and each transistor are A voltage detection circuit comprising a pair of diodes, each in the forward direction, is configured such that the series circuit of the resistor and the diode is parallel to the primary winding of the oscillation transformer, and the connection point between the resistor and the diode is A proportional voltage proportional to the ON voltage between the collector and emitter of the transistor is extracted from the voltage detection circuit, and the proportional voltage is input from the voltage detection circuit, and the voltage of the transistor is adjusted so that the transistor is between the saturated state and the unsaturated state. The present invention is characterized in that a base current control element for controlling the base current is provided in the base drive circuit.

以下、本発明を図示の実施例に従って説明すると、第2
図は本発明の一実施例を示し、同図において、葺4,1
5,16はダイオード、17は抵抗であり、これらは1
次巻線5,6のセンタータップである点Aからトランジ
スタ7,8のコレクタへ接続され「 これらダイオード
14,15,】6及び抵抗17によりトランジスタ7,
8のコレクタ、ェミッ夕闇のオン電圧を検出する電圧検
出回路18を形成している。
Hereinafter, the present invention will be explained according to the illustrated embodiments.
The figure shows an embodiment of the present invention, in which the roofs 4, 1
5 and 16 are diodes, 17 is a resistor, and these are 1
The point A, which is the center tap of the next windings 5 and 6, is connected to the collectors of the transistors 7 and 8.
8 forms a voltage detection circuit 18 that detects the on-voltage of the emitter.

19は新たに設けたトランジスタで、該トランジスター
9とバイアス抵抗9,10とでトランジスタ7,8にベ
ース電流を流すベース駆動回路20を形成し、バイアス
抵抗9,10を「上記ベース電流がトランジスタ7,8
を不飽和状態と飽和状態との中間になるように設定して
いる。
Reference numeral 19 denotes a newly provided transistor, and the transistor 9 and bias resistors 9 and 10 form a base drive circuit 20 that allows base current to flow through the transistors 7 and 8. ,8
is set to be between an unsaturated state and a saturated state.

上記実施例の構成によれば、トランジスタ7,8は交互
にオンするので、点Aより抵抗i7及びダイオード16
を介してダイオード14又はダイオード15に電流が流
れる。
According to the configuration of the above embodiment, since the transistors 7 and 8 are turned on alternately, the resistor i7 and the diode 16 are turned on from point A.
A current flows through the diode 14 or the diode 15.

即ちトランジスタ7がオンしているとき、点Aより抵抗
軍7及びダイオード16を介して電流が流れ、点C,B
間の電圧はトランジスタ7のコレクタ、ェミツタ間の電
圧にダイオード14のオン電圧(約0.7V)を加算し
た電圧になり、このときトランジスタ8はオフしている
為、ダイオード15には逆電圧が印加し電流が流れない
。又トランジスタ8がオンしているとき、点C,B間の
電圧はトランジスタ8のコレクタ、ェミッタ間の電圧と
ダイオード15のオン電圧の和となる。従って点Aより
抵抗17及びダイオード16を介して常に電流が流れる
為、点○,B間の電圧はトランジスタ7,8のオン電圧
+約1.4Vの電圧となる。そして、この点D,B間の
電圧にてトランジスタ19のェミッ夕よりバイアス抵抗
9,10を介してトランジスタ7,8にベース電流が流
れ、点Eの電圧は点Dの電圧よりトランジスタ19のベ
ース、ェミッタ間電圧(約0.7V)低くなり、点E,
B間の電圧はトランジスタ7,8のオン電圧+約0.7
Vとなる。またトランジスタ7,8のベース、ェミッタ
間の電圧は約0.7Vである為、トランジスタ7,登の
ベースと点E間の電圧はトランジスタ7,8のオン電圧
と等しくなり、バイアス抵抗97 181こ流れる翼流
はトランジスタ7,8のオン電圧に比例する事になる。
その結果、負荷が大きくなり、トランジスタ7,8のコ
レクタ電流が大きくなるとトそのベース電流が不足して
トランジスタ7,8が不飽和状態に移行し、コレクタ、
ヱミッタ間電圧が高くなるが、コレクタ、ヱミッタ間電
圧が高くなることによりベース電流が自動的に増加し、
不飽和状態に移行するのを防止する。反対に負荷が小さ
くなり、コレクタ電流が小さくなるとべ‐ス電流が大き
くなりすぎて飽和状態へ移行しようとするが、コレクタ
、ェミッタ間電圧が低下する為、ベース電流が自動的に
低下し飽和状態に移行することを防止する。従って、電
圧検出回路18はトランジスタ7,8のコレクタ、エミ
ツタ間のオン電圧を検出して該オン電圧に比例した比例
電圧を取出し、ベース駆動回路20は、トランジスタ7
,8に、それが飽和状態と不飽和状態の中間になるべく
電圧検出回路18の比例電圧に比例したベース電流を流
すのであり、負荷が変動してもトランジスタ7,8は常
に飽和状態と不飽和状態の中間に設定されるので、負荷
が増大しても常にコレクタ、ェミツタ間の電圧を低く抑
えることが可能となり、コレクタ、ェミツタ間電圧の上
昇によるロスを低くできる。また負荷が減少しても、ベ
ース電流の増加を防いでベース、ェミッタ間の蓄積キャ
リアを少なくでき、トランジスタ7,8のターンオフ時
間を短く抑えてトランジスタ7,8が同時にオンする期
間をほとんど無し、そのスイッチングロスを最小にでき
る。なお、前記実施例ではダイオードi6を設けトラン
ジスタ19のベース、ヱミッタ間電圧を補償しているが
、第3図に示す如くこのダイオードI6を無くし「トラ
ンジスタ7,8のベース電流がそのコレクタ「ェミッタ
間のオン電圧から約0.7Vを引いた値に比例するよう
にしてもよく、この場合ベース電流は前記実施例の場合
に比して小さくなり、トランジスタ7,8はやや不飽和
状態で動作し、同時にオンする期間はさらに短くなる。
That is, when the transistor 7 is on, a current flows from the point A through the resistor 7 and the diode 16, and the current flows from the point A to the point C and B.
The voltage between the collector and emitter of transistor 7 is the sum of the on-voltage of diode 14 (approximately 0.7V), and since transistor 8 is off at this time, a reverse voltage is applied to diode 15. No current flows when applied. When transistor 8 is on, the voltage between points C and B is the sum of the voltage between the collector and emitter of transistor 8 and the on-voltage of diode 15. Therefore, since a current always flows from point A through resistor 17 and diode 16, the voltage between points ○ and B becomes the on-voltage of transistors 7 and 8 plus about 1.4V. At this voltage between points D and B, a base current flows from the emitter of transistor 19 to transistors 7 and 8 via bias resistors 9 and 10, and the voltage at point E is higher than the voltage at point D at the base of transistor 19. , the emitter voltage (approximately 0.7V) decreases, and the point E,
The voltage between B is the ON voltage of transistors 7 and 8 + about 0.7
It becomes V. Also, since the voltage between the base and emitter of transistors 7 and 8 is approximately 0.7V, the voltage between the base of transistor 7 and point E is equal to the on-voltage of transistors 7 and 8, and the bias resistor 97 181 The flowing blade flow is proportional to the on-voltage of transistors 7 and 8.
As a result, when the load becomes large and the collector currents of transistors 7 and 8 become large, their base current becomes insufficient and transistors 7 and 8 go into an unsaturated state, and the collector currents become large.
The emitter voltage increases, but as the collector and emitter voltage increases, the base current automatically increases.
Prevents transition to unsaturated state. On the other hand, when the load becomes smaller and the collector current becomes smaller, the base current becomes too large and tries to enter the saturated state, but as the voltage between the collector and emitter decreases, the base current automatically decreases and the saturated state occurs. prevent the transition to Therefore, the voltage detection circuit 18 detects the on-voltage between the collectors and emitters of the transistors 7 and 8 and extracts a proportional voltage proportional to the on-voltage, and the base drive circuit 20 detects the on-voltage between the collectors and emitters of the transistors 7 and 8.
, 8, a base current proportional to the proportional voltage of the voltage detection circuit 18 flows as much as possible between the saturated state and the unsaturated state, so that even if the load changes, the transistors 7 and 8 are always in the saturated state and the unsaturated state. Since it is set in the middle of the states, it is possible to always keep the voltage between the collector and the emitter low even when the load increases, and it is possible to reduce the loss caused by the increase in the voltage between the collector and the emitter. Furthermore, even if the load decreases, the base current can be prevented from increasing and carriers accumulated between the base and emitter can be reduced, and the turn-off time of the transistors 7 and 8 can be kept short, so that there is almost no period in which the transistors 7 and 8 are turned on at the same time. The switching loss can be minimized. In the above embodiment, a diode i6 is provided to compensate for the voltage between the base and emitter of the transistor 19, but as shown in FIG. It may be made to be proportional to the value obtained by subtracting about 0.7V from the on-voltage of the transistor. In this case, the base current becomes smaller than that of the above embodiment, and the transistors 7 and 8 operate in a slightly unsaturated state. , the period in which they are simultaneously turned on becomes even shorter.

また第3図に2点鎖線Gで示す如く抵抗17を点Aの接
続に代え、電源1の正極側である点Fに接続してもよい
。さらに「電源として直流電源1を用いているが、これ
に代え交流を整流したものを用いてもよい。またトラン
ジスタ19のコレク外ま点Fに接続しなくてもよく「例
えば電源1の電圧が100Vより高い場合、トランジス
タ亀 9のロスが大きくなるので、新たに設けた10V
程度の別電源にこれを接続すれば、トランジスタ】9の
電力損を小さくできる。さらに、第4図に示す如くトラ
ンジスター9の代りにOPアンプ21を用いると共に〜
トランジスタ7,8の飽和と不飽和との中間となる電圧
約2〜3Vの別の基準電源22を新たに設けて、ベース
駆動回路20を形成し、基準電源22の電圧とトランジ
スタ7のコレクタ、ェミツタ間電圧が同一になるように
○Pアンプ21及びバイアス抵抗9,10‘こベース電
流を流すようにしてもよい。本発明によれば、交互に導
適する一対のトランジスタのコレクタ、ェミッタ間のオ
ン電圧に比例した比例電圧を取出す電圧検出回路を設け
、ベース駆動回路により前記トランジス外こ、それが飽
和状態と不飽和状態の中間になるべく前記電圧検出回路
の比例電圧に比例したベース電流を流すようにしている
ので、負荷が変動しても前記トランジスタを常に飽和状
態と不飽和状態の中間に設定でき、そのコレクタ「ヱミ
ツタ間電圧の上昇によるロスを低く抑えることができる
と共に、前記一対のトランジスタが同時にオンする期間
をほとんど無し、そのスイッチングロスを最小にでき〜
従ってィンバータ回路の効率を顕著に改善することが可
能となる。
Further, as shown by a two-dot chain line G in FIG. 3, the resistor 17 may be connected to a point F, which is the positive side of the power source 1, instead of being connected to the point A. Furthermore, ``Although the DC power source 1 is used as the power source, a rectified alternating current may be used instead.Also, it is not necessary to connect the terminal F to the outside of the transistor 19.''For example, if the voltage of the power source 1 is If it is higher than 100V, the loss of transistor 9 will be large, so the newly provided 10V
By connecting this to a separate power supply of about 100 Ω, the power loss of the transistor 9 can be reduced. Furthermore, as shown in FIG. 4, an OP amplifier 21 is used instead of the transistor 9, and...
Another reference power supply 22 with a voltage of about 2 to 3 V, which is intermediate between the saturation and unsaturation of the transistors 7 and 8, is newly provided to form the base drive circuit 20, and the voltage of the reference power supply 22 and the collector of the transistor 7, A base current may be made to flow through the ○P amplifier 21 and the bias resistors 9 and 10' so that the emitter-to-emitter voltages are the same. According to the present invention, a voltage detection circuit is provided which takes out a proportional voltage proportional to the on-voltage between the collector and emitter of a pair of transistors that are alternately conductive, and a base drive circuit detects whether the transistor is in a saturated state or an unsaturated state. Since the base current proportional to the proportional voltage of the voltage detection circuit is made to flow as much as possible between the states, even if the load fluctuates, the transistor can always be set between the saturated state and the unsaturated state, and its collector " It is possible to suppress the loss caused by the rise in the voltage between the emitters to a low level, and also to minimize the switching loss by almost eliminating the period in which the pair of transistors are simultaneously turned on.
Therefore, it becomes possible to significantly improve the efficiency of the inverter circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例を示す回路図、第2図は本発明の一実施
例を示す回路図、第3図及び第4図は夫々の他の実施例
を示す回路図である。 7,8…トランジスタ、亀8…電圧検出回路、20…ベ
ース 回路。 第1図 2図 第3図 第4図
FIG. 1 is a circuit diagram showing a conventional example, FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIGS. 3 and 4 are circuit diagrams showing other embodiments. 7, 8...transistor, turtle 8...voltage detection circuit, 20...base circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 1 直流電源1の一端を、発振トランジスタ4の1次巻
線56の両端に一対のトランジスタ7,8を介して夫々
接続すると共に、直流電源1の他端を前記1次巻線5,
6の中間タツプに接続し、発振トランス4のベース巻線
11から前記一対のトランジスタ7,8を交互に導通す
るように該トランジスタ7,8にベース電流を流すベー
ス駆動回路20を設け、発振トランス4の2次巻線13
に交流電圧を取出すようにしたインバータ回路において
、抵抗17と各トランジスタ7,8に対して夫々順方向
となる一対のダイオード14,15とを備える電圧検出
回路18を、前記抵抗17とダイオード14,15との
直列回路が発振トランス4の1次巻線5,6に対して夫
々並列になり、かつその抵抗17とダイオード14,1
5との接続点からトランジスタ7,8のコレクタ、エミ
ツタ間のオン電圧に比例した比例電圧を取出すように設
け、前記電圧検出回路18から比例電圧を入力しかつ前
記トランジスタ7,8が飽和状態と不飽和状態の中間に
なるように該トランジスタ7,8のベース電流を制御す
るベース電流制御素子19,21を、前記ベース駆動回
路20に設けたことを特徴とするインバータ回路。
1 One end of the DC power supply 1 is connected to both ends of the primary winding 56 of the oscillation transistor 4 via a pair of transistors 7 and 8, and the other end of the DC power supply 1 is connected to the primary winding 56 of the oscillation transistor 4.
A base drive circuit 20 is connected to the intermediate tap of the oscillation transformer 4 and causes a base current to flow from the base winding 11 of the oscillation transformer 4 to the pair of transistors 7 and 8 so as to alternately conduct them. 4 secondary winding 13
In an inverter circuit configured to take out an alternating current voltage at 15 are connected in parallel to the primary windings 5 and 6 of the oscillation transformer 4, respectively, and the resistor 17 and the diodes 14 and 1
A proportional voltage proportional to the ON voltage between the collectors and emitters of the transistors 7 and 8 is taken out from the connection point with the transistor 5, and the proportional voltage is inputted from the voltage detection circuit 18 and the transistors 7 and 8 are in a saturated state. An inverter circuit characterized in that the base drive circuit 20 is provided with base current control elements 19 and 21 that control the base currents of the transistors 7 and 8 so that the base currents are in an intermediate state between unsaturated states.
JP54163384A 1979-12-14 1979-12-14 inverter circuit Expired JPS6022595B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54163384A JPS6022595B2 (en) 1979-12-14 1979-12-14 inverter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54163384A JPS6022595B2 (en) 1979-12-14 1979-12-14 inverter circuit

Publications (2)

Publication Number Publication Date
JPS5686079A JPS5686079A (en) 1981-07-13
JPS6022595B2 true JPS6022595B2 (en) 1985-06-03

Family

ID=15772857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54163384A Expired JPS6022595B2 (en) 1979-12-14 1979-12-14 inverter circuit

Country Status (1)

Country Link
JP (1) JPS6022595B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6277296U (en) * 1985-10-31 1987-05-18
JPH0329438Y2 (en) * 1984-11-01 1991-06-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0329438Y2 (en) * 1984-11-01 1991-06-24
JPS6277296U (en) * 1985-10-31 1987-05-18

Also Published As

Publication number Publication date
JPS5686079A (en) 1981-07-13

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