JPS60224246A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60224246A
JPS60224246A JP7941984A JP7941984A JPS60224246A JP S60224246 A JPS60224246 A JP S60224246A JP 7941984 A JP7941984 A JP 7941984A JP 7941984 A JP7941984 A JP 7941984A JP S60224246 A JPS60224246 A JP S60224246A
Authority
JP
Japan
Prior art keywords
wiring
shield electrode
shield
electrode
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7941984A
Other languages
Japanese (ja)
Inventor
Yasushi Okawa
泰史 大川
Kenichi Oki
沖 賢一
Terunobu Miura
三浦 照信
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7941984A priority Critical patent/JPS60224246A/en
Publication of JPS60224246A publication Critical patent/JPS60224246A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the yield rate, by fixing a shield electrode at a DC potential, so that the effect of the short between the shield electrode and a wiring by an accident does not affect the entire device. CONSTITUTION:Shield electrodes 29 are provided only on a wiring and constituent transistors T1-T3, which are subject to external light and external electric fields. Their potentials are kept at the potentials corresponding to the driving conditions of wirings and elements. The shield electrode is not provided on a grounding bus line 30 and the wirings, which are not subject to the external effects. The wiring for connecting the shield electrode and the wiring under the shield wiring are arranged so that they are not crossed each other. Therefore, even though the shield electrode is short-circuited with the wirings, the entire address circuit does not become inoperative. The semiconductor device having this structure can be obtained in this way.

Description

【発明の詳細な説明】 (a)0発明の技術分野 本発明はデータアドレス部とこれによりアドレスされる
マトリクス部を含んだメモリ装置や、アクティブマトリ
クス型表示装置等に使用される半導体装置のシールド電
極を有する構造の装置の改良に関する。
Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a shield for a semiconductor device used in a memory device including a data address section and a matrix section addressed by the data address section, an active matrix type display device, etc. This invention relates to an improvement in a device having a structure having electrodes.

(b)、技術の背景 上記の半導体装置、特にアクティブマトリクス型表示装
置等においては、データアドレス部のシフトレジスタ等
が外部光や表示媒体からの発光や、さらに表示媒体の駆
動電圧等の影響により動作不良を起こすため、このよう
なおそれのある半導体装置では、データアドレス部に光
および電気のシールドが必要となる。このためシールド
が完全にとれて、しかもシールドを設けたことに起因す
る歩留りの低下が起こらないような構造が望まれている
(b), Technical Background In the above-mentioned semiconductor devices, especially active matrix display devices, the shift registers in the data address section are affected by external light, light emission from the display medium, and the drive voltage of the display medium. In order to cause malfunctions, semiconductor devices that are susceptible to such problems require optical and electrical shielding in the data address section. For this reason, there is a need for a structure in which the shield can be completely removed and the yield will not be lowered due to the provision of the shield.

(C)、従来技術と問題点 第1図は従来例によるデータアドレス部とこれによりア
ドレスされるマトリクス部を含んだ半導体装置の構成を
示す平面図である。
(C), Prior Art and Problems FIG. 1 is a plan view showing the structure of a semiconductor device including a data address section and a matrix section addressed by the data address section according to a conventional example.

図において、1はマトリクス部を示し、メモリセルや表
示セルを2次元に配列して構成され、2゜3はそれぞれ
X、Yデータアドレス回路を示し、多段のシフトレジス
タ等により構成されている。
In the figure, 1 indicates a matrix section, which is constructed by arranging memory cells and display cells two-dimensionally, and 2 and 3 indicate X and Y data address circuits, respectively, which are composed of multi-stage shift registers and the like.

4.5はシールド電極で絶縁層を介してそれぞれデータ
アドレス回路2,3全体を覆い、接地電位に保っている
4.5 is a shield electrode that covers the entire data address circuits 2 and 3, respectively, via an insulating layer, and maintains them at ground potential.

ところが、このような構造ではシールド電極下の配線と
、シールド電極間に短絡を生じた場合に、信号線や電源
線が接地されてしまうため、データアドレス回路全体が
動作不良となり、製造歩留りを大幅に引き下げることに
なる。
However, with this structure, if a short circuit occurs between the wiring under the shield electrode and the shield electrode, the signal line or power line will be grounded, causing the entire data address circuit to malfunction, significantly reducing manufacturing yield. It will be lowered to

第2図は従来例による電極構造を示す断面図である。FIG. 2 is a sectional view showing a conventional electrode structure.

図において21は珪素等よりなる基板、22は二酸化珪
素等よりなる絶縁層、23〜27は配線電極で例えば、
23は電源パスライン、24はトランジスタのソース電
極、25はトランジスタのゲート電極、26はトランジ
スタのドレイン電極、27は信号パスライン、28はシ
ールド電極である。
In the figure, 21 is a substrate made of silicon or the like, 22 is an insulating layer made of silicon dioxide, etc., and 23 to 27 are wiring electrodes, for example,
23 is a power supply pass line, 24 is a source electrode of a transistor, 25 is a gate electrode of a transistor, 26 is a drain electrode of a transistor, 27 is a signal pass line, and 28 is a shield electrode.

図示されるように、A−Hにおいてシールド電極と配線
の短絡が発生したと考える。例えばAの個所で短絡すれ
ば電源パスライン23は接地電位になり、これにつなが
るすべての素子が動作しなくなる。またEで短絡した場
合は信号パスライン?7が接地電位(一般には“L”レ
ベル)になり、やはり素子は動作しなくなる。
As shown in the figure, it is considered that a short circuit between the shield electrode and the wiring occurred at A-H. For example, if a short circuit occurs at point A, the power supply path line 23 becomes ground potential, and all elements connected to it become inoperable. Also, if there is a short circuit at E, is it a signal path line? 7 becomes the ground potential (generally "L" level), and the element no longer operates.

(d)1発明の目的 本発明の目的は従来技術の有する上記の欠点を除去し、
シールド電極と配線間が短絡しても、データアドレス回
路全体が動作不良となることを防止する構造を有する半
導体装置を提供することにある。
(d)1 Objective of the invention The objective of the present invention is to eliminate the above-mentioned drawbacks of the prior art,
An object of the present invention is to provide a semiconductor device having a structure that prevents the entire data address circuit from malfunctioning even if a short circuit occurs between a shield electrode and a wiring.

(e)0発明の構成 上記の目的は本発明によれば、データアドレス回路上に
絶縁層を介して島状に分割したシールド電極を設け、該
シールド電極を電気的なシールドの不必要な配線電極の
直流電位に固定するようにした半導体装置により達成さ
れる。
(e) 0 Structure of the Invention According to the present invention, a shield electrode divided into island shapes is provided on a data address circuit via an insulating layer, and the shield electrode is connected to a wiring line that does not require electrical shielding. This is achieved by a semiconductor device whose electrodes are fixed at a DC potential.

本発明によれば、シールド電極を直流電位に固定するこ
とにより、シールド電極と配線が万一短絡した場合でも
その影響が装置全体におよばないようにして、歩留りの
向上が期待できる。
According to the present invention, by fixing the shield electrode to a direct current potential, even if the shield electrode and the wiring should be short-circuited, the effect of the short-circuit will not affect the entire device, and an improvement in yield can be expected.

(f)1発明の実施例 第3図、第4図は本発明による電極構造を示すA−A矢
視断面図と平面図を模式的に示す。以下の図において第
2図と同一番号は同一対象物を示す。
(f) 1 Embodiment of the Invention FIGS. 3 and 4 schematically show a sectional view taken along the line A-A and a plan view showing an electrode structure according to the invention. In the following figures, the same numbers as in FIG. 2 indicate the same objects.

図において、23a、23bは電源パスライン、27a
In the figure, 23a and 23b are power supply path lines, 27a
.

27bは信号パスライン、29a 、 29bは島状シ
ールド電極、30は接地パスライン、T1〜T3は構成
素子であるトランジスタを示す。
27b is a signal path line, 29a and 29b are island-shaped shield electrodes, 30 is a ground path line, and T1 to T3 are transistors which are constituent elements.

図に示されるように、シールド電極は外部光や外部の電
界により影響を受けるおそれのある配線や構成素子であ
るトランジスタの上部にのみ設けてあり、それらの電位
は、各配線や素子の駆動条件に応じた電位に保っておく
As shown in the figure, the shield electrode is provided only above the wiring and component transistors that may be affected by external light and external electric fields, and their potential is determined by the driving conditions of each wiring and element. Keep the potential at the appropriate level.

また接地パスライン30や、外部からの影響を受けない
配線上にはシールド電極を設けないようにし、シールド
電極を接続する配線と下側の配線とはできるだけ交叉し
ないようにする。
Also, shield electrodes are not provided on the ground pass line 30 or on wiring that is not affected by external influences, and the wiring connecting the shield electrode and the lower wiring are prevented from intersecting as much as possible.

くっ0発明の効果 以上詳細に説明したように本発明によれば、シールド電
極と配線間が短絡しても、データアドレス回路全体が動
作不良となることを防止する構埠を有する半導体装置を
得ることができる。
Effects of the Invention As described in detail above, according to the present invention, a semiconductor device having a structure that prevents the entire data address circuit from malfunctioning even if there is a short circuit between the shield electrode and the wiring can be obtained. be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例によるデータアドレス部とこれによりア
ドレスされるマトリクス部を含んだ半導体装置の構成を
示す平面図、第2図は従来例による電極構造を示す断面
図、第3図、第4図は本発明による電極構造を示す断面
図、と平面図なある。 図において、1はマトリクス部、2.3はそれぞれX、
Yデータアドレス回路、4.5はシールド電極、21は
基板、22は絶縁層、23〜27は配線で23は電源パ
スライン、24はトランジスタのソース電極、25はト
ランジスタのゲート電極、26はトランジスタのドレイ
ン電極、27は信号パスライン、2Bはシールド電極、
29は島状シールド電極、30は接地パスライン、T 
I”” T sは構成素子であるトランジスタを示す。 軍j 聞 第2図 隼3阿 第4問
FIG. 1 is a plan view showing the structure of a semiconductor device including a conventional data address section and a matrix section addressed by the data address section, FIG. 2 is a cross-sectional view showing an electrode structure according to the conventional example, and FIGS. The figures are a cross-sectional view and a plan view showing the electrode structure according to the present invention. In the figure, 1 is the matrix section, 2.3 is X,
Y data address circuit, 4.5 is a shield electrode, 21 is a substrate, 22 is an insulating layer, 23 to 27 are wiring lines, 23 is a power supply path line, 24 is a source electrode of a transistor, 25 is a gate electrode of a transistor, 26 is a transistor 27 is a signal path line, 2B is a shield electrode,
29 is an island-shaped shield electrode, 30 is a ground pass line, T
I''''Ts indicates a transistor which is a constituent element. Military j question number 2 Hayabusa 3A question 4

Claims (1)

【特許請求の範囲】[Claims] データアドレス回路上に絶縁層を介して島状に分割した
シールド電極を設け、該シールド電極を電気的なシール
ドの不必要な配線電極の直流電位に固定するようにした
ことを特徴とする半導体装置。
A semiconductor device characterized in that a shield electrode divided into islands is provided on a data address circuit via an insulating layer, and the shield electrode is fixed to a DC potential of a wiring electrode that does not require electrical shielding. .
JP7941984A 1984-04-20 1984-04-20 Semiconductor device Pending JPS60224246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7941984A JPS60224246A (en) 1984-04-20 1984-04-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7941984A JPS60224246A (en) 1984-04-20 1984-04-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60224246A true JPS60224246A (en) 1985-11-08

Family

ID=13689344

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7941984A Pending JPS60224246A (en) 1984-04-20 1984-04-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60224246A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150189A (en) * 1986-02-28 1992-09-22 Canon Kabushiki Kaisha Semiconductor apparatus
US5594267A (en) * 1991-03-27 1997-01-14 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5150189A (en) * 1986-02-28 1992-09-22 Canon Kabushiki Kaisha Semiconductor apparatus
US5594267A (en) * 1991-03-27 1997-01-14 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same

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