JPS6022379A - Semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate the assembling and the output synthesizing by a method wherein a group of semiconductor single crystal layer consists of two layers of a P type layer and an N type layer having a distribution of impurity concentration, wherein an avalanche oscillation can be triggered off, and the two groups or more are repeatedly and continuously formed. CONSTITUTION:A group of semiconductor single crystal layer consists of two layers of a P type layer and an N type layer having a distribution of impurity concentration, wherein an avalanche oscillation can be triggered off, and the two groups or more are repeatedly and continuously formed by an epitaxial growth method. Each group consisting of the N type layer and the P type layer forms an oscillating region. According to such a method, the difficulty of assembling to be performed by the conventional method, as seen in the case of series connection in chips, is eased, and the output synthesizing dependent on the stray inductances of connecting lead wires is made easy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor device, and particularly to a high frequency, crystal output semiconductor device 1C that utilizes the abancié effect.

[Prior art]

The Impasso Dimade, which utilizes the avalanche effect in the PN junction or Schottky junction, is a very important element as a microwave homogeneous oscillation source. As with other devices, higher frequencies and higher outputs are desired29. For example, attempts have been made to connect chips in parallel or in series in order to increase output. However, parallel connection is almost the same as increasing the electrode area of the l-chip, and as the number of connected elements increases, the impedance of the element decreases and matching with an external circuit becomes difficult. On the other hand, in series connection, as the number of connected devices increases, impedance increases and matching with an external circuit becomes easier. In this way, serial connection is more advantageous in terms of matching with external circuits, but on the other hand, in terms of ease of assembly, it is better to connect chips in series.
) is much more difficult than parallel connection. In addition, there were many shortcomings, such as poor output control due to the stray inductance of the lead wires connecting the chips.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-frequency, high-output semiconductor device that eliminates the above-mentioned drawbacks, is easy to assemble, and has improved output synthesis.

[Structure of the invention]

The semiconductor device of the present invention is a semiconductor device having a PN junction and utilizing an avalanche effect, which includes a pair of semiconductor single crystal layers consisting of two layers of P-type and N-type, each having an impurity concentration distribution capable of avalanche oscillation. Two or more sets of single crystal layers are repeatedly and continuously formed, and the single crystal layers are connected in series as an oscillation element.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing an impurity concentration distribution in one embodiment of the present invention. In the figure, the vertical axis is the absolute cylinder of impurity concentration, and the horizontal axis is the distance from the surface. N+ is a low-resistance N-type semiconductor substrate, on which a high-resistance N-type layer is epitaxially grown, and a low-resistance P-type layer, P+, is also epitaxially grown over the high-resistance N-type layer. It has a type 9 g.

The Nm layer and Pm layer are further grown repeatedly, three times in total. Each set consisting of an N-type layer and a P-type layer forms an oscillation region, and in this disaster example, an SDR (Si
Same as the concentration distribution of DrifO type inva-in-butt diode, for example, when the oscillation frequency is 10 GHz, the thickness of the N-type layer, fA degree, and the thickness and concentration of the P-type layer are each 5 to 6 μm, 8 x 10" 5cInshi and 2~
It is sufficient to select 3 μm and 10 tyn.

In this case, the conventional 81) R type in-pad diode is
This means that devices connected in series can be made with one chip. Crystal growth is carried out by liquid phase growth using the sliding boat method or MBE (molecular beatnEp 1t).
axy) etc.

It is clear from the above explanation that by changing the impurity concentration distribution of the N-type and P-type layers, it is possible to connect a DDR (Double pre ft) type invat diode and a lead type invat diode in series within one chip. It is.

〔Effect of the invention〕

As explained above, the present invention eliminates the drawbacks of conventional serial connection of chips, such as difficulty in assembly and difficulty in output synthesis due to stray inductance of connection lead wires, and A high-frequency, high-output semiconductor device in which this process is successfully performed can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the impurity @degree distribution of gold according to an embodiment of the present invention. ＼−１ ￥1ヅ

Claims (1)

[Claims] In a semiconductor device that has a PN junction and utilizes the avalanche effect, impurity concentration distribution t that allows avalanche oscillation
Two or more sets of semiconductor single crystal layers consisting of two layers, P type and N type, are repeatedly and continuously formed, and the single crystal layers are connected in series as an oscillation element? ! -Featured semiconductor device.