JPS6022363A - Manufacture of mis dynamic memory cell - Google Patents

Abstract

PURPOSE:To reduce the coupling capacity CG of a p<+> layer and a word wire by a method wherein a linear CVDSiO2 is formed on the side wall of a gate electrode, and the overlapping of the p<+> layer and the gate electrode is prevented in a self-matching manner. CONSTITUTION:After a thermal oxide film 12 has been formed on the whole surface of a p type substrate 11, Si3N4 13 is deposited on the whole surface of said film 12, and the Si3N4 13 located on the area other than the region where an element will be formed is removed by etching. Then, a thick thermal oxide film 15 is formed on an element isolation region. Resist 16 is covered, and p-well is formed. Subsequently, a gate electrode 18 is formed by performing a patterning, and a CVDSiO2 19 is deposited on the whole surface. Said CVDSiO2 19 is left on the side wall part only of the gate electrode. Then, a p<+> layer 20 is formed. At this time, care is to be given to prevent the overlapping of a p<+> layer and a gate. Then, an n<+> layer is formed. Besides, a CVDSiO2 26 is deposited on the whole surface, an aperture is provided on the n<+> diffusion layer 27 which will be turned to a bit line, Al is deposited, and a metal wiring 26 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor memory device, and more particularly to a method for manufacturing a J-flow sense type box OS dynamic RAM cell.

[Prior art and its problems]

It is expected that the density of dynamic memory will continue to increase in the future.
In the Capacitor method, leak...ζ flow +7
) Since it is important to reduce the area of the cell capacitor, it is expected that a cell system that can be used for current amplification within the memory cell will be available until high integration becomes possible. An example of this method is K, T'er
ada, etal”ANew V L S I Memo
ry Ce1l TJs ing (:apacita
nce Couol-ing', IEDM, 198
2. A cross-sectional view of this memory cell structure is shown in FIG. 1, and an equivalent circuit is shown in FIG.

The structure is as follows: A common 0MO8 structure 7-2-3-6 is made under the gate (8) of the switching transistor on a P-type substrate, the p-layer layer (6) is used as a floating gate, and a junction y ( junkti
on) FET (1-4-6) is formed. (
Figure 1) The principle is that in the shading operation, the word line (8)
Set to a negative voltage, turn on the PMO8F"ET of Q, and set p"1ayer (6) to Ov on the substrate'.

Writing 'O"% 1 // is determined by the bit line potential. By changing the amount of charge stored in the capacitance CNW (Fig. 2 24) between the p layer 1ayer and the bit line n+ by the bit line, When the bit line is at a positive voltage, 1θ' is the p layer 1ayer (6
) is written to. After the write operation, the word line voltage is set to O.
Return to v, and make the p layer electrically floating.

The bit line of the cell in which '1# is written is changed from a positive voltage to Ov.
, the potential of the p layer becomes a negative potential due to the capacitance CNW (24) with the bit line, and the junction
FET is cut off. At this time, gate (8)
Coupling capacitance C between and p layer (6)
The smaller G (23) is, the smaller t is, the lower the voltage of the p layer is -7 ≦, and the cut off of junction1i' E T is complete. Due to the lateral spread of the implanted components and the thermal diffusion caused by thermal annealing for the social activation of the implanted 41I material, it is inevitable that p
The layer -71- gets in there and the CG becomes large. In this case, even if the cell voltage line written with 11" is changed from a positive voltage to OV, the voltage between the p layer and the p-layer does not drop sufficiently, and the ju
tion FET is not cut off enough and V+
The voltage of (7) is transmitted to the 13it line, and 11" cannot be sufficiently extracted. This point was the M point between Capacity't 3nce Coupling type cells in the 1) ε technique.

[Date of invention]

The present invention provides the above-mentioned Capacitance Couple.
This was done to improve the cut off characteristic of the bit line signal when the '1/TH of the ng, jlq cell is read. There is a big difference in the numbers (: apa-citance C
The purpose is to provide an uping type cell.

[Summary of the invention]

The present invention uses Capacitance Couple i to increase the signal difference when reading 11'' and 0#.
Coupling capacitance C between the p layer of the ng type cell and the word 1 gland
6, a linear CVD5iot is formed on the side wall of the gate electrode, and ions are implanted to form the p-layer in the same state, so that the p-layer and the gate electrode do not overlap in a self-aligned manner. Do it like this.

〔Effect of the invention〕

According to the present invention, (: apacitance couple
The coupling capacitance between the word line of the ing type cell and the p layer can be significantly reduced, and therefore,
It is possible to widen the readout signal difference between '12 and 10'. Therefore, when reading out cell fermentation information with a sense amplifier, it is possible to increase the sensitivity of the sense amplifier and enable highly sensitive detection. By enabling highly sensitive detection, the detection speed of cell cleanup can be increased.
It is possible to realize a high-performance dynamic RAM with fast access time.

[Embodiments of the invention]

Embodiments of the present invention will be described below in the order of manufacturing method process diagrams and FIGS.

P-type (IOO) substrate (11
) to protect the Si surface (12) f
After the formation, Si, N, (13) is deposited on the entire surface, and the area outside the element forming area is removed by etching. This iron,
A channel stop B+ is implanted in the element isolation region. (1%) (Figure 3 (a)) Next, thermal oxidation is performed using Si3N4 as a mask, and a thick thermally atomized film (
15). After this, a part of the element isolation region is covered with a resist (16), and (b) this is used as a mask for p
and form a p well (17). After that, the resist is removed by etching, and a gate electrode (18) which will become a word line is patterned and formed, and a CV
Deposit D5' Ot (19). (Third cause G/-
1) Next, C'VDSi is etched by directional ion etching.
O&etch and cvasto on the sidewalls of the gate electrode.
CVD5i02 (19) is left only on the side wall of the gate electrode by taking advantage of the fact that t is thick (attached).
, S j' Ot and B+ as a mask for the gate electrode.
is implanted to form a p layer (20)i. [See FIG. 3] At this time, the cvi) sio2 thickness and the acceleration energy during implantation of B+ are adjusted so that the p+ layer and the gate do not overlap.

Next, a resist (21) is patterned to partially cover the nth side of the gate electrode 1, and using this as a mask, p+ is implanted to form a B+ layer (22)'il-. (Figure 3 (E)) Next, the resist (21)'j) was etched away, CVD S r 02 (26) was almost crushed on the entire surface, and CVD5iO! on the n+ diffusion lip (27) which became the bit line!
Drill a hole in.

By depositing A4 on the entire surface and patterning it, the metal wiring (26) of the bit line is formed.

[Brief explanation of drawings]

Figure 1 shows Capacitance (:
A sectional view of an upling type cell, FIG. 2 is its equivalent circuit diagram, and FIGS.
nce Coupling type cell process UI is on the same page. Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 2 Figure 8 B+

Claims (1)

[Claims] (1) Has one bit line and one word line, and has one
The gates connected to two word lines are pch and nch
The two 1VIIsFFJTc/) gates are co-ML,
Only the source of the IVf ISFET is made floating, and this floating source serves as the gate of the junction FET.
When writing information, charge is stored in the floating gate using the capacitive coupling between the Bit line and the floating gate, and the junction FET is turned on and off.
In a read-out type memory cell with 200 mm, an insulating film is deposited on the entire surface after forming the PolySi that forms the word line.
(2) Taking advantage of the fact that the insulating film is thickly deposited on the sidewalls of Po1ySi, the entire insulating film is subjected to directional ion etching, leaving the insulating film in a linear form only on the sidewalls of Po1ySi, and the gate and The floating source ion implantation process uses the sidewall insulating film as a mask, which eliminates the overlap between the floating source and gate.