JPS60223349A - Speed converting circuit - Google Patents

Abstract

PURPOSE:To prevent data errors by inputting an output from register in parallel with a parallel/serial converting circuit with a timing signal in synchronization with a burst signal to control the circuit thereby decreasing the phase difference of both parallel inputs. CONSTITUTION:A low-speed clock CLK-L and a universal signal phase signal PH are inputted both to a timing generating circuit 6. The timing generating circuit 6 consists of a shift register and generates two kinds of timing signals. The two kinds of the timing signals are shifted mutually by N/2 bits. A phase comparison circuit 5 compares the two kinds of timing signals generated by the timing generating circuit 6 with the phase in a burst signal phase signal PH' and controls changeover switches 7, 8 to select a larger phase difference more than a specified value. That is, a signal (2) is transferred from a register 3 to a converting circuit 4 by using the burst phase signal PH' through the timing signal (4) in the figure, arranged into a prescribed location by a high speed clock CLK-H and becomes a burst signal and then is outputted to an output terminal OUT.

Description

Detailed Description of the Invention (a) 1 Technical Field of the Invention The present invention relates to a speed conversion circuit for converting a universal signal into a burst signal in a PCM communication terminal equipment, and particularly relates to a speed conversion circuit that converts a universal signal into a burst signal in a PCM communication terminal equipment, and particularly relates to a speed conversion circuit that converts a universal signal into a burst signal in a PCM communication terminal equipment. This invention relates to a speed conversion circuit for reducing errors that occur during speed fluctuations.

(b) Background of the Technology Recently, there has been an increase in the number of cases in which not only voice signals are input to terminal equipment for PCM communications, but also signals having direct PCM codes are input.

(C)6 Prior art and problems According to the prior art, the speed conversion circuit that converts the universal signal into a burst signal in the terminal equipment of PCM communication is configured using an elastake store (ES). .

This elastic store has the disadvantage that it is expensive, and the control circuit around the elastic store is also expensive.

(d)9 Object of the invention The object of the invention is to eliminate the above-mentioned drawbacks of the prior art,
To provide a speed conversion circuit that can be realized with a simple configuration using general-purpose gates and registers and is therefore inexpensive.

(e) 9 Structure of the Invention According to the present invention, the above object is to provide a device having a function of dividing a universal signal synchronized with a low-speed clock into a plurality of N-bit burst signals synchronized with a high-speed clock and converting the same into N-bit burst signals synchronized with a high-speed clock. a first register that accommodates N/2 bits of a universal signal input in serial format; an N-bit serial-parallel circuit that converts the universal signal input in serial format and the output signal of the first register into a parallel format signal; a conversion circuit, an N-bit second register that accommodates a parallel signal output from the conversion circuit; A parallel-to-serial conversion circuit, and means for generating two timing signals with a phase difference of N/2 bits of the low-speed clock as a parallel input timing signal of the second register and selecting one of them. , the timing signal selected by the means and the parallel
When the phase difference between the input timing signals of the serial conversion circuit is smaller than a predetermined value, the parallel input timing signal of the second register is switched to another timing signal, and the parallel input timing signal of the second register is switched in conjunction with the selection of the parallel input timing signal of the second register. This is accomplished by providing a speed conversion circuit that selects the universal signal and the second register output to serve as the serial input signal of the serial-to-parallel conversion circuit.

That is, according to the present invention, a universal signal input in serial format and a parallel signal are written in a register using a timing signal synchronized with the universal signal, and the output is written in parallel to a parallel-serial conversion circuit using a timing signal synchronized with a burst signal. input, and control the phase difference between the two parallel inputs to be small to prevent data errors.
By compensating the phase of the output signal depending on the presence or absence of a bit register, it is possible to realize a speed conversion circuit with a simple configuration using general-purpose gates and registers, and therefore at a low price.

(f)0 Embodiment of the Invention FIG. 1 is a block diagram showing an embodiment of a speed conversion circuit according to the invention.

FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1.

In the figure, 1 is a register that accommodates N/2 bits of the universal signal input in serial format, 2 is a circuit that converts an N-bit serial format signal into a parallel format signal, and 3 is an N-bit parallel signal. a register that houses the
4 is a circuit that converts an N-bit parallel format signal into a serial format signal, 5 is a phase comparison circuit, 6 is a timing generation circuit, 7 and 8 are respective changeover switches, IN is an input terminal of the speed conversion circuit, and OUT is a Output terminal of speed conversion circuit, C
LK-L is a low-speed clock, CLK-H is a high-speed clock,
PH is the universal signal phase signal and PH' is the burst signal phase signal.

The present invention will be described in detail below with reference to the drawings.

In FIG. 1, a universal signal in serial format is applied to input terminal IN. Further, the low speed clock CLK-L is a clock signal extracted from the universal signal, and the universal signal phase signal PH is a signal indicating the leading position of N bits. Note that N indicates the bit length of the burst signal.

Both the low-speed clock CLK-L and the universal signal phase signal PH are input to the timing generation circuit 6. The timing generation circuit 6 is composed of a shift register and generates two types of timing signals. These two types of timing signals are shifted from each other by N/2 bits.

When the changeover switch 7 is now in the contact position shown by the solid line in FIG. 1, the N-bit universal signal is directly input to the conversion circuit 2. This situation is shown in ■ in Figure 2.

When the changeover switch 7 takes the contact position shown by the dotted line in FIG. 1, the N-bit universal signal enters the conversion circuit 2 via the register 1. Therefore, in this case, the universal signal will be delayed by N/2 bits. This situation is shown in ■ in Figure 2.

The two types of timing signals generated by the timing generation circuit 6 are generated at the time when the input of the universal signal to the conversion circuit 2 is completed, as shown in ■ and ■ in FIG. 2, and in the case of ■, the timing signal shown in ■ , ■, the universal signals accommodated in the conversion circuit 2 are transferred to the registers 3 by the timing signals shown in ■. In this case, it is necessary to prevent the register 4 from changing while reading data from the conversion circuit 4 using the burst signal phase signal PH'.

Therefore, the phase comparison circuit 5 uses the two types of timing signals generated by the timing generation circuit 6 and the burst signal phase signal PH.
The changeover switches 7 and 8 are controlled so as to compare the phases of `` and select the one whose phase difference is larger than the specified value.

That is, the symbol (■) in FIG. 2 indicates the burst signal phase signal PH'. Since the burst signal phase signal PH' shown in (2) substantially overlaps with the timing signal shown in (2), the timing signal shown in (2) is selected.

That is, the signal (2) is transferred from the register 3 to the conversion circuit 4 by the burst signal phase signal PH' by the timing signal (2) in FIG. 2, and the signal (2) in FIG.
The signals are arranged at the positions shown in FIG. 1 to form a burst signal, which is output to the output terminal 0tJT.

(g1 Effects of the Invention As described in detail above, the present invention has the great effect of being able to realize a speed conversion circuit with a simple configuration using general-purpose gates and registers, and therefore at a low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a speed conversion circuit according to the present invention, and FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. In the figure, 1 is a register that accommodates N/2 bits of a universal signal input in serial format, 2 is a circuit that converts an N-bit serial format signal into a parallel format signal, and 3 is an N-bit parallel signal. a register that houses the
4 is a circuit that converts an N-bit parallel format signal into a serial format signal, 5 is a phase comparison circuit, 6 is a timing generation circuit, 7 and 8 are respective changeover switches, IN is an input terminal of the speed conversion circuit, and OUT is a Output terminal of speed conversion circuit, C
LK-L is a low-speed clock, CLK-H is a high-speed clock,
PH is the universal signal phase signal and PH' is the burst signal phase signal. early first day

Claims (1)

[Claims] In a device that has a function of dividing a universal signal synchronized with a low-speed clock into N-bit burst signals synchronized with a high-speed clock, N/2 bits of the universal signal input in serial format are converted into N-bit burst signals synchronized with a high-speed clock. an N-bit serial-to-parallel conversion circuit for converting a universal signal inputted in serial format and an output signal of the first digitizer into a parallel format signal; 2 register, an N-bit parallel-to-serial conversion circuit that inputs the parallel output signal of the second register according to the phase signal of the burst signal and outputs it in serial format according to the high-speed clock, and a parallel input timing signal of the second register. comprising means for generating two timing signals with a phase difference of N/2 bits of the low-speed clock and selecting one of them, the timing signal selected by the means and the parallel-to-serial conversion circuit; When the phase difference between the input timing signals of is smaller than a predetermined value, the parallel input timing signal of the second register is switched to another timing signal, and in conjunction with the selection of the parallel input timing signal of the second register, the universal signal and A speed conversion circuit characterized in that the second register output is selected and used as a serial input signal of the serial-parallel conversion circuit.