JPS60223331A - Differential modulator - Google Patents

Abstract

PURPOSE:To obtain the titled modulator suitable for circuit integration by bringing a clock frequency to 1/2<2/3> for the same noise level with less number of added elements and constituting a signal coder with simple structure. CONSTITUTION:A voltage signal inputted from a signal input terminal 11 is impressed to an adder 12 in a form of a charge by a means 18 converted into a charge proportional to the voltage signal. When an output of an integration device 13 exceeds 1/2Vp succeedingly, a vharge corresponding to a -Vp is fed to the adder, and when the output reaches -1/2Vp or below, a charge corresponding to a +Vp is fed to the adder. Only the input signal is fed to the integration device when the output is -1/2Vp. Then the feedback loop is operated so that the output of the integration device does not exceed + or -1/2Vp. Since the value is + or -Vp in a conventional circuit, it is expected that thenoise voltage of the converted output is decreased to 1/2. It is known in the noise voltage per unit band width of a delta sigma modulator that it is proportional to fc<3/2> when the maximum input voltage is constant, where fc is the sampling frequency. Thus, the clock frequency is decreased to 1/2<2/3> to obtain the same noise level by using the device of this invention.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for encoding a low frequency analog signal into a relatively high speed digital signal.

(Prior art and its problems) Conventionally, when converting a low-frequency analog signal into a digital signal, high-resolution A/D conversion is performed at a sampling frequency that is approximately two to three times the maximum frequency of the analog signal to be converted. It was normal.

At this time, signals with a frequency higher than 1/2 of the sampling frequency are mixed into the digital signal as noise, so
At the time of conversion, A/D conversion has been performed after sufficiently attenuating signals of 1/2 or more of the sampling frequency through a high-precision band-limiting filter. However, it is extremely difficult to make this band-limiting filter with high precision. Therefore, in recent years, a method has been studied in which A/D conversion is performed using a simple A/D converter at a sampling frequency sufficiently higher than the signal frequency, and then only the signal components are extracted using a digital filter. The digital filter has Crota sigma modulation. As shown in the block diagram in FIG. 1, delta-sigma modulation consists of an analog adder 2, an integrator 3, a voltage comparator 4,
This is realized by connecting the reference voltage generators 6 in series to form a loop. Here, the reference voltage generator generates a voltage designed as the minimum voltage value of the input signal as the reference voltage when the code output of terminal 5 is "1", and when the code output is 10", the voltage is the maximum value of the input signal. Generates a voltage designed as

Its operation is to add the voltage input from input terminal 1 and the voltage output from reference voltage generator 6, and compare the accumulated result with the voltage that has been integrated by integrator 3 up to that point using a comparator. If it is negative, it outputs "0".

In this way, one bit is encoded. According to this encoding method, for example, a 3.4KHz telephone signal is
In order to encode with bit precision, sampling of several h or more is required, and extremely high-speed operation is required.

OBJECTS OF THE INVENTION A first object of the present invention is to provide a means for reducing this too high locking frequency to 1/27' with a small number of additional elements. This not only simplifies the circuit design of the integrated circuit, but also has the effect of reducing power consumption, which generally increases in proportion to clock frequency, to 1/2.

A second object of the present invention is to provide a circuit configuration suitable for integration.

(Structure of the Invention) The present invention provides a means for inputting a modulated signal and converting it into a charge proportional to this input, and a positive and a negative charge, respectively, with half the amount of charge corresponding to the maximum amplitude of the modulated signal. means for supplying electric charges; and means for integrating and adding these three electric charges with the electric charges stored up to that time and converting the result into a voltage;
means for generating a voltage that is 1/2 of the voltage that is output when only positive charges corresponding to 1/2 of the maximum amplitude are supplied to the means for integrating and adding; and 1/2 of the maximum amplitude;
means for generating a voltage that is 1/2 of the voltage that would be output when only negative charges corresponding to 2 are supplied to the means for integrating and adding; means for comparing voltages, means for comparing the output of the integrating means and the negative 1/2 voltage, and adding the positive and negative 1/2 charges based on the output results from the output stage that compares the two. A differential modulator is characterized in that it has a means for controlling whether or not.

(Detailed explanation of configuration) The basic operation of the present invention will be explained using FIG.

The voltage signal input from the signal input terminal 11# is applied to the adder 12 in the form of a charge by a means 18 for converting it into a charge proportional to the voltage signal. On the other hand, comparators 14-1 and 14-
Charges supplied from means 16-1 and 16-2 for generating positive and negative charges corresponding to a voltage of 1/2 of the maximum input signal amplitude controlled by the output of 2 are also applied to the adder 12. The result of this addition is added to the charge stored up to that point by the integrator 13, and the result is used as a voltage for the comparator 14-
1 and 14-2. The comparator 14-1 determines whether the integrator output voltage is 779 or more when the center of the input maximum amplitude is zero and the maximum value is vp and the minimum value is -Vp. If the value is below, output “0”. The terminal 17-1 is connected to means for generating this p/2. Moreover, the comparator 14-2 is
It is determined whether the integrator output voltage is below 11 vp, and if it is below, it outputs 1'', and if it is above, it outputs O''. The output of this comparator is at terminals 15-1 and 15-2.
The signals are output as codes for digital signal processing, and are also supplied to the means for generating negative and positive charges, respectively. Therefore, when the output of the integrator exceeds l/2Vp, a charge corresponding to -Vp is added to the adder, and -
When it becomes 1/2vp or less, a charge corresponding to +Vp is added to the adder. And the output is from 1 1/2 Vp to 1
At /2Vp only the input signal is fed to the integrator. This feedback loop thus has a ±
It operates so as not to exceed 1/2 Vp. According to the conventional circuit, since this is ±Vp, it can be expected that the noise voltage of the conversion output will be reduced to 1/2. In general, the noise voltage per unit bandwidth of a delta-sigma modulator can be reduced to 1/2 J using this method at the maximum input voltage to obtain a low noise level.

(Embodiment) A more detailed circuit example in which the present invention is integrated into an integrated circuit is shown in FIG. In the figure, numerals 81 to 812 are switch elements driven by clocks φ1 and ψ2, which are opposite in phase and do not conduct at the same time. The signal is input from the terminal 21 and 21 at φ.
It reaches one electrode of the capacitor C1 through a switch S2 connected to and grounded at φ. The other electrode of C1 is grounded at φ1 and connected to the switch S1 connected to the negative input terminal of the operational amplifier 23 at φ1, thereby forming a means for converting the input voltage into a charge proportional to the input voltage.

The outputs 25-1 and 25-2 of the two comparators 24-4 and 24-2 are ANDed by inputting ψ2 to the terminal 37 by the AND gates 40 and 41, respectively, and the outputs 35 and 36 are S3. Drive S4 and the pair S5, S6. At φ1, S3. S
4.85 is grounded, and S6 is connected to a terminal 38 connected to a reference power source. Here, a capacitor C3 is connected between 83 and 84, and a capacitor C3 with a value equal to C2 is connected between 85°S6, and these C2, C, , 83, 84
, 85, and 36 form means for supplying positive and negative charges with 1/2 of the amount of charge corresponding to the maximum voltage amplitude. S3 and S5 are connected to the input end of the operational amplifier circuit when outputs 35 and 36, respectively, become logic 1.

At this time, 84 and 86 are connected to the reference voltage source and ground, respectively. Operational amplifier 23 and C4 constitute a dividing means, as well as C1 and C2C.

When Sl, S, , S conduct the charges of C4
It also plays the role of adding to the top. Here, the amount of charge charged to 31 by C, , C, , C, is -C, V, respectively, where the input voltage is Vl and the IJ reference voltage is Va.

It is represented by C, VR, -C, VR. On the other hand, when there is a change in the charge Q of the integrating circuit, the change in the output voltage appearing at the node 32 is expressed as Δv, =-Q/C4.

Next, to determine whether the output voltage of node 32 exceeds Vp/2, two sets of C5, S7, and S9 connected in series are connected to the input of comparator 24-1, and φ! In the cycle 87 is grounded, and S9 is connected to the terminal 39 connected to the means for supplying the reference voltage. When comparing φ, S7 is connected to the operational amplifier 23, and S9 is connected to the ground side, so that the input Vi of the comparator has an input capacitance Ci and the output of the operational amplifier 2. Then, ■i”” (C2Vl, -Cq ■u)/(Cs +c
, +c i ). The voltage at which the charge of C7 or C3 is transferred as jVo at one time is jVo'=
(Ct/, C4), ■n, so the ratio of C3 and C2 is i:(C,'.C5/2.C4), and the comparison of Vp/2 in the explanation of FIG. 2 can be made.

-Vp/2 comparison has almost the same structure as Vp/2, but when 810 corresponding to S9 is ψ, grounding ψ,
This can be achieved by connecting to VR.

This comparison makes the state determination at the end of the cycle of φ,
The result is output to the outside and also supplied to the AND gate. The signal encoding device can be constructed with a simple structure and is suitable for integrated circuit implementation.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional delta-sigma modulator. 2 is an analog adder, 3 is an integrator, and 4 is a comparator. FIG. 2 shows a circuit according to the present invention, in which 18 is a device for converting voltage into charge;
12 is an adder, 13 is an integrator, and 14-1.14-2 is a comparator. FIG. 3 is a circuit diagram of an embodiment of the present invention embodying the circuit of FIG. 2. 71-1 Figure 72

Claims (1)

[Claims] means for inputting a modulated signal and converting it into a charge proportional to the input; and means for supplying positive and negative charges, respectively, with half the amount of charge corresponding to the maximum voltage amplitude of the modulated signal. , 1/20 of the voltage that is output when these three charges are integrally added to the previously stored charges and only positive charges corresponding thereto are supplied to the means for integrating and adding. and means for generating 1/of the maximum amplitude.
means for generating a voltage that is 1/2 of the voltage that would be output when only negative charges corresponding to 2 are supplied to the means for integrating and adding; A means for comparing voltages, a means for comparing the output of the integrating means and the negative 1/2 voltage, and a means for adding the positive and negative 1/2 charges based on the output results from the means for comparing the two. 1. A differential modulator comprising: means for controlling whether